From: Alexandru Elisei <alexandru.elisei@arm.com>
To: Andre Przywara <andre.przywara@arm.com>,
Andrew Jones <drjones@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>
Cc: Marc Zyngier <maz@kernel.org>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org
Subject: Re: [kvm-unit-tests PATCH 11/17] arm: gic: Check for validity of both group enable bits
Date: Tue, 12 Nov 2019 16:58:05 +0000 [thread overview]
Message-ID: <5f667bf5-7404-4a33-590e-cdf0a432cb8d@arm.com> (raw)
In-Reply-To: <20191108144240.204202-12-andre.przywara@arm.com>
Hi,
On 11/8/19 2:42 PM, Andre Przywara wrote:
> The GIC distributor actually supports *two* enable bits, one per
> interrupt group. Linux itself won't care and will only ever use one bit.
> In a VM however we have two groups available, so we should be able to
> flip the two separate enable bits.
>
> Provide tests that try to flip the two available bits and check whether
> they stick.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> arm/gic.c | 21 +++++++++++++++++++++
> lib/arm/asm/gic-v3.h | 4 ++--
> lib/arm/gic-v3.c | 2 +-
> 3 files changed, 24 insertions(+), 3 deletions(-)
>
> diff --git a/arm/gic.c b/arm/gic.c
> index 485ca4f..a0511e5 100644
> --- a/arm/gic.c
> +++ b/arm/gic.c
> @@ -640,6 +640,8 @@ static void spi_test_smp(void)
> report("SPI delievered on all cores", cores == nr_cpus);
> }
>
> +#define GICD_CTLR_ENABLE_BOTH (GICD_CTLR_ENABLE_G0 | GICD_CTLR_ENABLE_G1)
> +
> /*
> * Check the security state configuration of the GIC.
> * Test whether we can switch to a single security state, to test both
> @@ -694,6 +696,25 @@ static void test_irq_group(void *gicd_base)
> return;
> }
>
> + /* Check whether the group enable bits stick. */
> + reg = readl(gicd_base + GICD_CTLR);
> + writel(reg & ~GICD_CTLR_ENABLE_BOTH, gicd_base + GICD_CTLR);
> + reg = readl(gicd_base + GICD_CTLR);
> + report("both groups disabled sticks",
> + (reg & GICD_CTLR_ENABLE_BOTH) == 0);
> +
> + reg &= ~GICD_CTLR_ENABLE_BOTH;
> + writel(reg | GICD_CTLR_ENABLE_G1, gicd_base + GICD_CTLR);
> + reg = readl(gicd_base + GICD_CTLR);
> + report("group 1 enabled sticks",
> + (reg & GICD_CTLR_ENABLE_BOTH) == GICD_CTLR_ENABLE_G1);
> +
> + reg &= ~GICD_CTLR_ENABLE_BOTH;
> + writel(reg | GICD_CTLR_ENABLE_G0, gicd_base + GICD_CTLR);
> + reg = readl(gicd_base + GICD_CTLR);
> + report("group 0 enabled sticks",
> + (reg & GICD_CTLR_ENABLE_BOTH) == GICD_CTLR_ENABLE_G0);
How about adding a check that enabling both groups at the same time works?
> +
> /*
> * On a security aware GIC in non-secure world the IGROUPR registers
> * are RAZ/WI. KVM emulates a single-security-state GIC, so both
> diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h
> index 2eaf944..0a29610 100644
> --- a/lib/arm/asm/gic-v3.h
> +++ b/lib/arm/asm/gic-v3.h
> @@ -21,8 +21,8 @@
> #define GICD_CTLR_RWP (1U << 31)
> #define GICD_CTLR_DS (1U << 6)
> #define GICD_CTLR_ARE_NS (1U << 4)
> -#define GICD_CTLR_ENABLE_G1A (1U << 1)
> -#define GICD_CTLR_ENABLE_G1 (1U << 0)
> +#define GICD_CTLR_ENABLE_G1 (1U << 1)
> +#define GICD_CTLR_ENABLE_G0 (1U << 0)
Nice cleanup.
>
> #define GICD_IROUTER 0x6000
> #define GICD_PIDR2 0xffe8
> diff --git a/lib/arm/gic-v3.c b/lib/arm/gic-v3.c
> index feecb5e..d6a5186 100644
> --- a/lib/arm/gic-v3.c
> +++ b/lib/arm/gic-v3.c
> @@ -42,7 +42,7 @@ void gicv3_enable_defaults(void)
> writel(0, dist + GICD_CTLR);
> gicv3_dist_wait_for_rwp();
>
> - writel(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
> + writel(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G0 | GICD_CTLR_ENABLE_G1,
> dist + GICD_CTLR);
> gicv3_dist_wait_for_rwp();
>
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next prev parent reply other threads:[~2019-11-12 16:58 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-08 14:42 [kvm-unit-tests PATCH 00/17] arm: gic: Test SPIs and interrupt groups Andre Przywara
2019-11-08 14:42 ` [kvm-unit-tests PATCH 01/17] arm: gic: Enable GIC MMIO tests for GICv3 as well Andre Przywara
2019-11-08 17:28 ` Alexandru Elisei
2019-11-12 12:49 ` Auger Eric
2019-11-08 14:42 ` [kvm-unit-tests PATCH 02/17] arm: gic: Generalise function names Andre Przywara
2019-11-12 11:11 ` Alexandru Elisei
2019-11-12 12:49 ` Auger Eric
2019-11-08 14:42 ` [kvm-unit-tests PATCH 03/17] arm: gic: Provide per-IRQ helper functions Andre Przywara
2019-11-12 12:51 ` Alexandru Elisei
2019-11-12 15:53 ` Auger Eric
2019-11-12 16:53 ` Alexandru Elisei
2019-11-12 13:49 ` Auger Eric
2019-11-08 14:42 ` [kvm-unit-tests PATCH 04/17] arm: gic: Support no IRQs test case Andre Przywara
2019-11-12 13:26 ` Alexandru Elisei
2019-11-12 21:14 ` Auger Eric
2019-11-08 14:42 ` [kvm-unit-tests PATCH 05/17] arm: gic: Prepare IRQ handler for handling SPIs Andre Przywara
2019-11-12 13:36 ` Alexandru Elisei
2019-11-12 20:56 ` Auger Eric
2019-11-08 14:42 ` [kvm-unit-tests PATCH 06/17] arm: gic: Add simple shared IRQ test Andre Przywara
2019-11-12 13:54 ` Alexandru Elisei
2019-11-08 14:42 ` [kvm-unit-tests PATCH 07/17] arm: gic: Extend check_acked() to allow silent call Andre Przywara
2019-11-12 15:23 ` Alexandru Elisei
2019-11-14 12:32 ` Andrew Jones
2019-11-15 11:32 ` Alexandru Elisei
2019-11-08 14:42 ` [kvm-unit-tests PATCH 08/17] arm: gic: Add simple SPI MP test Andre Przywara
2019-11-12 15:41 ` Alexandru Elisei
2019-11-08 14:42 ` [kvm-unit-tests PATCH 09/17] arm: gic: Add test for flipping GICD_CTLR.DS Andre Przywara
2019-11-12 16:42 ` Alexandru Elisei
2019-11-14 13:39 ` Vladimir Murzin
2019-11-14 14:17 ` Andre Przywara
2019-11-14 14:50 ` Vladimir Murzin
2019-11-14 15:21 ` Alexandru Elisei
2019-11-14 15:27 ` Peter Maydell
2019-11-14 15:47 ` Alexandru Elisei
2019-11-14 15:56 ` Peter Maydell
2019-11-08 14:42 ` [kvm-unit-tests PATCH 10/17] arm: gic: Check for writable IGROUPR registers Andre Przywara
2019-11-12 16:51 ` Alexandru Elisei
2019-11-08 14:42 ` [kvm-unit-tests PATCH 11/17] arm: gic: Check for validity of both group enable bits Andre Przywara
2019-11-12 16:58 ` Alexandru Elisei [this message]
2019-11-08 14:42 ` [kvm-unit-tests PATCH 12/17] arm: gic: Change gic_read_iar() to take group parameter Andre Przywara
2019-11-12 17:19 ` Alexandru Elisei
2019-11-14 12:50 ` Andrew Jones
2019-11-08 14:42 ` [kvm-unit-tests PATCH 13/17] arm: gic: Change write_eoir() " Andre Przywara
2019-11-08 14:42 ` [kvm-unit-tests PATCH 14/17] arm: gic: Prepare for receiving GIC group 0 interrupts via FIQs Andre Przywara
2019-11-12 17:30 ` Alexandru Elisei
2019-11-08 14:42 ` [kvm-unit-tests PATCH 15/17] arm: gic: Provide FIQ handler Andre Przywara
2019-11-13 10:14 ` Alexandru Elisei
2019-11-08 14:42 ` [kvm-unit-tests PATCH 16/17] arm: gic: Prepare interrupt statistics for both groups Andre Przywara
2019-11-13 10:44 ` Alexandru Elisei
2019-11-08 14:42 ` [kvm-unit-tests PATCH 17/17] arm: gic: Test Group0 SPIs Andre Przywara
2019-11-13 11:26 ` Alexandru Elisei
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