From: Alexandru Elisei <alexandru.elisei@arm.com>
To: Andre Przywara <andre.przywara@arm.com>,
Andrew Jones <drjones@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>
Cc: Marc Zyngier <maz@kernel.org>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org
Subject: Re: [kvm-unit-tests PATCH 01/17] arm: gic: Enable GIC MMIO tests for GICv3 as well
Date: Fri, 8 Nov 2019 17:28:38 +0000 [thread overview]
Message-ID: <cc2a6815-89f7-4a3a-1d7f-9b834c064486@arm.com> (raw)
In-Reply-To: <20191108144240.204202-2-andre.przywara@arm.com>
Hi Andre,
On 11/8/19 2:42 PM, Andre Przywara wrote:
> So far the GIC MMIO tests were only enabled for a GICv2 guest. Modern
> machines tend to have a GICv3-only GIC, so can't run those tests.
> It turns out that most GIC distributor registers we test in the unit
> tests are actually the same in GICv3, so we can just enable those tests
> for GICv3 guests as well.
> The only exception is the CPU number in the TYPER register, which is
> only valid in the GICv2 compat mode (ARE=0), which KVM does not support.
> So we protect this test against running on a GICv3 guest.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> arm/gic.c | 13 +++++++++++--
> arm/unittests.cfg | 26 ++++++++++++++++++++++----
> lib/arm/asm/gic-v3.h | 2 ++
> 3 files changed, 35 insertions(+), 6 deletions(-)
>
> diff --git a/arm/gic.c b/arm/gic.c
> index adb6aa4..04b3337 100644
> --- a/arm/gic.c
> +++ b/arm/gic.c
> @@ -6,6 +6,7 @@
> * + MMIO access tests
> * GICv3
> * + test sending/receiving IPIs
> + * + MMIO access tests
> *
> * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> *
> @@ -496,7 +497,14 @@ static void gic_test_mmio(void)
> idreg = gic_dist_base + GICD_ICPIDR2;
> break;
> case 0x3:
> - report_abort("GICv3 MMIO tests NYI");
> + /*
> + * We only test generic registers or those affecting
> + * SPIs, so don't need to consider the SGI base in
> + * the redistributor here.
> + */
> + gic_dist_base = gicv3_dist_base();
> + idreg = gic_dist_base + GICD_PIDR2;
> + break;
> default:
> report_abort("GIC version %d not supported", gic_version());
> }
> @@ -505,7 +513,8 @@ static void gic_test_mmio(void)
> nr_irqs = GICD_TYPER_IRQS(reg);
> report_info("number of implemented SPIs: %d", nr_irqs - GIC_FIRST_SPI);
>
> - test_typer_v2(reg);
> + if (gic_version() == 0x2)
> + test_typer_v2(reg);
>
> report_info("IIDR: 0x%08x", readl(gic_dist_base + GICD_IIDR));
More context:
@@ -489,30 +490,38 @@ static void gic_test_mmio(void)
u32 reg;
int nr_irqs;
void *gic_dist_base, *idreg;
switch(gic_version()) {
case 0x2:
gic_dist_base = gicv2_dist_base();
idreg = gic_dist_base + GICD_ICPIDR2;
break;
case 0x3:
- report_abort("GICv3 MMIO tests NYI");
+ /*
+ * We only test generic registers or those affecting
+ * SPIs, so don't need to consider the SGI base in
+ * the redistributor here.
+ */
+ gic_dist_base = gicv3_dist_base();
+ idreg = gic_dist_base + GICD_PIDR2;
+ break;
default:
report_abort("GIC version %d not supported", gic_version());
}
reg = readl(gic_dist_base + GICD_TYPER);
nr_irqs = GICD_TYPER_IRQS(reg);
report_info("number of implemented SPIs: %d", nr_irqs - GIC_FIRST_SPI);
- test_typer_v2(reg);
+ if (gic_version() == 0x2)
+ test_typer_v2(reg);
report_info("IIDR: 0x%08x", readl(gic_dist_base + GICD_IIDR));
report("GICD_TYPER is read-only",
test_readonly_32(gic_dist_base + GICD_TYPER, false));
report("GICD_IIDR is read-only",
test_readonly_32(gic_dist_base + GICD_IIDR, false));
reg = readl(idreg);
report("ICPIDR2 is read-only", test_readonly_32(idreg, false));
In the case of GICv3, the register is GICD_PIDR2, not ICPIDR2. You can probably
use a different variable to store the identification register name.
>
> diff --git a/arm/unittests.cfg b/arm/unittests.cfg
> index daeb5a0..12ac142 100644
> --- a/arm/unittests.cfg
> +++ b/arm/unittests.cfg
> @@ -86,28 +86,46 @@ smp = $((($MAX_SMP < 8)?$MAX_SMP:8))
> extra_params = -machine gic-version=2 -append 'ipi'
> groups = gic
>
> -[gicv2-mmio]
> +[gicv3-ipi]
> +file = gic.flat
> +smp = $MAX_SMP
> +extra_params = -machine gic-version=3 -append 'ipi'
> +groups = gic
> +
> +[gicv2-max-mmio]
The renaming is not mentioned in the commit message. If you want to rename these
tests, can you rename them to gic{v2,v3}-mmio-max so they're consistent with the
other test names?
Thanks,
Alex
> file = gic.flat
> smp = $((($MAX_SMP < 8)?$MAX_SMP:8))
> extra_params = -machine gic-version=2 -append 'mmio'
> groups = gic
>
> +[gicv3-max-mmio]
> +file = gic.flat
> +smp = $MAX_SMP
> +extra_params = -machine gic-version=3 -append 'mmio'
> +groups = gic
> +
> [gicv2-mmio-up]
> file = gic.flat
> smp = 1
> extra_params = -machine gic-version=2 -append 'mmio'
> groups = gic
>
> +[gicv3-mmio-up]
> +file = gic.flat
> +smp = 1
> +extra_params = -machine gic-version=3 -append 'mmio'
> +groups = gic
> +
> [gicv2-mmio-3p]
> file = gic.flat
> smp = $((($MAX_SMP < 3)?$MAX_SMP:3))
> extra_params = -machine gic-version=2 -append 'mmio'
> groups = gic
>
> -[gicv3-ipi]
> +[gicv3-mmio-3p]
> file = gic.flat
> -smp = $MAX_SMP
> -extra_params = -machine gic-version=3 -append 'ipi'
> +smp = $((($MAX_SMP < 3)?$MAX_SMP:3))
> +extra_params = -machine gic-version=2 -append 'mmio'
> groups = gic
>
> [gicv2-active]
> diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h
> index 347be2f..ed6a5ad 100644
> --- a/lib/arm/asm/gic-v3.h
> +++ b/lib/arm/asm/gic-v3.h
> @@ -23,6 +23,8 @@
> #define GICD_CTLR_ENABLE_G1A (1U << 1)
> #define GICD_CTLR_ENABLE_G1 (1U << 0)
>
> +#define GICD_PIDR2 0xffe8
> +
> /* Re-Distributor registers, offsets from RD_base */
> #define GICR_TYPER 0x0008
>
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next prev parent reply other threads:[~2019-11-08 17:28 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-08 14:42 [kvm-unit-tests PATCH 00/17] arm: gic: Test SPIs and interrupt groups Andre Przywara
2019-11-08 14:42 ` [kvm-unit-tests PATCH 01/17] arm: gic: Enable GIC MMIO tests for GICv3 as well Andre Przywara
2019-11-08 17:28 ` Alexandru Elisei [this message]
2019-11-12 12:49 ` Auger Eric
2019-11-08 14:42 ` [kvm-unit-tests PATCH 02/17] arm: gic: Generalise function names Andre Przywara
2019-11-12 11:11 ` Alexandru Elisei
2019-11-12 12:49 ` Auger Eric
2019-11-08 14:42 ` [kvm-unit-tests PATCH 03/17] arm: gic: Provide per-IRQ helper functions Andre Przywara
2019-11-12 12:51 ` Alexandru Elisei
2019-11-12 15:53 ` Auger Eric
2019-11-12 16:53 ` Alexandru Elisei
2019-11-12 13:49 ` Auger Eric
2019-11-08 14:42 ` [kvm-unit-tests PATCH 04/17] arm: gic: Support no IRQs test case Andre Przywara
2019-11-12 13:26 ` Alexandru Elisei
2019-11-12 21:14 ` Auger Eric
2019-11-08 14:42 ` [kvm-unit-tests PATCH 05/17] arm: gic: Prepare IRQ handler for handling SPIs Andre Przywara
2019-11-12 13:36 ` Alexandru Elisei
2019-11-12 20:56 ` Auger Eric
2019-11-08 14:42 ` [kvm-unit-tests PATCH 06/17] arm: gic: Add simple shared IRQ test Andre Przywara
2019-11-12 13:54 ` Alexandru Elisei
2019-11-08 14:42 ` [kvm-unit-tests PATCH 07/17] arm: gic: Extend check_acked() to allow silent call Andre Przywara
2019-11-12 15:23 ` Alexandru Elisei
2019-11-14 12:32 ` Andrew Jones
2019-11-15 11:32 ` Alexandru Elisei
2019-11-08 14:42 ` [kvm-unit-tests PATCH 08/17] arm: gic: Add simple SPI MP test Andre Przywara
2019-11-12 15:41 ` Alexandru Elisei
2019-11-08 14:42 ` [kvm-unit-tests PATCH 09/17] arm: gic: Add test for flipping GICD_CTLR.DS Andre Przywara
2019-11-12 16:42 ` Alexandru Elisei
2019-11-14 13:39 ` Vladimir Murzin
2019-11-14 14:17 ` Andre Przywara
2019-11-14 14:50 ` Vladimir Murzin
2019-11-14 15:21 ` Alexandru Elisei
2019-11-14 15:27 ` Peter Maydell
2019-11-14 15:47 ` Alexandru Elisei
2019-11-14 15:56 ` Peter Maydell
2019-11-08 14:42 ` [kvm-unit-tests PATCH 10/17] arm: gic: Check for writable IGROUPR registers Andre Przywara
2019-11-12 16:51 ` Alexandru Elisei
2019-11-08 14:42 ` [kvm-unit-tests PATCH 11/17] arm: gic: Check for validity of both group enable bits Andre Przywara
2019-11-12 16:58 ` Alexandru Elisei
2019-11-08 14:42 ` [kvm-unit-tests PATCH 12/17] arm: gic: Change gic_read_iar() to take group parameter Andre Przywara
2019-11-12 17:19 ` Alexandru Elisei
2019-11-14 12:50 ` Andrew Jones
2019-11-08 14:42 ` [kvm-unit-tests PATCH 13/17] arm: gic: Change write_eoir() " Andre Przywara
2019-11-08 14:42 ` [kvm-unit-tests PATCH 14/17] arm: gic: Prepare for receiving GIC group 0 interrupts via FIQs Andre Przywara
2019-11-12 17:30 ` Alexandru Elisei
2019-11-08 14:42 ` [kvm-unit-tests PATCH 15/17] arm: gic: Provide FIQ handler Andre Przywara
2019-11-13 10:14 ` Alexandru Elisei
2019-11-08 14:42 ` [kvm-unit-tests PATCH 16/17] arm: gic: Prepare interrupt statistics for both groups Andre Przywara
2019-11-13 10:44 ` Alexandru Elisei
2019-11-08 14:42 ` [kvm-unit-tests PATCH 17/17] arm: gic: Test Group0 SPIs Andre Przywara
2019-11-13 11:26 ` Alexandru Elisei
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