From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org,
ira.weiny@intel.com, vishal.l.verma@intel.com,
alison.schofield@intel.com, dan.j.williams@intel.com,
linux-kernel@vger.kernel.org
Subject: [PATCH v2] cxl/mem: Fix register block offset calculation
Date: Thu, 15 Apr 2021 19:49:12 -0700 [thread overview]
Message-ID: <20210416024912.638180-1-ben.widawsky@intel.com> (raw)
In-Reply-To: <20210415232610.603273-1-ben.widawsky@intel.com>
The offset for the register block should be a 64K aligned value, and
therefore FIELD_GET (which will shift) is not correct for the
calculation.
From 8.1.9.1 of the CXL 2.0 spec:
A[31:16] of offset from the address contained by one of the Function's
Base Address Registers to point to the base of the Register Block.
Register Block Offset is 64K aligned. Hence A[15:0] is zero
The "Register Offset Low" register of a "DVSEC Register Locator"
contains the 64K aligned offset for the registers along with the BAR
indicator and an ID. The implementation was treating the "Register Block
Offset Low" field a value rather than as a pre-aligned component of the
64-bit offset. So, just mask, don't mask and shift (FIELD_GET).
This wasn't found earlier because the primary development done in the
QEMU environment only uses 0 offsets
Fixes: 8adaf747c9f0 ("cxl/mem: Find device capabilities")
Reported-by: Vishal Verma <vishal.l.verma@intel.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
drivers/cxl/mem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index e3003f49b329..1b5078311f7d 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -998,7 +998,7 @@ static struct cxl_mem *cxl_mem_create(struct pci_dev *pdev, u32 reg_lo,
return NULL;
}
- offset = ((u64)reg_hi << 32) | FIELD_GET(CXL_REGLOC_ADDR_MASK, reg_lo);
+ offset = ((u64)reg_hi << 32) | (reg_lo & CXL_REGLOC_ADDR_MASK);
bar = FIELD_GET(CXL_REGLOC_BIR_MASK, reg_lo);
/* Basic sanity check that BAR is big enough */
--
2.31.1
prev parent reply other threads:[~2021-04-16 2:49 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-15 23:26 [PATCH 1/3] cxl/mem: Fix register block offset calculation Ben Widawsky
2021-04-15 23:26 ` [PATCH 2/3] cxl/mem: Print unknown capability IDs as hex Ben Widawsky
2021-04-15 23:34 ` Verma, Vishal L
2021-04-15 23:26 ` [PATCH 3/3] cxl/mem: Demarcate vendor specific capability IDs Ben Widawsky
2021-04-15 23:27 ` Ben Widawsky
2021-04-15 23:37 ` Verma, Vishal L
2021-04-15 23:50 ` Ben Widawsky
2021-05-19 20:01 ` Dan Williams
2021-04-16 0:29 ` Dan Williams
2021-04-16 0:03 ` [PATCH 1/3] cxl/mem: Fix register block offset calculation Dan Williams
2021-04-16 2:49 ` Ben Widawsky [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210416024912.638180-1-ben.widawsky@intel.com \
--to=ben.widawsky@intel.com \
--cc=alison.schofield@intel.com \
--cc=dan.j.williams@intel.com \
--cc=ira.weiny@intel.com \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=vishal.l.verma@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).