From: Dan Williams <dan.j.williams@intel.com>
To: Ben Widawsky <ben.widawsky@intel.com>
Cc: linux-cxl@vger.kernel.org, Linux PCI <linux-pci@vger.kernel.org>,
Linux ACPI <linux-acpi@vger.kernel.org>,
"Weiny, Ira" <ira.weiny@intel.com>,
Vishal L Verma <vishal.l.verma@intel.com>,
"Schofield, Alison" <alison.schofield@intel.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/3] cxl/mem: Fix register block offset calculation
Date: Thu, 15 Apr 2021 17:03:17 -0700 [thread overview]
Message-ID: <CAPcyv4iSUfHuzm+4ttA2RgH5Z7xXrLRnkXRLD=8XUtLb2G0-fw@mail.gmail.com> (raw)
In-Reply-To: <20210415232610.603273-1-ben.widawsky@intel.com>
On Thu, Apr 15, 2021 at 4:26 PM Ben Widawsky <ben.widawsky@intel.com> wrote:
>
> The offset for the register block should be a 64K aligned value, and
> therefore FIELD_GET (which will shift) is not correct for the
> calculation.
>
> From 8.1.9.1 of the CXL 2.0 spec:
> A[31:16] of offset from the address contained by one of the Function's
> Base Address Registers to point to the base of the Register Block.
> Register Block Offset is 64K aligned. Hence A[15:0] is zero
>
> Fix this by simply using a mask.
The above reads slightly funny to me, is this any clearer?
The "Register Offset Low" register of a "DVSEC Register Locator"
contains the 64K aligned offset for the registers along with the BAR
indicator and an id. The implementation was treating the "Register
Block Offset Low" field a value rather than as a pre-aligned component
of the 64-bit offset. So, just mask, don't mask and shift (FIELD_GET).
>
> This wasn't found earlier because the primary development done in the
> QEMU environment only uses 0 offsets
>
> Fixes: 8adaf747c9f0b ("cxl/mem: Find device capabilities")
As I've learned, linux-next will flag this as the wrong format.
Fixes: 8adaf747c9f0 ("cxl/mem: Find device capabilities")
...i.e. looks like your core.abbrev setting is 13 rather than 12 per
Documentation/process/submitting-patches.rst
Other than that, fix looks good to me.
> Reported-by: Vishal Verma <vishal.l.verma@intel.com>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> ---
> drivers/cxl/mem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index e3003f49b329..1b5078311f7d 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -998,7 +998,7 @@ static struct cxl_mem *cxl_mem_create(struct pci_dev *pdev, u32 reg_lo,
> return NULL;
> }
>
> - offset = ((u64)reg_hi << 32) | FIELD_GET(CXL_REGLOC_ADDR_MASK, reg_lo);
> + offset = ((u64)reg_hi << 32) | (reg_lo & CXL_REGLOC_ADDR_MASK);
> bar = FIELD_GET(CXL_REGLOC_BIR_MASK, reg_lo);
>
> /* Basic sanity check that BAR is big enough */
> --
> 2.31.1
next prev parent reply other threads:[~2021-04-16 0:03 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-15 23:26 [PATCH 1/3] cxl/mem: Fix register block offset calculation Ben Widawsky
2021-04-15 23:26 ` [PATCH 2/3] cxl/mem: Print unknown capability IDs as hex Ben Widawsky
2021-04-15 23:34 ` Verma, Vishal L
2021-04-15 23:26 ` [PATCH 3/3] cxl/mem: Demarcate vendor specific capability IDs Ben Widawsky
2021-04-15 23:27 ` Ben Widawsky
2021-04-15 23:37 ` Verma, Vishal L
2021-04-15 23:50 ` Ben Widawsky
2021-05-19 20:01 ` Dan Williams
2021-04-16 0:29 ` Dan Williams
2021-04-16 0:03 ` Dan Williams [this message]
2021-04-16 2:49 ` [PATCH v2] cxl/mem: Fix register block offset calculation Ben Widawsky
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