From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Joseph Lo <josephl@nvidia.com>
Subject: [PATCH 05/19] clk: tegra: dfll: registration for multiple SoCs
Date: Tue, 4 Dec 2018 17:25:34 +0800 [thread overview]
Message-ID: <20181204092548.3038-6-josephl@nvidia.com> (raw)
In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com>
From: Peter De Schrijver <pdeschrijver@nvidia.com>
In a future patch, support for the DFLL in Tegra210 will be introduced.
This requires support for more than 1 set of CVB and CPU max frequency
tables.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 45 ++++++++++++++++------
1 file changed, 34 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
index 269d3595758b..1a2cc113e5c8 100644
--- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
+++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
@@ -1,7 +1,7 @@
/*
* Tegra124 DFLL FCPU clock source driver
*
- * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved.
+ * Copyright (C) 2012-2018 NVIDIA Corporation. All rights reserved.
*
* Aleksandr Frid <afrid@nvidia.com>
* Paul Walmsley <pwalmsley@nvidia.com>
@@ -21,6 +21,7 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <soc/tegra/fuse.h>
@@ -28,8 +29,15 @@
#include "clk-dfll.h"
#include "cvb.h"
+struct dfll_fcpu_data {
+ const unsigned long *cpu_max_freq_table;
+ unsigned int cpu_max_freq_table_size;
+ const struct cvb_table *cpu_cvb_tables;
+ unsigned int cpu_cvb_tables_size;
+};
+
/* Maximum CPU frequency, indexed by CPU speedo id */
-static const unsigned long cpu_max_freq_table[] = {
+static const unsigned long tegra124_cpu_max_freq_table[] = {
[0] = 2014500000UL,
[1] = 2320500000UL,
[2] = 2116500000UL,
@@ -82,16 +90,36 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = {
},
};
+static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
+ .cpu_max_freq_table = tegra124_cpu_max_freq_table,
+ .cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table),
+ .cpu_cvb_tables = tegra124_cpu_cvb_tables,
+ .cpu_cvb_tables_size = ARRAY_SIZE(tegra124_cpu_cvb_tables)
+};
+
+static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
+ {
+ .compatible = "nvidia,tegra124-dfll",
+ .data = &tegra124_dfll_fcpu_data,
+ },
+ { },
+};
+
static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
{
int process_id, speedo_id, speedo_value, err;
struct tegra_dfll_soc_data *soc;
+ const struct dfll_fcpu_data *fcpu_data;
+
+ fcpu_data = of_device_get_match_data(&pdev->dev);
+ if (!fcpu_data)
+ return -ENODEV;
process_id = tegra_sku_info.cpu_process_id;
speedo_id = tegra_sku_info.cpu_speedo_id;
speedo_value = tegra_sku_info.cpu_speedo_value;
- if (speedo_id >= ARRAY_SIZE(cpu_max_freq_table)) {
+ if (speedo_id >= fcpu_data->cpu_max_freq_table_size) {
dev_err(&pdev->dev, "unknown max CPU freq for speedo_id=%d\n",
speedo_id);
return -ENODEV;
@@ -107,10 +135,10 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
return -ENODEV;
}
- soc->max_freq = cpu_max_freq_table[speedo_id];
+ soc->max_freq = fcpu_data->cpu_max_freq_table[speedo_id];
- soc->cvb = tegra_cvb_add_opp_table(soc->dev, tegra124_cpu_cvb_tables,
- ARRAY_SIZE(tegra124_cpu_cvb_tables),
+ soc->cvb = tegra_cvb_add_opp_table(soc->dev, fcpu_data->cpu_cvb_tables,
+ fcpu_data->cpu_cvb_tables_size,
process_id, speedo_id, speedo_value,
soc->max_freq);
if (IS_ERR(soc->cvb)) {
@@ -142,11 +170,6 @@ static int tegra124_dfll_fcpu_remove(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
- { .compatible = "nvidia,tegra124-dfll", },
- { },
-};
-
static const struct dev_pm_ops tegra124_dfll_pm_ops = {
SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend,
tegra_dfll_runtime_resume, NULL)
--
2.19.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2018-12-04 9:29 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-04 9:25 [PATCH 00/19] Tegra210 DFLL support Joseph Lo
2018-12-04 9:25 ` [PATCH 01/19] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2018-12-07 13:41 ` Jon Hunter
2018-12-10 8:49 ` Joseph Lo
2018-12-10 8:59 ` Jon Hunter
2018-12-10 9:31 ` Joseph Lo
2018-12-10 9:44 ` Jon Hunter
2018-12-11 1:28 ` Joseph Lo
2018-12-11 9:16 ` Peter De Schrijver
2018-12-11 9:36 ` Joseph Lo
2018-12-11 9:15 ` Peter De Schrijver
2018-12-11 11:52 ` Jon Hunter
2018-12-12 1:52 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 02/19] dt-bindings: clock: tegra124-dfll: add Tegra210 support Joseph Lo
2018-12-07 13:50 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 03/19] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2018-12-04 15:36 ` Peter De Schrijver
2018-12-05 3:05 ` Joseph Lo
2018-12-05 9:37 ` Peter De Schrijver
2018-12-07 13:52 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 04/19] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
2018-12-04 15:37 ` Peter De Schrijver
2018-12-05 3:10 ` Joseph Lo
2018-12-07 13:53 ` Jon Hunter
2018-12-04 9:25 ` Joseph Lo [this message]
2018-12-07 13:55 ` [PATCH 05/19] clk: tegra: dfll: registration for multiple SoCs Jon Hunter
2018-12-04 9:25 ` [PATCH 06/19] clk: tegra: dfll: CVB calculation alignment with the regulator Joseph Lo
2018-12-07 14:10 ` Jon Hunter
2018-12-11 6:23 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 07/19] clk: tegra: dfll: support PWM regulator control Joseph Lo
2018-12-04 15:53 ` Peter De Schrijver
2018-12-05 6:14 ` Joseph Lo
2018-12-07 14:26 ` Jon Hunter
2018-12-11 6:36 ` Joseph Lo
2018-12-07 15:09 ` Jon Hunter
2018-12-11 6:37 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 08/19] clk: tegra: dfll: round down voltages based on alignment Joseph Lo
2018-12-04 15:46 ` Peter De Schrijver
2018-12-05 6:20 ` Joseph Lo
2018-12-05 6:51 ` Joseph Lo
2018-12-05 9:11 ` Peter De Schrijver
2018-12-05 9:30 ` Joseph Lo
2018-12-07 14:34 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 09/19] clk: tegra: dfll: add CVB tables for Tegra210 Joseph Lo
2018-12-07 14:39 ` Jon Hunter
2018-12-11 7:34 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 10/19] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Joseph Lo
2018-12-07 14:40 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 11/19] cpufreq: tegra124: do not handle the CPU rail Joseph Lo
2018-12-07 14:49 ` Jon Hunter
2018-12-11 8:48 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 12/19] cpufreq: tegra124: extend to support Tegra210 Joseph Lo
2018-12-04 9:30 ` Viresh Kumar
2018-12-04 11:22 ` Dmitry Osipenko
2018-12-05 3:25 ` Joseph Lo
2018-12-07 14:50 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 13/19] arm64: dts: tegra210: add DFLL clock Joseph Lo
2018-12-07 14:54 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 14/19] arm64: dts: tegra210: add CPU clocks Joseph Lo
2018-12-07 14:54 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 15/19] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Joseph Lo
2018-12-07 14:55 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 16/19] arm64: dts: tegra210-p2371-2180: enable DFLL clock Joseph Lo
2018-12-07 14:57 ` Jon Hunter
2018-12-11 8:52 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 17/19] arm64: dts: tegra210-smaug: add CPU power rail regulator Joseph Lo
2018-12-07 15:03 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 18/19] arm64: dts: tegra210-smaug: enable DFLL clock Joseph Lo
2018-12-07 15:03 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 19/19] arm64: defconfig: Enable MAX8973 regulator Joseph Lo
2018-12-07 15:04 ` Jon Hunter
2018-12-04 15:10 ` [PATCH 00/19] Tegra210 DFLL support Thierry Reding
2018-12-05 6:11 ` Joseph Lo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181204092548.3038-6-josephl@nvidia.com \
--to=josephl@nvidia.com \
--cc=jonathanh@nvidia.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=pdeschrijver@nvidia.com \
--cc=thierry.reding@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).