From: Jagan Teki <jagan@amarulasolutions.com>
To: Maxime Ripard <maxime.ripard@bootlin.com>,
Chen-Yu Tsai <wens@csie.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-sunxi <linux-sunxi@googlegroups.com>,
Jagan Teki <jagan@amarulasolutions.com>,
Michael Trimarchi <michael@amarulasolutions.com>,
linux-amarula@amarulasolutions.com, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 12/17] drm/sun4i: sun6i_mipi_dsi: Set proper vblk timing calculation
Date: Mon, 10 Dec 2018 21:47:24 +0530 [thread overview]
Message-ID: <20181210161729.29720-13-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20181210161729.29720-1-jagan@amarulasolutions.com>
Unlike hblk, the vblk timings should follow an equation to compute
the desired value for lane 4 devices and rest of devices it would be 0.
BSP code from BPI-M64-bsp is computing vblk as for 4-lane devices
(from linux-sunxi
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
tmp = (ht*dsi_pixel_bits[format]/8)*vt-(4+dsi_hblk+2);
dsi_vblk = (lane-tmp%lane);
So, update the vblk timing calculation accordingly.
Tested on 2-lane, 4-lane MIPI-DSI LCD panels.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 29 +++++++++++++++++++-------
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index d8947be92f9d..cbcef7bf7681 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -355,6 +355,27 @@ static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi,
SUN6I_DSI_INST_JUMP_CFG_NUM(1));
};
+static u16 sun6i_dsi_get_timings_vblk(struct sun6i_dsi *dsi,
+ struct drm_display_mode *mode, u16 hblk)
+{
+ struct mipi_dsi_device *device = dsi->device;
+ unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8;
+ int tmp;
+
+ if (device->lanes != 4)
+ return 0;
+
+ /*
+ * The vertical blank is set using a blanking packet (4 bytes +
+ * payload + 2 bytes). Its minimal size is therefore 6 bytes
+ */
+#define VBLK_PACKET_OVERHEAD 6
+ tmp = (mode->htotal * Bpp) * mode->vtotal -
+ (hblk + VBLK_PACKET_OVERHEAD);
+
+ return (device->lanes - tmp % device->lanes);
+}
+
static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi,
struct drm_display_mode *mode)
{
@@ -503,13 +524,7 @@ static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi,
(mode->htotal - (mode->hsync_end - mode->hsync_start)) *
Bpp - HBLK_PACKET_OVERHEAD);
- /*
- * And I'm not entirely sure what vblk is about. The driver in
- * Allwinner BSP is using a rather convoluted calculation
- * there only for 4 lanes. However, using 0 (the !4 lanes
- * case) even with a 4 lanes screen seems to work...
- */
- vblk = 0;
+ vblk = sun6i_dsi_get_timings_vblk(dsi, mode, hblk);
/* How many bytes do we need to send all payloads? */
bytes = max_t(size_t, max(max(hfp, hblk), max(hsa, hbp)), vblk);
--
2.18.0.321.gffc6fa0e3
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next prev parent reply other threads:[~2018-12-10 16:21 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-10 16:17 [PATCH v5 00/17] drm/sun4i: Allwinner A64 MIPI-DSI support Jagan Teki
2018-12-10 16:17 ` [PATCH v5 01/17] clk: sunxi-ng: Add check for minimal rate to NKM PLLs Jagan Teki
2018-12-10 16:17 ` [PATCH v5 02/17] drm/sun4i: sun6i_mipi_dsi: Add has_mod_clk quirk Jagan Teki
2018-12-10 16:17 ` [PATCH v5 03/17] drm/sun4i: sun6i_mipi_dsi: Add Allwinner A64 MIPI DSI support Jagan Teki
2018-12-10 16:17 ` [PATCH v5 04/17] dt-bindings: sun6i-dsi: Add compatible for A64 MIPI DSI Jagan Teki
2018-12-10 16:17 ` [PATCH v5 05/17] drm/sun4i: sun6i_mipi_dsi: Add DSI Generic short write 2 param transfer Jagan Teki
2018-12-10 16:17 ` [PATCH v5 06/17] drm/sun4i: sun6i_mipi_dsi: Fix TCON DRQ set bits Jagan Teki
2018-12-10 16:17 ` [PATCH v5 07/17] drm/sun4i: sun6i_mipi_dsi: Refactor vertical video start delay Jagan Teki
2018-12-11 16:49 ` Maxime Ripard
2018-12-11 17:00 ` Jagan Teki
2018-12-12 19:43 ` Jagan Teki
2018-12-19 15:50 ` Maxime Ripard
2018-12-20 20:56 ` Jagan Teki
2019-01-06 16:29 ` Jagan Teki
2019-01-07 14:11 ` Maxime Ripard
2019-01-07 15:18 ` Jagan Teki
2019-01-08 8:58 ` Maxime Ripard
[not found] ` <CAMty3ZC9OQtwT-iH=S1LhHsBPc_jFKGAnCYYeR9nuKuDWSKLQw@mail.gmail.com>
2019-01-12 16:43 ` Maxime Ripard
2019-01-12 19:37 ` Jagan Teki
2019-01-16 19:17 ` Maxime Ripard
2019-01-17 4:32 ` Jagan Teki
2019-01-18 15:44 ` Jagan Teki
2019-01-22 11:11 ` Maxime Ripard
2019-01-22 11:51 ` Jagan Teki
2019-01-25 21:21 ` Maxime Ripard
2019-01-22 11:14 ` Maxime Ripard
2018-12-10 16:17 ` [PATCH v5 08/17] drm/sun4i: sun6i_mipi_dsi: Fix DSI hbp timing value Jagan Teki
2018-12-10 16:17 ` [PATCH v5 09/17] drm/sun4i: sun6i_mipi_dsi: Fix DSI hblk timing calculation Jagan Teki
2018-12-10 16:17 ` [PATCH v5 10/17] drm/sun4i: sun6i_mipi_dsi: Add DSI hblk packet overhead Jagan Teki
2018-12-10 16:17 ` [PATCH v5 11/17] drm/sun4i: sun6i_mipi_dsi: Fix DSI hfp timing value Jagan Teki
2018-12-10 16:17 ` Jagan Teki [this message]
2018-12-10 16:17 ` [PATCH v5 13/17] drm/sun4i: sun6i_mipi_dsi: Add support for VCC-DSI voltage regulator Jagan Teki
2018-12-10 16:17 ` [PATCH v5 14/17] dt-bindings: sun6i-dsi: Add VCC-DSI supply property Jagan Teki
2018-12-10 16:17 ` [PATCH v5 15/17] clk: sunxi-ng: a64: Add minimum rate for PLL_MIPI Jagan Teki
2018-12-11 16:32 ` Maxime Ripard
2018-12-11 16:35 ` [linux-sunxi] " Jagan Teki
2018-12-11 16:50 ` Maxime Ripard
2018-12-10 16:17 ` [PATCH v5 16/17] dt-bindings: sun6i-dsi: Add A64 DPHY compatible (w/ A31 fallback) Jagan Teki
2018-12-10 16:17 ` [PATCH v5 17/17] arm64: dts: allwinner: a64: Add DSI pipeline Jagan Teki
2018-12-11 16:34 ` Maxime Ripard
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