Re: [PATCH v2 3/4] spi: mediatek: modify set_cs_timing callback

[Andy Shevchenko <andy.shevchenko@gmail.com>]

On Tue, Aug 3, 2021 at 1:42 PM Mason Zhang <Mason.Zhang@mediatek.com> wrote:
>
> This patch modified set_cs_timing callback:
>   1 support spi_device set cs_timing in their driver;
>   2 support set absolute time but no clk count, because;
>     clk src will change in different platform;
>   3 call this function in prepare_message but not in other API.

Perhaps it should be 3 patches?

...

> +static int mtk_spi_set_hw_cs_timing(struct spi_device *spi)
> +{
> +       struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
> +       struct spi_delay *cs_setup = &spi->cs_setup;
> +       struct spi_delay *cs_hold = &spi->cs_hold;
> +       struct spi_delay *cs_inactive = &spi->cs_inactive;
> +       u16 setup, hold, inactive;
> +       u32 reg_val;
> +       int delay;
> +
> +       delay = spi_delay_to_ns(cs_setup, NULL);
> +       if (delay < 0)
> +               return delay;
> +       setup = (delay / 1000) * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000);

1000 is NSEC_PER_USEC (here and below)?

> +       delay = spi_delay_to_ns(cs_hold, NULL);
> +       if (delay < 0)
> +               return delay;
> +       hold = (delay / 1000) * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000);
> +
> +       delay = spi_delay_to_ns(cs_inactive, NULL);
> +       if (delay < 0)
> +               return delay;
> +       inactive = (delay / 1000) * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000);

> +       setup    = setup ? setup : 1;
> +       hold     = hold ? hold : 1;
> +       inactive = inactive ? inactive : 1;

All of these can be simplified by using ?: (short ternary) form.

> +       reg_val = readl(mdata->base + SPI_CFG0_REG);
> +       if (mdata->dev_comp->enhance_timing) {
> +               reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
> +               reg_val |= (((hold - 1) & 0xffff)
> +                          << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
> +               reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
> +               reg_val |= (((setup - 1) & 0xffff)
> +                          << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
> +       } else {
> +               reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
> +               reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
> +               reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
> +               reg_val |= (((setup - 1) & 0xff)
> +                           << SPI_CFG0_CS_SETUP_OFFSET);
> +       }
> +       writel(reg_val, mdata->base + SPI_CFG0_REG);
> +
> +       reg_val = readl(mdata->base + SPI_CFG1_REG);
> +       reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
> +       reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
> +       writel(reg_val, mdata->base + SPI_CFG1_REG);
> +
> +       return 0;
> +}

-- 
With Best Regards,
Andy Shevchenko

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