From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: [PATCH 2/6] cxl/core: Improve CXL core kernel docs
Date: Thu, 15 Jul 2021 12:41:21 -0700 [thread overview]
Message-ID: <20210715194125.898305-3-ben.widawsky@intel.com> (raw)
In-Reply-To: <20210715194125.898305-1-ben.widawsky@intel.com>
Now that CXL core's role is well understood, the documentation should
reflect that information.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
drivers/cxl/core/bus.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c
index 00b759ff92d3..f50872e8e7af 100644
--- a/drivers/cxl/core/bus.c
+++ b/drivers/cxl/core/bus.c
@@ -12,8 +12,15 @@
/**
* DOC: cxl core
*
- * The CXL core provides a sysfs hierarchy for control devices and a rendezvous
- * point for cross-device interleave coordination through cxl ports.
+ * The CXL core provides a set of interfaces that can be consumed by CXL aware
+ * drivers. The interfaces allow for creation, modification, and destruction of
+ * regions, memory devices, ports, and decoders. CXL aware drivers must register
+ * with the CXL core via these interfaces in order to be able to participate in
+ * cross-device interleave coordination. The CXL core also establishes and
+ * maintains the bridge to the nvdimm subsystem.
+ *
+ * CXL core introduces sysfs hierarchy to control the devices that are
+ * instantiated by the core.
*/
static DEFINE_IDA(cxl_port_ida);
--
2.32.0
next prev parent reply other threads:[~2021-07-15 19:55 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-15 19:41 [PATCH 0/6] CXL core reorganization Ben Widawsky
2021-07-15 19:41 ` [PATCH 1/6] cxl: Move cxl_core to new directory Ben Widawsky
2021-07-15 22:44 ` Dan Williams
2021-07-20 18:07 ` [PATCH v2 " Ben Widawsky
2021-07-20 18:14 ` Ben Widawsky
2021-07-15 19:41 ` Ben Widawsky [this message]
2021-07-15 23:46 ` [PATCH 2/6] cxl/core: Improve CXL core kernel docs Dan Williams
2021-07-15 19:41 ` [PATCH 3/6] cxl/core: Extract register and pmem functionality Ben Widawsky
2021-07-28 22:14 ` Dan Williams
2021-07-15 19:41 ` [PATCH 4/6] cxl/mem: Move character device region creation Ben Widawsky
2021-07-28 22:34 ` Dan Williams
2021-07-15 19:41 ` [PATCH 5/6] cxl: Pass fops and shutdown to memdev creation Ben Widawsky
2021-07-28 23:21 ` Dan Williams
2021-07-15 19:41 ` [PATCH 6/6] cxl/core: Move memdev management to core Ben Widawsky
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