[RFC v2 0/5] MIPS: ralink: peripheral clock gating driver

[NOGUCHI Hiroshi <drvlabo@gmail.com>]

Changelog:

v2:
  - moves ralink gating clock driver to drivers/clk/
  - describes the resources of gating clocks in devicetree
      and removes resource tables in source code
  - changes gating clock provider to platform_driver
  - changes PLL clock provider to platform_driver
  - replaces clk_* API calls to clk_hw_* APIs
  - uses BIT() macro
  - uses IS_ENABLED(CONFIG_COMMON_CLK) macro

------
This series introduce Mediatek/Ralink SoC's clock gating driver and
rework PLL clks as clock provider.

The gating clocks are different at individual SoCs.
Their resources are described with devicetree.

NOGUCHI Hiroshi (5):
  clk: ralink: add rt2880-clock driver
  dt-bindings: clk: add document for ralink clock driver
  mips: ralink: mt7620/76x8 use common clk framework
  mips: ralink: mt76x8: add nodes for PLL clocks and gating clocks
  mips: ralink: mt7620: add nodes for PLL	clocks and gating clocks

 .../bindings/clock/ralink,rt2880-clock.txt    |  58 +++++
 arch/mips/boot/dts/ralink/mt7620a.dtsi        |  46 +++-
 arch/mips/boot/dts/ralink/mt7628a.dtsi        |  52 +++++
 arch/mips/ralink/Kconfig                      |   2 +
 arch/mips/ralink/clk.c                        |  33 +++
 arch/mips/ralink/common.h                     |   4 +
 arch/mips/ralink/mt7620.c                     |  82 +++++---
 drivers/clk/Kconfig                           |   6 +
 drivers/clk/Makefile                          |   1 +
 drivers/clk/clk-rt2880.c                      | 199 ++++++++++++++++++
 include/dt-bindings/clock/mt7620-clk.h        |  17 ++
 11 files changed, 472 insertions(+), 28 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt
 create mode 100644 drivers/clk/clk-rt2880.c
 create mode 100644 include/dt-bindings/clock/mt7620-clk.h

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2.20.1