From: NOGUCHI Hiroshi <drvlabo@gmail.com>
To: John Crispin <john@phrozen.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
linux-mips@vger.kernel.org, linux-clk@vger.kernel.org,
NOGUCHI Hiroshi <drvlabo@gmail.com>
Subject: [RFC v2 4/5] mips: ralink: mt76x8: add nodes for clocks
Date: Fri, 5 Apr 2019 09:01:28 +0900 [thread overview]
Message-ID: <20190405000129.19331-5-drvlabo@gmail.com> (raw)
In-Reply-To: <20190405000129.19331-1-drvlabo@gmail.com>
Signed-off-by: NOGUCHI Hiroshi <drvlabo@gmail.com>
---
arch/mips/boot/dts/ralink/mt7628a.dtsi | 52 ++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
index 9ff7e8faaecc..f7630b52c8d7 100644
--- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/clock/mt7620-clk.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -26,6 +28,31 @@
compatible = "mti,cpu-interrupt-controller";
};
+ pll: pll {
+ compatible = "mediatek,mt7620-pll";
+ #clock-cells = <1>;
+ clock-output-names = "cpu", "sys", "periph", "pcmi2s", "xtal";
+ };
+
+ clkctrl: clkctrl {
+ compatible = "ralink,rt2880-clock";
+ #clock-cells = <1>;
+ ralink,sysctl = <&sysc>;
+
+ clock-indices =
+ <12>,
+ <16>, <17>, <18>, <19>,
+ <20>;
+ clock-output-names =
+ "uart0",
+ "i2c", "i2s", "spi", "uart1",
+ "uart2";
+ clocks =
+ <&pll MT7620_CLK_PERIPH>,
+ <&pll MT7620_CLK_PERIPH>, <&pll MT7620_CLK_PCMI2S>, <&pll MT7620_CLK_SYS>, <&pll MT7620_CLK_PERIPH>,
+ <&pll MT7620_CLK_PERIPH>;
+ };
+
palmbus@10000000 {
compatible = "palmbus";
reg = <0x10000000 0x200000>;
@@ -62,10 +89,29 @@
reg = <0x300 0x100>;
};
+ spi0: spi@b00 {
+ compatible = "ralink,mt7621-spi";
+ reg = <0xb00 0x100>;
+
+ clocks = <&clkctrl 18>;
+ clock-names = "spi";
+
+ resets = <&resetc 18>;
+ reset-names = "spi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
uart0: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
+ clocks = <&clkctrl 12>;
+ clock-names = "uart0";
+
resets = <&resetc 12>;
reset-names = "uart0";
@@ -79,6 +125,9 @@
compatible = "ns16550a";
reg = <0xd00 0x100>;
+ clocks = <&clkctrl 19>;
+ clock-names = "uart1";
+
resets = <&resetc 19>;
reset-names = "uart1";
@@ -92,6 +141,9 @@
compatible = "ns16550a";
reg = <0xe00 0x100>;
+ clocks = <&clkctrl 20>;
+ clock-names = "uart2";
+
resets = <&resetc 20>;
reset-names = "uart2";
--
2.20.1
next prev parent reply other threads:[~2019-04-05 0:02 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-05 0:01 [RFC v2 0/5] MIPS: ralink: peripheral clock gating driver NOGUCHI Hiroshi
2019-04-05 0:01 ` [RFC v2 1/5] clk: mips: ralink: add Ralink MIPS gating clock driver NOGUCHI Hiroshi
2019-04-25 19:27 ` Stephen Boyd
2019-05-01 10:58 ` NOGUCHI Hiroshi
2019-04-05 0:01 ` [RFC v2 2/5] dt-bindings: clk: add document for ralink " NOGUCHI Hiroshi
2019-04-25 19:29 ` Stephen Boyd
2019-05-01 11:33 ` NOGUCHI Hiroshi
2019-05-02 21:42 ` Stephen Boyd
2019-04-05 0:01 ` [RFC v2 3/5] mips: ralink: mt7620/76x8 use common clk framework NOGUCHI Hiroshi
2019-04-25 19:18 ` Stephen Boyd
2019-04-05 0:01 ` NOGUCHI Hiroshi [this message]
2019-04-05 0:01 ` [RFC v2 5/5] mips: ralink: mt7620: add nodes for clocks NOGUCHI Hiroshi
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