Re: [RFC v2 1/5] clk: mips: ralink: add Ralink MIPS gating clock driver

[NOGUCHI Hiroshi <drvlabo@gmail.com>]

Thanks for suggestions.

>> +{
>> +       struct clk_hw *clk_hw;
>> +       const char *name;
>> +       const char *parent_name;
>> +       u32 val;
>> +       int cnt;
>> +       int num;
>> +       int i;
>> +       int idx;
>> +
>> +       syscon_regmap = syscon_regmap_lookup_by_phandle(np, "ralink,sysctl");
>> +       if (IS_ERR(syscon_regmap)) {
>> +               pr_err("rt2880-clock: could not get syscon regmap.\n");
>> +               return PTR_ERR(syscon_regmap);
>> +       }
>> +
>> +       cnt = of_property_count_u32_elems(np, "clock-indices");
>> +       if (cnt < 0) {
>> +               pr_err("rt2880-clock: clock-indices property is invalid.\n");
>> +               return cnt;
>> +       }
>> +
>> +       num = 0;
>> +       for (i = 0; i < cnt; i++) {
>> +               if (of_property_read_u32_index(np, "clock-indices", i, &val))
> 
> I'm a little lost one what the indices are for? Why is the number space
> being folded like this?

I want to let the clock cell index match  with the bit number in the 
gate control register.
Is my "clock-indices" usage wrong ?