From: Dan Williams <dan.j.williams@intel.com>
To: <linux-cxl@vger.kernel.org>
Cc: Ben Widawsky <bwidawsk@kernel.org>, <hch@infradead.org>,
<alison.schofield@intel.com>, <nvdimm@lists.linux.dev>,
<linux-pci@vger.kernel.org>, <patches@lists.linux.dev>
Subject: [PATCH 11/46] cxl/core: Define a 'struct cxl_endpoint_decoder' for tracking DPA resources
Date: Thu, 23 Jun 2022 19:46:21 -0700 [thread overview]
Message-ID: <165603878173.551046.17541236959392713646.stgit@dwillia2-xfh> (raw)
In-Reply-To: <165603869943.551046.3498980330327696732.stgit@dwillia2-xfh>
Previously the target routing specifics of switch decoders and platfom
CXL window resource tracking of root decoders were factored out of
'struct cxl_decoder'. While switch decoders translate from SPA to
downstream ports, endpoint decoders translate from SPA to DPA.
This patch, 3 of 3, adds a 'struct cxl_endpoint_decoder' that tracks an
endpoint-specific Device Physical Address (DPA) resource. For now this
just defines ->dpa_res, a follow-on patch will handle requesting DPA
resource ranges from a device-DPA resource tree.
Co-developed-by: Ben Widawsky <bwidawsk@kernel.org>
Signed-off-by: Ben Widawsky <bwidawsk@kernel.org>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
drivers/cxl/core/hdm.c | 12 +++++++++---
drivers/cxl/core/port.c | 36 +++++++++++++++++++++++++++---------
drivers/cxl/cxl.h | 15 ++++++++++++++-
tools/testing/cxl/test/cxl.c | 11 +++++++++--
4 files changed, 59 insertions(+), 15 deletions(-)
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 2d1f3e6eebea..2223d151b61b 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -224,9 +224,15 @@ int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm)
int rc, target_count = cxlhdm->target_count;
struct cxl_decoder *cxld;
- if (is_cxl_endpoint(port))
- cxld = cxl_endpoint_decoder_alloc(port);
- else {
+ if (is_cxl_endpoint(port)) {
+ struct cxl_endpoint_decoder *cxled;
+
+ cxled = cxl_endpoint_decoder_alloc(port);
+ if (IS_ERR(cxled))
+ cxld = ERR_CAST(cxled);
+ else
+ cxld = &cxled->cxld;
+ } else {
struct cxl_switch_decoder *cxlsd;
cxlsd = cxl_switch_decoder_alloc(port, target_count);
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index abf3455c4eff..b5f5fb9aa4b7 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -243,12 +243,12 @@ static void __cxl_decoder_release(struct cxl_decoder *cxld)
put_device(&port->dev);
}
-static void cxl_decoder_release(struct device *dev)
+static void cxl_endpoint_decoder_release(struct device *dev)
{
- struct cxl_decoder *cxld = to_cxl_decoder(dev);
+ struct cxl_endpoint_decoder *cxled = to_cxl_endpoint_decoder(dev);
- __cxl_decoder_release(cxld);
- kfree(cxld);
+ __cxl_decoder_release(&cxled->cxld);
+ kfree(cxled);
}
static void cxl_switch_decoder_release(struct device *dev)
@@ -278,7 +278,7 @@ static void cxl_root_decoder_release(struct device *dev)
static const struct device_type cxl_decoder_endpoint_type = {
.name = "cxl_decoder_endpoint",
- .release = cxl_decoder_release,
+ .release = cxl_endpoint_decoder_release,
.groups = cxl_decoder_endpoint_attribute_groups,
};
@@ -320,6 +320,15 @@ struct cxl_decoder *to_cxl_decoder(struct device *dev)
}
EXPORT_SYMBOL_NS_GPL(to_cxl_decoder, CXL);
+struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev)
+{
+ if (dev_WARN_ONCE(dev, !is_endpoint_decoder(dev),
+ "not a cxl_endpoint_decoder device\n"))
+ return NULL;
+ return container_of(dev, struct cxl_endpoint_decoder, cxld.dev);
+}
+EXPORT_SYMBOL_NS_GPL(to_cxl_endpoint_decoder, CXL);
+
static struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev)
{
if (dev_WARN_ONCE(dev, !is_switch_decoder(dev),
@@ -1258,8 +1267,12 @@ static struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port,
cxld = &cxlsd->cxld;
}
} else {
- alloc = kzalloc(sizeof(*cxld), GFP_KERNEL);
- cxld = alloc;
+ struct cxl_endpoint_decoder *cxled;
+
+ alloc = kzalloc(sizeof(*cxled), GFP_KERNEL);
+ cxled = alloc;
+ if (cxled)
+ cxld = &cxled->cxld;
}
if (!alloc)
return ERR_PTR(-ENOMEM);
@@ -1357,12 +1370,17 @@ EXPORT_SYMBOL_NS_GPL(cxl_switch_decoder_alloc, CXL);
*
* Return: A new cxl decoder to be registered by cxl_decoder_add()
*/
-struct cxl_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port)
+struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port)
{
+ struct cxl_decoder *cxld;
+
if (!is_cxl_endpoint(port))
return ERR_PTR(-EINVAL);
- return cxl_decoder_alloc(port, 0);
+ cxld = cxl_decoder_alloc(port, 0);
+ if (IS_ERR(cxld))
+ return ERR_CAST(cxld);
+ return to_cxl_endpoint_decoder(&cxld->dev);
}
EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_alloc, CXL);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 6dd1e4c57a67..579f2d802396 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -239,6 +239,18 @@ struct cxl_decoder {
unsigned long flags;
};
+/**
+ * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder
+ * @cxld: base cxl_decoder_object
+ * @dpa_res: actively claimed DPA span of this decoder
+ * @skip: offset into @dpa_res where @cxld.hpa_range maps
+ */
+struct cxl_endpoint_decoder {
+ struct cxl_decoder cxld;
+ struct resource *dpa_res;
+ resource_size_t skip;
+};
+
/**
* struct cxl_switch_decoder - Switch specific CXL HDM Decoder
* @cxld: base cxl_decoder object
@@ -379,6 +391,7 @@ struct cxl_dport *cxl_find_dport_by_dev(struct cxl_port *port,
struct cxl_decoder *to_cxl_decoder(struct device *dev);
struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
+struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev);
bool is_root_decoder(struct device *dev);
bool is_endpoint_decoder(struct device *dev);
struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
@@ -386,7 +399,7 @@ struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
unsigned int nr_targets);
int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);
-struct cxl_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);
+struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);
int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map);
int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);
int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint);
diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index 68288354b419..f52a5dd69d36 100644
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -459,8 +459,15 @@ static int mock_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm)
cxld = ERR_CAST(cxlsd);
else
cxld = &cxlsd->cxld;
- } else
- cxld = cxl_endpoint_decoder_alloc(port);
+ } else {
+ struct cxl_endpoint_decoder *cxled;
+
+ cxled = cxl_endpoint_decoder_alloc(port);
+ if (IS_ERR(cxled))
+ cxld = ERR_CAST(cxled);
+ else
+ cxld = &cxled->cxld;
+ }
if (IS_ERR(cxld)) {
dev_warn(&port->dev,
"Failed to allocate the decoder\n");
next prev parent reply other threads:[~2022-06-24 2:46 UTC|newest]
Thread overview: 157+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-24 2:45 [PATCH 00/46] CXL PMEM Region Provisioning Dan Williams
2022-06-24 2:45 ` [PATCH 01/46] tools/testing/cxl: Fix cxl_hdm_decode_init() calling convention Dan Williams
2022-06-28 10:37 ` Jonathan Cameron
[not found] ` <CGME20220629174147uscas1p211384ae262e099484440ef285be26c75@uscas1p2.samsung.com>
2022-06-29 17:41 ` Adam Manzanares
2022-07-09 20:06 ` Dan Williams
2022-07-12 22:11 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 02/46] cxl/port: Keep port->uport valid for the entire life of a port Dan Williams
2022-06-24 3:37 ` Alison Schofield
2022-06-28 11:47 ` Jonathan Cameron
2022-06-28 14:27 ` Dan Williams
[not found] ` <CGME20220629174622uscas1p2236a084ce25771a3ab57c6f006632f35@uscas1p2.samsung.com>
2022-06-29 17:46 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 03/46] cxl/hdm: Use local hdm variable Dan Williams
2022-06-24 3:38 ` Alison Schofield
2022-06-28 15:16 ` Jonathan Cameron
[not found] ` <CGME20220629200312uscas1p292303b9325dcbfe59293f002dc9e6b03@uscas1p2.samsung.com>
2022-06-29 20:03 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 04/46] cxl/core: Rename ->decoder_range ->hpa_range Dan Williams
2022-06-24 3:39 ` Alison Schofield
2022-06-28 15:17 ` Jonathan Cameron
[not found] ` <CGME20220629200652uscas1p2c1da644ea63a5de69e14e046379779b1@uscas1p2.samsung.com>
2022-06-29 20:06 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 05/46] cxl/core: Drop ->platform_res attribute for root decoders Dan Williams
2022-06-28 15:24 ` Jonathan Cameron
2022-07-09 23:33 ` Dan Williams
[not found] ` <CGME20220629202117uscas1p2892fb68ae60c4754e2f7d26882a92ae5@uscas1p2.samsung.com>
2022-06-29 20:21 ` Adam Manzanares
2022-07-09 23:38 ` Dan Williams
2022-06-24 2:45 ` [PATCH 06/46] cxl/core: Drop is_cxl_decoder() Dan Williams
2022-06-24 3:48 ` Alison Schofield
2022-06-28 15:25 ` Jonathan Cameron
[not found] ` <CGME20220629203448uscas1p264a7f79a1ed7f9257eefcb3064c7d943@uscas1p2.samsung.com>
2022-06-29 20:34 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 07/46] cxl: Introduce cxl_to_{ways,granularity} Dan Williams
2022-06-28 15:36 ` Jonathan Cameron
2022-07-09 23:52 ` Dan Williams
2022-06-24 2:45 ` [PATCH 08/46] cxl/core: Define a 'struct cxl_switch_decoder' Dan Williams
2022-06-28 16:12 ` Jonathan Cameron
2022-06-30 10:56 ` Jonathan Cameron
2022-07-10 0:49 ` Dan Williams
2022-07-10 0:33 ` Dan Williams
2022-06-24 2:46 ` [PATCH 09/46] cxl/acpi: Track CXL resources in iomem_resource Dan Williams
2022-06-28 16:43 ` Jonathan Cameron
2022-07-10 2:12 ` Dan Williams
2022-07-19 14:24 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 10/46] cxl/core: Define a 'struct cxl_root_decoder' for tracking CXL window resources Dan Williams
2022-06-28 16:49 ` Jonathan Cameron
2022-07-10 2:20 ` Dan Williams
2022-06-28 16:53 ` Jonathan Cameron
2022-06-24 2:46 ` Dan Williams [this message]
2022-06-28 16:55 ` [PATCH 11/46] cxl/core: Define a 'struct cxl_endpoint_decoder' for tracking DPA resources Jonathan Cameron
2022-07-10 2:40 ` Dan Williams
2022-06-24 2:46 ` [PATCH 12/46] cxl/mem: Convert partition-info to resources Dan Williams
2022-06-28 17:02 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 13/46] cxl/hdm: Require all decoders to be enumerated Dan Williams
2022-06-28 17:04 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 14/46] cxl/hdm: Enumerate allocated DPA Dan Williams
2022-06-29 14:43 ` Jonathan Cameron
2022-07-10 3:03 ` Dan Williams
2022-07-19 14:25 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 15/46] cxl/Documentation: List attribute permissions Dan Williams
2022-06-28 3:16 ` Alison Schofield
2022-06-29 14:59 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 16/46] cxl/hdm: Add 'mode' attribute to decoder objects Dan Williams
2022-06-29 15:28 ` Jonathan Cameron
2022-07-10 3:45 ` Dan Williams
2022-06-24 2:47 ` [PATCH 17/46] cxl/hdm: Track next decoder to allocate Dan Williams
2022-06-29 15:31 ` Jonathan Cameron
2022-07-10 3:55 ` Dan Williams
2022-07-19 14:27 ` Jonathan Cameron
2022-07-10 16:34 ` Dan Williams
2022-06-24 2:47 ` [PATCH 18/46] cxl/hdm: Add support for allocating DPA to an endpoint decoder Dan Williams
2022-06-29 15:56 ` Jonathan Cameron
2022-07-10 16:53 ` Dan Williams
2022-06-24 2:47 ` [PATCH 19/46] cxl/debug: Move debugfs init to cxl_core_init() Dan Williams
2022-06-29 15:58 ` Jonathan Cameron
2022-06-24 2:47 ` [PATCH 20/46] cxl/mem: Add a debugfs version of 'iomem' for DPA, 'dpamem' Dan Williams
2022-06-29 16:08 ` Jonathan Cameron
2022-07-10 17:09 ` Dan Williams
2022-06-24 2:47 ` [PATCH 21/46] tools/testing/cxl: Move cxl_test resources to the top of memory Dan Williams
2022-06-29 16:11 ` Jonathan Cameron
2022-07-10 17:19 ` Dan Williams
2022-06-24 2:47 ` [PATCH 22/46] tools/testing/cxl: Expand CFMWS windows Dan Williams
2022-06-29 16:14 ` Jonathan Cameron
2022-06-24 2:47 ` [PATCH 23/46] tools/testing/cxl: Add partition support Dan Williams
2022-06-29 16:20 ` Jonathan Cameron
2022-06-24 2:48 ` [PATCH 24/46] tools/testing/cxl: Fix decoder default state Dan Williams
2022-06-29 16:22 ` Jonathan Cameron
2022-07-10 17:33 ` Dan Williams
2022-06-24 2:48 ` [PATCH 25/46] cxl/port: Record dport in endpoint references Dan Williams
2022-06-29 16:49 ` Jonathan Cameron
2022-07-10 18:40 ` Dan Williams
2022-06-24 4:19 ` [PATCH 26/46] cxl/port: Record parent dport when adding ports Dan Williams
2022-06-29 17:02 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 27/46] cxl/port: Move 'cxl_ep' references to an xarray per port Dan Williams
2022-06-29 17:19 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 28/46] cxl/port: Move dport tracking to an xarray Dan Williams
2022-06-30 9:18 ` Jonathan Cameron
2022-07-10 19:06 ` Dan Williams
2022-06-24 4:19 ` [PATCH 29/46] cxl/port: Cache CXL host bridge data Dan Williams
2022-06-30 9:21 ` Jonathan Cameron
2022-07-10 19:09 ` Dan Williams
2022-06-24 4:19 ` [PATCH 30/46] cxl/hdm: Add sysfs attributes for interleave ways + granularity Dan Williams
2022-06-30 9:26 ` Jonathan Cameron
2022-07-10 20:40 ` Dan Williams
2022-07-19 14:32 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 31/46] cxl/hdm: Initialize decoder type for memory expander devices Dan Williams
2022-06-30 9:33 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 32/46] cxl/mem: Enumerate port targets before adding endpoints Dan Williams
2022-06-30 9:48 ` Jonathan Cameron
2022-07-10 21:01 ` Dan Williams
2022-06-24 4:19 ` [PATCH 33/46] resource: Introduce alloc_free_mem_region() Dan Williams
2022-06-30 10:35 ` Jonathan Cameron
2022-07-10 21:58 ` Dan Williams
2022-06-24 4:19 ` [PATCH 34/46] cxl/region: Add region creation support Dan Williams
2022-06-30 13:17 ` Jonathan Cameron
2022-07-11 0:08 ` Dan Williams
2022-07-19 14:42 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 35/46] cxl/region: Add a 'uuid' attribute Dan Williams
2022-06-28 10:29 ` Jonathan Cameron
2022-06-28 14:24 ` Dan Williams
2022-06-24 4:19 ` [PATCH 36/46] cxl/region: Add interleave ways attribute Dan Williams
2022-06-30 13:44 ` Jonathan Cameron
2022-07-11 0:32 ` Dan Williams
2022-07-19 14:47 ` Jonathan Cameron
2022-07-19 22:15 ` Dan Williams
2022-07-20 9:59 ` Jonathan Cameron
2022-06-30 13:45 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 37/46] cxl/region: Allocate host physical address (HPA) capacity to new regions Dan Williams
2022-06-30 13:56 ` Jonathan Cameron
2022-07-11 0:47 ` Dan Williams
2022-06-24 4:19 ` [PATCH 38/46] cxl/region: Enable the assignment of endpoint decoders to regions Dan Williams
2022-06-30 14:31 ` Jonathan Cameron
2022-07-11 1:12 ` Dan Williams
2022-06-24 4:19 ` [PATCH 39/46] cxl/acpi: Add a host-bridge index lookup mechanism Dan Williams
2022-06-30 15:48 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 40/46] cxl/region: Attach endpoint decoders Dan Williams
2022-06-24 18:25 ` Jonathan Cameron
2022-06-24 18:49 ` Dan Williams
2022-06-24 20:51 ` Dan Williams
2022-06-24 23:21 ` Dan Williams
2022-06-30 16:34 ` Jonathan Cameron
2022-07-11 2:02 ` Dan Williams
2022-06-24 4:19 ` [PATCH 41/46] cxl/region: Program target lists Dan Williams
2022-06-24 4:19 ` [PATCH 42/46] cxl/hdm: Commit decoder state to hardware Dan Williams
2022-06-30 17:05 ` Jonathan Cameron
2022-07-11 3:02 ` Dan Williams
2022-06-24 4:19 ` [PATCH 43/46] cxl/region: Add region driver boiler plate Dan Williams
2022-06-30 17:09 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 44/46] cxl/pmem: Delete unused nvdimm attribute Dan Williams
2022-06-30 17:10 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 45/46] cxl/pmem: Fix offline_nvdimm_bus() to offline by bridge Dan Williams
2022-06-30 17:14 ` Jonathan Cameron
2022-07-11 19:49 ` Dan Williams
2022-06-24 4:19 ` [PATCH 46/46] cxl/region: Introduce cxl_pmem_region objects Dan Williams
2022-06-30 17:34 ` Jonathan Cameron
2022-07-11 20:05 ` Dan Williams
2022-06-24 15:13 ` [PATCH 00/46] CXL PMEM Region Provisioning Jonathan Cameron
2022-06-24 15:32 ` Dan Williams
2022-06-28 3:12 ` Alison Schofield
2022-06-28 3:34 ` Dan Williams
2022-07-02 2:26 ` Alison Schofield
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