From: Dan Williams <dan.j.williams@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <nvdimm@lists.linux.dev>,
<linux-pci@vger.kernel.org>, <patches@lists.linux.dev>,
<hch@lst.de>, "Ben Widawsky" <bwidawsk@kernel.org>
Subject: Re: [PATCH 46/46] cxl/region: Introduce cxl_pmem_region objects
Date: Mon, 11 Jul 2022 13:05:57 -0700 [thread overview]
Message-ID: <62cc82a533fcd_3535162941b@dwillia2-xfh.notmuch> (raw)
In-Reply-To: <20220630183453.00007b56@Huawei.com>
Jonathan Cameron wrote:
> On Thu, 23 Jun 2022 21:19:50 -0700
> Dan Williams <dan.j.williams@intel.com> wrote:
>
> > The LIBNVDIMM subsystem is a platform agnostic representation of system
> > NVDIMM / persistent memory resources. To date, the CXL subsystem's
> > interaction with LIBNVDIMM has been to register an nvdimm-bridge device
> > and cxl_nvdimm objects to proxy CXL capabilities into existing LIBNVDIMM
> > subsystem mechanics.
> >
> > With regions the approach is the same. Create a new cxl_pmem_region
> > object to proxy CXL region details into a LIBNVDIMM definition. With
> > this enabling LIBNVDIMM can partition CXL persistent memory regions with
> > legacy namespace labels. A follow-on patch will add CXL region label and
> > CXL namespace label support to persist region configurations across
> > driver reload / system-reset events.
> ah. Now I see why we share ID space with NVDIMMs. Fair enough, I should
> have read to the end ;)
>
> >
> > Co-developed-by: Ben Widawsky <bwidawsk@kernel.org>
> > Signed-off-by: Ben Widawsky <bwidawsk@kernel.org>
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
>
> End of day, so a fairly superficial review on this and I'll hopefully
> take a second look at one or two of the earlier patches when time allows.
>
> Jonathan
>
> ...
>
> > +static struct cxl_pmem_region *cxl_pmem_region_alloc(struct cxl_region *cxlr)
> > +{
> > + struct cxl_pmem_region *cxlr_pmem = ERR_PTR(-ENXIO);
>
> Rarely used, so better to set it where it is.
Ok.
>
> > + struct cxl_region_params *p = &cxlr->params;
> > + struct device *dev;
> > + int i;
> > +
> > + down_read(&cxl_region_rwsem);
> > + if (p->state != CXL_CONFIG_COMMIT)
> > + goto out;
> > + cxlr_pmem = kzalloc(struct_size(cxlr_pmem, mapping, p->nr_targets),
> > + GFP_KERNEL);
> > + if (!cxlr_pmem) {
> > + cxlr_pmem = ERR_PTR(-ENOMEM);
> > + goto out;
> > + }
> > +
> > + cxlr_pmem->hpa_range.start = p->res->start;
> > + cxlr_pmem->hpa_range.end = p->res->end;
> > +
> > + /* Snapshot the region configuration underneath the cxl_region_rwsem */
> > + cxlr_pmem->nr_mappings = p->nr_targets;
> > + for (i = 0; i < p->nr_targets; i++) {
> > + struct cxl_endpoint_decoder *cxled = p->targets[i];
> > + struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> > + struct cxl_pmem_region_mapping *m = &cxlr_pmem->mapping[i];
> > +
> > + m->cxlmd = cxlmd;
> > + get_device(&cxlmd->dev);
> > + m->start = cxled->dpa_res->start;
> > + m->size = resource_size(cxled->dpa_res);
> > + m->position = i;
> > + }
> > +
> > + dev = &cxlr_pmem->dev;
> > + cxlr_pmem->cxlr = cxlr;
> > + device_initialize(dev);
> > + lockdep_set_class(&dev->mutex, &cxl_pmem_region_key);
> > + device_set_pm_not_required(dev);
> > + dev->parent = &cxlr->dev;
> > + dev->bus = &cxl_bus_type;
> > + dev->type = &cxl_pmem_region_type;
> > +out:
> > + up_read(&cxl_region_rwsem);
> > +
> > + return cxlr_pmem;
> > +}
> > +
> > +static void cxlr_pmem_unregister(void *dev)
> > +{
> > + device_unregister(dev);
> > +}
> > +
> > +/**
> > + * devm_cxl_add_pmem_region() - add a cxl_region to nd_region bridge
> > + * @host: same host as @cxlmd
>
> Run kernel-doc over these and clean all the warning sup.
> Parameter if cxlr not host
Fixed.
>
>
> > + *
> > + * Return: 0 on success negative error code on failure.
> > + */
>
>
> > /*
> > * Unit test builds overrides this to __weak, find the 'strong' version
> > diff --git a/drivers/cxl/pmem.c b/drivers/cxl/pmem.c
> > index b271f6e90b91..4ba7248275ac 100644
> > --- a/drivers/cxl/pmem.c
> > +++ b/drivers/cxl/pmem.c
> > @@ -7,6 +7,7 @@
>
> >
>
>
> > +static int match_cxl_nvdimm(struct device *dev, void *data)
> > +{
> > + return is_cxl_nvdimm(dev);
> > +}
> > +
> > +static void unregister_region(void *nd_region)
>
> Better to give this a more specific name as we have several
> unregister_region() functions in CXL now.
Ok, unregister_nvdimm_region() it is.
>
> > +{
> > + struct cxl_nvdimm_bridge *cxl_nvb;
> > + struct cxl_pmem_region *cxlr_pmem;
> > + int i;
> > +
> > + cxlr_pmem = nd_region_provider_data(nd_region);
> > + cxl_nvb = cxlr_pmem->bridge;
> > + device_lock(&cxl_nvb->dev);
> > + for (i = 0; i < cxlr_pmem->nr_mappings; i++) {
> > + struct cxl_pmem_region_mapping *m = &cxlr_pmem->mapping[i];
> > + struct cxl_nvdimm *cxl_nvd = m->cxl_nvd;
> > +
> > + if (cxl_nvd->region) {
> > + put_device(&cxlr_pmem->dev);
> > + cxl_nvd->region = NULL;
> > + }
> > + }
> > + device_unlock(&cxl_nvb->dev);
> > +
> > + nvdimm_region_delete(nd_region);
> > +}
> > +
>
> > +
> > +static int cxl_pmem_region_probe(struct device *dev)
> > +{
> > + struct nd_mapping_desc mappings[CXL_DECODER_MAX_INTERLEAVE];
> > + struct cxl_pmem_region *cxlr_pmem = to_cxl_pmem_region(dev);
> > + struct cxl_region *cxlr = cxlr_pmem->cxlr;
> > + struct cxl_pmem_region_info *info = NULL;
> > + struct cxl_nvdimm_bridge *cxl_nvb;
> > + struct nd_interleave_set *nd_set;
> > + struct nd_region_desc ndr_desc;
> > + struct cxl_nvdimm *cxl_nvd;
> > + struct nvdimm *nvdimm;
> > + struct resource *res;
> > + int rc = 0, i;
> > +
> > + cxl_nvb = cxl_find_nvdimm_bridge(&cxlr_pmem->mapping[0].cxlmd->dev);
> > + if (!cxl_nvb) {
> > + dev_dbg(dev, "bridge not found\n");
> > + return -ENXIO;
> > + }
> > + cxlr_pmem->bridge = cxl_nvb;
> > +
> > + device_lock(&cxl_nvb->dev);
> > + if (!cxl_nvb->nvdimm_bus) {
> > + dev_dbg(dev, "nvdimm bus not found\n");
> > + rc = -ENXIO;
> > + goto out;
> > + }
> > +
> > + memset(&mappings, 0, sizeof(mappings));
> > + memset(&ndr_desc, 0, sizeof(ndr_desc));
> > +
> > + res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
> > + if (!res) {
> > + rc = -ENOMEM;
> > + goto out;
> > + }
> > +
> > + res->name = "Persistent Memory";
> > + res->start = cxlr_pmem->hpa_range.start;
> > + res->end = cxlr_pmem->hpa_range.end;
> > + res->flags = IORESOURCE_MEM;
> > + res->desc = IORES_DESC_PERSISTENT_MEMORY;
> > +
> > + rc = insert_resource(&iomem_resource, res);
> > + if (rc)
> > + goto out;
> > +
> > + rc = devm_add_action_or_reset(dev, cxlr_pmem_remove_resource, res);
> > + if (rc)
> > + goto out;
> > +
> > + ndr_desc.res = res;
> > + ndr_desc.provider_data = cxlr_pmem;
> > +
> > + ndr_desc.numa_node = memory_add_physaddr_to_nid(res->start);
> > + ndr_desc.target_node = phys_to_target_node(res->start);
> > + if (ndr_desc.target_node == NUMA_NO_NODE) {
> > + ndr_desc.target_node = ndr_desc.numa_node;
> > + dev_dbg(&cxlr->dev, "changing target node from %d to %d",
> > + NUMA_NO_NODE, ndr_desc.target_node);
> > + }
> > +
> > + nd_set = devm_kzalloc(dev, sizeof(*nd_set), GFP_KERNEL);
> > + if (!nd_set) {
> > + rc = -ENOMEM;
> > + goto out;
> > + }
> > +
> > + ndr_desc.memregion = cxlr->id;
> > + set_bit(ND_REGION_CXL, &ndr_desc.flags);
> > + set_bit(ND_REGION_PERSIST_MEMCTRL, &ndr_desc.flags);
> > +
> > + info = kmalloc_array(cxlr_pmem->nr_mappings, sizeof(*info), GFP_KERNEL);
> > + if (!info)
> > + goto out;
> > +
> > + rc = -ENODEV;
>
> Personal taste, but I'd much rather see that set in the error handlers
> so I can quickly see where it applies.
Ok.
>
> > + for (i = 0; i < cxlr_pmem->nr_mappings; i++) {
> > + struct cxl_pmem_region_mapping *m = &cxlr_pmem->mapping[i];
> > + struct cxl_memdev *cxlmd = m->cxlmd;
> > + struct cxl_dev_state *cxlds = cxlmd->cxlds;
> > + struct device *d;
> > +
> > + d = device_find_child(&cxlmd->dev, NULL, match_cxl_nvdimm);
> > + if (!d) {
> > + dev_dbg(dev, "[%d]: %s: no cxl_nvdimm found\n", i,
> > + dev_name(&cxlmd->dev));
> > + goto err;
> > + }
> > +
> > + /* safe to drop ref now with bridge lock held */
> > + put_device(d);
> > +
> > + cxl_nvd = to_cxl_nvdimm(d);
> > + nvdimm = dev_get_drvdata(&cxl_nvd->dev);
> > + if (!nvdimm) {
> > + dev_dbg(dev, "[%d]: %s: no nvdimm found\n", i,
> > + dev_name(&cxlmd->dev));
> > + goto err;
> > + }
> > + cxl_nvd->region = cxlr_pmem;
> > + get_device(&cxlr_pmem->dev);
> > + m->cxl_nvd = cxl_nvd;
> > + mappings[i] = (struct nd_mapping_desc) {
> > + .nvdimm = nvdimm,
> > + .start = m->start,
> > + .size = m->size,
> > + .position = i,
> > + };
> > + info[i].offset = m->start;
> > + info[i].serial = cxlds->serial;
> > + }
> > + ndr_desc.num_mappings = cxlr_pmem->nr_mappings;
> > + ndr_desc.mapping = mappings;
> > +
> > + /*
> > + * TODO enable CXL labels which skip the need for 'interleave-set cookie'
> > + */
> > + nd_set->cookie1 =
> > + nd_fletcher64(info, sizeof(*info) * cxlr_pmem->nr_mappings, 0);
> > + nd_set->cookie2 = nd_set->cookie1;
> > + ndr_desc.nd_set = nd_set;
> > +
> > + cxlr_pmem->nd_region =
> > + nvdimm_pmem_region_create(cxl_nvb->nvdimm_bus, &ndr_desc);
> > + if (IS_ERR(cxlr_pmem->nd_region)) {
> > + rc = PTR_ERR(cxlr_pmem->nd_region);
> > + goto err;
> > + } else
>
> no need for else as other branch has gone flying off down to
> err.
Yup.
>
> > + rc = devm_add_action_or_reset(dev, unregister_region,
> > + cxlr_pmem->nd_region);
> > +out:
>
> Having labels out: and err: where both are used for errors is pretty
> confusing naming... Perhaps you are better off just not sharing the
> good exit path with any of the error paths.
>
Ok.
>
> > + device_unlock(&cxl_nvb->dev);
> > + put_device(&cxl_nvb->dev);
> > + kfree(info);
>
> Ok, so safe to do this here, but would be nice to do this
> in reverse order of setup with multiple labels so we can avoid
> paths that free things that were never created. Doesn't look
> like it would hurt much to move kfree(info) above the device_unlock()
> and only do that if we have allocated info.
Ok, but no need for more labels, unconditionally free'ing info and
trying to unwind the mapping references can proceed if @info is
initialized to NULL and @i is initialized to 0.
next prev parent reply other threads:[~2022-07-11 20:06 UTC|newest]
Thread overview: 157+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-24 2:45 [PATCH 00/46] CXL PMEM Region Provisioning Dan Williams
2022-06-24 2:45 ` [PATCH 01/46] tools/testing/cxl: Fix cxl_hdm_decode_init() calling convention Dan Williams
2022-06-28 10:37 ` Jonathan Cameron
[not found] ` <CGME20220629174147uscas1p211384ae262e099484440ef285be26c75@uscas1p2.samsung.com>
2022-06-29 17:41 ` Adam Manzanares
2022-07-09 20:06 ` Dan Williams
2022-07-12 22:11 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 02/46] cxl/port: Keep port->uport valid for the entire life of a port Dan Williams
2022-06-24 3:37 ` Alison Schofield
2022-06-28 11:47 ` Jonathan Cameron
2022-06-28 14:27 ` Dan Williams
[not found] ` <CGME20220629174622uscas1p2236a084ce25771a3ab57c6f006632f35@uscas1p2.samsung.com>
2022-06-29 17:46 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 03/46] cxl/hdm: Use local hdm variable Dan Williams
2022-06-24 3:38 ` Alison Schofield
2022-06-28 15:16 ` Jonathan Cameron
[not found] ` <CGME20220629200312uscas1p292303b9325dcbfe59293f002dc9e6b03@uscas1p2.samsung.com>
2022-06-29 20:03 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 04/46] cxl/core: Rename ->decoder_range ->hpa_range Dan Williams
2022-06-24 3:39 ` Alison Schofield
2022-06-28 15:17 ` Jonathan Cameron
[not found] ` <CGME20220629200652uscas1p2c1da644ea63a5de69e14e046379779b1@uscas1p2.samsung.com>
2022-06-29 20:06 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 05/46] cxl/core: Drop ->platform_res attribute for root decoders Dan Williams
2022-06-28 15:24 ` Jonathan Cameron
2022-07-09 23:33 ` Dan Williams
[not found] ` <CGME20220629202117uscas1p2892fb68ae60c4754e2f7d26882a92ae5@uscas1p2.samsung.com>
2022-06-29 20:21 ` Adam Manzanares
2022-07-09 23:38 ` Dan Williams
2022-06-24 2:45 ` [PATCH 06/46] cxl/core: Drop is_cxl_decoder() Dan Williams
2022-06-24 3:48 ` Alison Schofield
2022-06-28 15:25 ` Jonathan Cameron
[not found] ` <CGME20220629203448uscas1p264a7f79a1ed7f9257eefcb3064c7d943@uscas1p2.samsung.com>
2022-06-29 20:34 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 07/46] cxl: Introduce cxl_to_{ways,granularity} Dan Williams
2022-06-28 15:36 ` Jonathan Cameron
2022-07-09 23:52 ` Dan Williams
2022-06-24 2:45 ` [PATCH 08/46] cxl/core: Define a 'struct cxl_switch_decoder' Dan Williams
2022-06-28 16:12 ` Jonathan Cameron
2022-06-30 10:56 ` Jonathan Cameron
2022-07-10 0:49 ` Dan Williams
2022-07-10 0:33 ` Dan Williams
2022-06-24 2:46 ` [PATCH 09/46] cxl/acpi: Track CXL resources in iomem_resource Dan Williams
2022-06-28 16:43 ` Jonathan Cameron
2022-07-10 2:12 ` Dan Williams
2022-07-19 14:24 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 10/46] cxl/core: Define a 'struct cxl_root_decoder' for tracking CXL window resources Dan Williams
2022-06-28 16:49 ` Jonathan Cameron
2022-07-10 2:20 ` Dan Williams
2022-06-28 16:53 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 11/46] cxl/core: Define a 'struct cxl_endpoint_decoder' for tracking DPA resources Dan Williams
2022-06-28 16:55 ` Jonathan Cameron
2022-07-10 2:40 ` Dan Williams
2022-06-24 2:46 ` [PATCH 12/46] cxl/mem: Convert partition-info to resources Dan Williams
2022-06-28 17:02 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 13/46] cxl/hdm: Require all decoders to be enumerated Dan Williams
2022-06-28 17:04 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 14/46] cxl/hdm: Enumerate allocated DPA Dan Williams
2022-06-29 14:43 ` Jonathan Cameron
2022-07-10 3:03 ` Dan Williams
2022-07-19 14:25 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 15/46] cxl/Documentation: List attribute permissions Dan Williams
2022-06-28 3:16 ` Alison Schofield
2022-06-29 14:59 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 16/46] cxl/hdm: Add 'mode' attribute to decoder objects Dan Williams
2022-06-29 15:28 ` Jonathan Cameron
2022-07-10 3:45 ` Dan Williams
2022-06-24 2:47 ` [PATCH 17/46] cxl/hdm: Track next decoder to allocate Dan Williams
2022-06-29 15:31 ` Jonathan Cameron
2022-07-10 3:55 ` Dan Williams
2022-07-19 14:27 ` Jonathan Cameron
2022-07-10 16:34 ` Dan Williams
2022-06-24 2:47 ` [PATCH 18/46] cxl/hdm: Add support for allocating DPA to an endpoint decoder Dan Williams
2022-06-29 15:56 ` Jonathan Cameron
2022-07-10 16:53 ` Dan Williams
2022-06-24 2:47 ` [PATCH 19/46] cxl/debug: Move debugfs init to cxl_core_init() Dan Williams
2022-06-29 15:58 ` Jonathan Cameron
2022-06-24 2:47 ` [PATCH 20/46] cxl/mem: Add a debugfs version of 'iomem' for DPA, 'dpamem' Dan Williams
2022-06-29 16:08 ` Jonathan Cameron
2022-07-10 17:09 ` Dan Williams
2022-06-24 2:47 ` [PATCH 21/46] tools/testing/cxl: Move cxl_test resources to the top of memory Dan Williams
2022-06-29 16:11 ` Jonathan Cameron
2022-07-10 17:19 ` Dan Williams
2022-06-24 2:47 ` [PATCH 22/46] tools/testing/cxl: Expand CFMWS windows Dan Williams
2022-06-29 16:14 ` Jonathan Cameron
2022-06-24 2:47 ` [PATCH 23/46] tools/testing/cxl: Add partition support Dan Williams
2022-06-29 16:20 ` Jonathan Cameron
2022-06-24 2:48 ` [PATCH 24/46] tools/testing/cxl: Fix decoder default state Dan Williams
2022-06-29 16:22 ` Jonathan Cameron
2022-07-10 17:33 ` Dan Williams
2022-06-24 2:48 ` [PATCH 25/46] cxl/port: Record dport in endpoint references Dan Williams
2022-06-29 16:49 ` Jonathan Cameron
2022-07-10 18:40 ` Dan Williams
2022-06-24 4:19 ` [PATCH 26/46] cxl/port: Record parent dport when adding ports Dan Williams
2022-06-29 17:02 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 27/46] cxl/port: Move 'cxl_ep' references to an xarray per port Dan Williams
2022-06-29 17:19 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 28/46] cxl/port: Move dport tracking to an xarray Dan Williams
2022-06-30 9:18 ` Jonathan Cameron
2022-07-10 19:06 ` Dan Williams
2022-06-24 4:19 ` [PATCH 29/46] cxl/port: Cache CXL host bridge data Dan Williams
2022-06-30 9:21 ` Jonathan Cameron
2022-07-10 19:09 ` Dan Williams
2022-06-24 4:19 ` [PATCH 30/46] cxl/hdm: Add sysfs attributes for interleave ways + granularity Dan Williams
2022-06-30 9:26 ` Jonathan Cameron
2022-07-10 20:40 ` Dan Williams
2022-07-19 14:32 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 31/46] cxl/hdm: Initialize decoder type for memory expander devices Dan Williams
2022-06-30 9:33 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 32/46] cxl/mem: Enumerate port targets before adding endpoints Dan Williams
2022-06-30 9:48 ` Jonathan Cameron
2022-07-10 21:01 ` Dan Williams
2022-06-24 4:19 ` [PATCH 33/46] resource: Introduce alloc_free_mem_region() Dan Williams
2022-06-30 10:35 ` Jonathan Cameron
2022-07-10 21:58 ` Dan Williams
2022-06-24 4:19 ` [PATCH 34/46] cxl/region: Add region creation support Dan Williams
2022-06-30 13:17 ` Jonathan Cameron
2022-07-11 0:08 ` Dan Williams
2022-07-19 14:42 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 35/46] cxl/region: Add a 'uuid' attribute Dan Williams
2022-06-28 10:29 ` Jonathan Cameron
2022-06-28 14:24 ` Dan Williams
2022-06-24 4:19 ` [PATCH 36/46] cxl/region: Add interleave ways attribute Dan Williams
2022-06-30 13:44 ` Jonathan Cameron
2022-07-11 0:32 ` Dan Williams
2022-07-19 14:47 ` Jonathan Cameron
2022-07-19 22:15 ` Dan Williams
2022-07-20 9:59 ` Jonathan Cameron
2022-06-30 13:45 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 37/46] cxl/region: Allocate host physical address (HPA) capacity to new regions Dan Williams
2022-06-30 13:56 ` Jonathan Cameron
2022-07-11 0:47 ` Dan Williams
2022-06-24 4:19 ` [PATCH 38/46] cxl/region: Enable the assignment of endpoint decoders to regions Dan Williams
2022-06-30 14:31 ` Jonathan Cameron
2022-07-11 1:12 ` Dan Williams
2022-06-24 4:19 ` [PATCH 39/46] cxl/acpi: Add a host-bridge index lookup mechanism Dan Williams
2022-06-30 15:48 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 40/46] cxl/region: Attach endpoint decoders Dan Williams
2022-06-24 18:25 ` Jonathan Cameron
2022-06-24 18:49 ` Dan Williams
2022-06-24 20:51 ` Dan Williams
2022-06-24 23:21 ` Dan Williams
2022-06-30 16:34 ` Jonathan Cameron
2022-07-11 2:02 ` Dan Williams
2022-06-24 4:19 ` [PATCH 41/46] cxl/region: Program target lists Dan Williams
2022-06-24 4:19 ` [PATCH 42/46] cxl/hdm: Commit decoder state to hardware Dan Williams
2022-06-30 17:05 ` Jonathan Cameron
2022-07-11 3:02 ` Dan Williams
2022-06-24 4:19 ` [PATCH 43/46] cxl/region: Add region driver boiler plate Dan Williams
2022-06-30 17:09 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 44/46] cxl/pmem: Delete unused nvdimm attribute Dan Williams
2022-06-30 17:10 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 45/46] cxl/pmem: Fix offline_nvdimm_bus() to offline by bridge Dan Williams
2022-06-30 17:14 ` Jonathan Cameron
2022-07-11 19:49 ` Dan Williams
2022-06-24 4:19 ` [PATCH 46/46] cxl/region: Introduce cxl_pmem_region objects Dan Williams
2022-06-30 17:34 ` Jonathan Cameron
2022-07-11 20:05 ` Dan Williams [this message]
2022-06-24 15:13 ` [PATCH 00/46] CXL PMEM Region Provisioning Jonathan Cameron
2022-06-24 15:32 ` Dan Williams
2022-06-28 3:12 ` Alison Schofield
2022-06-28 3:34 ` Dan Williams
2022-07-02 2:26 ` Alison Schofield
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