From: Dan Williams <dan.j.williams@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <nvdimm@lists.linux.dev>,
<linux-pci@vger.kernel.org>, <patches@lists.linux.dev>,
<hch@lst.de>
Subject: Re: [PATCH 28/46] cxl/port: Move dport tracking to an xarray
Date: Sun, 10 Jul 2022 12:06:21 -0700 [thread overview]
Message-ID: <62cb232d48a38_3177ca294ac@dwillia2-xfh.notmuch> (raw)
In-Reply-To: <20220630101808.0000714f@Huawei.com>
Jonathan Cameron wrote:
> On Thu, 23 Jun 2022 21:19:32 -0700
> Dan Williams <dan.j.williams@intel.com> wrote:
>
> > Reduce the complexity and the overhead of walking the topology to
> > determine endpoint connectivity to root decoder interleave
> > configurations.
> >
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> Hi Dan,
>
> A few minor comments inline around naming and also one query on why
> the refactor or reap_ports is connected to the xarray change.
>
> Thanks,
>
> Jonathan
>
> > ---
> > drivers/cxl/acpi.c | 2 +-
> > drivers/cxl/core/hdm.c | 6 ++-
> > drivers/cxl/core/port.c | 88 ++++++++++++++++++-----------------------
> > drivers/cxl/cxl.h | 12 +++---
> > 4 files changed, 51 insertions(+), 57 deletions(-)
> >
> > diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> > index 09fe92177d03..92ad1f359faf 100644
> > --- a/drivers/cxl/acpi.c
> > +++ b/drivers/cxl/acpi.c
> > @@ -197,7 +197,7 @@ static int add_host_bridge_uport(struct device *match, void *arg)
> > if (!bridge)
> > return 0;
> >
> > - dport = cxl_find_dport_by_dev(root_port, match);
> > + dport = cxl_dport_load(root_port, match);
>
> Load is kind of specific to the xarray. I'd be tempted to keep it to
> original find naming.
ok.
>
>
> > if (!dport) {
> > dev_dbg(host, "host bridge expected and not found\n");
> > return 0;
> > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> > index c0164f9b2195..672bf3e97811 100644
> > --- a/drivers/cxl/core/hdm.c
> > +++ b/drivers/cxl/core/hdm.c
> > @@ -50,8 +50,9 @@ static int add_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
> > int devm_cxl_add_passthrough_decoder(struct cxl_port *port)
> > {
> > struct cxl_switch_decoder *cxlsd;
> > - struct cxl_dport *dport;
> > + struct cxl_dport *dport = NULL;
> > int single_port_map[1];
> > + unsigned long index;
> >
> > cxlsd = cxl_switch_decoder_alloc(port, 1);
> > if (IS_ERR(cxlsd))
> > @@ -59,7 +60,8 @@ int devm_cxl_add_passthrough_decoder(struct cxl_port *port)
> >
> > device_lock_assert(&port->dev);
> >
> > - dport = list_first_entry(&port->dports, typeof(*dport), list);
> > + xa_for_each(&port->dports, index, dport)
> > + break;
> > single_port_map[0] = dport->port_id;
> >
> > return add_hdm_decoder(port, &cxlsd->cxld, single_port_map);
> > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> > index ea3ab9baf232..d2f6898940fa 100644
> > --- a/drivers/cxl/core/port.c
> > +++ b/drivers/cxl/core/port.c
> > @@ -452,6 +452,7 @@ static void cxl_port_release(struct device *dev)
> > xa_for_each(&port->endpoints, index, ep)
> > cxl_ep_remove(port, ep);
> > xa_destroy(&port->endpoints);
> > + xa_destroy(&port->dports);
> > ida_free(&cxl_port_ida, port->id);
> > kfree(port);
> > }
> > @@ -566,7 +567,7 @@ static struct cxl_port *cxl_port_alloc(struct device *uport,
> > port->component_reg_phys = component_reg_phys;
> > ida_init(&port->decoder_ida);
> > port->dpa_end = -1;
> > - INIT_LIST_HEAD(&port->dports);
> > + xa_init(&port->dports);
> > xa_init(&port->endpoints);
> >
> > device_initialize(dev);
> > @@ -696,17 +697,13 @@ static int match_root_child(struct device *dev, const void *match)
> > return 0;
> >
> > port = to_cxl_port(dev);
> > - device_lock(dev);
> > - list_for_each_entry(dport, &port->dports, list) {
> > - iter = match;
> > - while (iter) {
> > - if (iter == dport->dport)
> > - goto out;
> > - iter = iter->parent;
> > - }
> > + iter = match;
> > + while (iter) {
> > + dport = cxl_dport_load(port, iter);
> > + if (dport)
> > + break;
> > + iter = iter->parent;
> > }
> > -out:
> > - device_unlock(dev);
> >
> > return !!iter;
> > }
> > @@ -730,9 +727,10 @@ EXPORT_SYMBOL_NS_GPL(find_cxl_root, CXL);
> > static struct cxl_dport *find_dport(struct cxl_port *port, int id)
> > {
> > struct cxl_dport *dport;
> > + unsigned long index;
> >
> > device_lock_assert(&port->dev);
> > - list_for_each_entry (dport, &port->dports, list)
> > + xa_for_each(&port->dports, index, dport)
> > if (dport->port_id == id)
> > return dport;
> > return NULL;
> > @@ -741,18 +739,21 @@ static struct cxl_dport *find_dport(struct cxl_port *port, int id)
> > static int add_dport(struct cxl_port *port, struct cxl_dport *new)
> > {
> > struct cxl_dport *dup;
> > + int rc;
> >
> > device_lock_assert(&port->dev);
> > dup = find_dport(port, new->port_id);
> > - if (dup)
> > + if (dup) {
> > dev_err(&port->dev,
> > "unable to add dport%d-%s non-unique port id (%s)\n",
> > new->port_id, dev_name(new->dport),
> > dev_name(dup->dport));
> > - else
> > - list_add_tail(&new->list, &port->dports);
> > + rc = -EBUSY;
>
> Direct return slightly simpler and reduce indent on next bit plus makes
> this more obviously an 'error condition' by indenting it.
Looks good, yes.
>
> > + } else
> > + rc = xa_insert(&port->dports, (unsigned long)new->dport, new,
> > + GFP_KERNEL);
> >
> > - return dup ? -EEXIST : 0;
> > + return rc;
> > }
> >
> > /*
> > @@ -779,10 +780,8 @@ static void cxl_dport_remove(void *data)
> > struct cxl_dport *dport = data;
> > struct cxl_port *port = dport->port;
> >
> > + xa_erase(&port->dports, (unsigned long) dport->dport);
> > put_device(dport->dport);
> > - cond_cxl_root_lock(port);
> > - list_del(&dport->list);
> > - cond_cxl_root_unlock(port);
> > }
> >
> > static void cxl_dport_unlink(void *data)
> > @@ -834,7 +833,6 @@ struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
> > if (!dport)
> > return ERR_PTR(-ENOMEM);
> >
> > - INIT_LIST_HEAD(&dport->list);
> > dport->dport = dport_dev;
> > dport->port_id = port_id;
> > dport->component_reg_phys = component_reg_phys;
> > @@ -925,7 +923,7 @@ static int match_port_by_dport(struct device *dev, const void *data)
> > return 0;
> >
> > port = to_cxl_port(dev);
> > - dport = cxl_find_dport_by_dev(port, ctx->dport_dev);
> > + dport = cxl_dport_load(port, ctx->dport_dev);
> > if (ctx->dport)
> > *ctx->dport = dport;
> > return dport != NULL;
> > @@ -1025,19 +1023,27 @@ EXPORT_SYMBOL_NS_GPL(cxl_endpoint_autoremove, CXL);
> > * for a port to be unregistered is when all memdevs beneath that port have gone
> > * through ->remove(). This "bottom-up" removal selectively removes individual
> > * child ports manually. This depends on devm_cxl_add_port() to not change is
> > - * devm action registration order.
> > + * devm action registration order, and for dports to have already been
> > + * destroyed by reap_dports().
> > */
> > -static void delete_switch_port(struct cxl_port *port, struct list_head *dports)
> > +static void delete_switch_port(struct cxl_port *port)
> > +{
> > + devm_release_action(port->dev.parent, cxl_unlink_uport, port);
> > + devm_release_action(port->dev.parent, unregister_port, port);
> > +}
> > +
> > +static void reap_dports(struct cxl_port *port)
> > {
> > - struct cxl_dport *dport, *_d;
> > + struct cxl_dport *dport;
> > + unsigned long index;
> > +
> > + device_lock_assert(&port->dev);
> >
> > - list_for_each_entry_safe(dport, _d, dports, list) {
> > + xa_for_each(&port->dports, index, dport) {
> > devm_release_action(&port->dev, cxl_dport_unlink, dport);
> > devm_release_action(&port->dev, cxl_dport_remove, dport);
> > devm_kfree(&port->dev, dport);
> > }
> > - devm_release_action(port->dev.parent, cxl_unlink_uport, port);
> > - devm_release_action(port->dev.parent, unregister_port, port);
> > }
> >
> > static struct cxl_ep *cxl_ep_load(struct cxl_port *port,
> > @@ -1054,8 +1060,8 @@ static void cxl_detach_ep(void *data)
> > for (iter = &cxlmd->dev; iter; iter = grandparent(iter)) {
> > struct device *dport_dev = grandparent(iter);
> > struct cxl_port *port, *parent_port;
> > - LIST_HEAD(reap_dports);
> > struct cxl_ep *ep;
> > + bool died = false;
> >
> > if (!dport_dev)
> > break;
> > @@ -1095,15 +1101,16 @@ static void cxl_detach_ep(void *data)
> > * enumerated port. Block new cxl_add_ep() and garbage
> > * collect the port.
> > */
> > + died = true;
> > port->dead = true;
> > - list_splice_init(&port->dports, &reap_dports);
> > + reap_dports(port);
>
> I'm not immediately clear on why this refactor is tied up with moving
> to the xarray. Perhaps a comment in the commit message to add
> more detail around this?
Sure, added the following:
Note that cxl_detach_ep(), after it determines that the last @ep has
departed and decides to delete the port, now needs to walk the dport
array with the device_lock() held to remove entries. Previously
list_splice_init() could be used atomically delete all dport entries at
once and then perform entry tear down outside the lock. There is no
list_splice_init() equivalent for the xarray.
next prev parent reply other threads:[~2022-07-10 19:06 UTC|newest]
Thread overview: 157+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-24 2:45 [PATCH 00/46] CXL PMEM Region Provisioning Dan Williams
2022-06-24 2:45 ` [PATCH 01/46] tools/testing/cxl: Fix cxl_hdm_decode_init() calling convention Dan Williams
2022-06-28 10:37 ` Jonathan Cameron
[not found] ` <CGME20220629174147uscas1p211384ae262e099484440ef285be26c75@uscas1p2.samsung.com>
2022-06-29 17:41 ` Adam Manzanares
2022-07-09 20:06 ` Dan Williams
2022-07-12 22:11 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 02/46] cxl/port: Keep port->uport valid for the entire life of a port Dan Williams
2022-06-24 3:37 ` Alison Schofield
2022-06-28 11:47 ` Jonathan Cameron
2022-06-28 14:27 ` Dan Williams
[not found] ` <CGME20220629174622uscas1p2236a084ce25771a3ab57c6f006632f35@uscas1p2.samsung.com>
2022-06-29 17:46 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 03/46] cxl/hdm: Use local hdm variable Dan Williams
2022-06-24 3:38 ` Alison Schofield
2022-06-28 15:16 ` Jonathan Cameron
[not found] ` <CGME20220629200312uscas1p292303b9325dcbfe59293f002dc9e6b03@uscas1p2.samsung.com>
2022-06-29 20:03 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 04/46] cxl/core: Rename ->decoder_range ->hpa_range Dan Williams
2022-06-24 3:39 ` Alison Schofield
2022-06-28 15:17 ` Jonathan Cameron
[not found] ` <CGME20220629200652uscas1p2c1da644ea63a5de69e14e046379779b1@uscas1p2.samsung.com>
2022-06-29 20:06 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 05/46] cxl/core: Drop ->platform_res attribute for root decoders Dan Williams
2022-06-28 15:24 ` Jonathan Cameron
2022-07-09 23:33 ` Dan Williams
[not found] ` <CGME20220629202117uscas1p2892fb68ae60c4754e2f7d26882a92ae5@uscas1p2.samsung.com>
2022-06-29 20:21 ` Adam Manzanares
2022-07-09 23:38 ` Dan Williams
2022-06-24 2:45 ` [PATCH 06/46] cxl/core: Drop is_cxl_decoder() Dan Williams
2022-06-24 3:48 ` Alison Schofield
2022-06-28 15:25 ` Jonathan Cameron
[not found] ` <CGME20220629203448uscas1p264a7f79a1ed7f9257eefcb3064c7d943@uscas1p2.samsung.com>
2022-06-29 20:34 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 07/46] cxl: Introduce cxl_to_{ways,granularity} Dan Williams
2022-06-28 15:36 ` Jonathan Cameron
2022-07-09 23:52 ` Dan Williams
2022-06-24 2:45 ` [PATCH 08/46] cxl/core: Define a 'struct cxl_switch_decoder' Dan Williams
2022-06-28 16:12 ` Jonathan Cameron
2022-06-30 10:56 ` Jonathan Cameron
2022-07-10 0:49 ` Dan Williams
2022-07-10 0:33 ` Dan Williams
2022-06-24 2:46 ` [PATCH 09/46] cxl/acpi: Track CXL resources in iomem_resource Dan Williams
2022-06-28 16:43 ` Jonathan Cameron
2022-07-10 2:12 ` Dan Williams
2022-07-19 14:24 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 10/46] cxl/core: Define a 'struct cxl_root_decoder' for tracking CXL window resources Dan Williams
2022-06-28 16:49 ` Jonathan Cameron
2022-07-10 2:20 ` Dan Williams
2022-06-28 16:53 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 11/46] cxl/core: Define a 'struct cxl_endpoint_decoder' for tracking DPA resources Dan Williams
2022-06-28 16:55 ` Jonathan Cameron
2022-07-10 2:40 ` Dan Williams
2022-06-24 2:46 ` [PATCH 12/46] cxl/mem: Convert partition-info to resources Dan Williams
2022-06-28 17:02 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 13/46] cxl/hdm: Require all decoders to be enumerated Dan Williams
2022-06-28 17:04 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 14/46] cxl/hdm: Enumerate allocated DPA Dan Williams
2022-06-29 14:43 ` Jonathan Cameron
2022-07-10 3:03 ` Dan Williams
2022-07-19 14:25 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 15/46] cxl/Documentation: List attribute permissions Dan Williams
2022-06-28 3:16 ` Alison Schofield
2022-06-29 14:59 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 16/46] cxl/hdm: Add 'mode' attribute to decoder objects Dan Williams
2022-06-29 15:28 ` Jonathan Cameron
2022-07-10 3:45 ` Dan Williams
2022-06-24 2:47 ` [PATCH 17/46] cxl/hdm: Track next decoder to allocate Dan Williams
2022-06-29 15:31 ` Jonathan Cameron
2022-07-10 3:55 ` Dan Williams
2022-07-19 14:27 ` Jonathan Cameron
2022-07-10 16:34 ` Dan Williams
2022-06-24 2:47 ` [PATCH 18/46] cxl/hdm: Add support for allocating DPA to an endpoint decoder Dan Williams
2022-06-29 15:56 ` Jonathan Cameron
2022-07-10 16:53 ` Dan Williams
2022-06-24 2:47 ` [PATCH 19/46] cxl/debug: Move debugfs init to cxl_core_init() Dan Williams
2022-06-29 15:58 ` Jonathan Cameron
2022-06-24 2:47 ` [PATCH 20/46] cxl/mem: Add a debugfs version of 'iomem' for DPA, 'dpamem' Dan Williams
2022-06-29 16:08 ` Jonathan Cameron
2022-07-10 17:09 ` Dan Williams
2022-06-24 2:47 ` [PATCH 21/46] tools/testing/cxl: Move cxl_test resources to the top of memory Dan Williams
2022-06-29 16:11 ` Jonathan Cameron
2022-07-10 17:19 ` Dan Williams
2022-06-24 2:47 ` [PATCH 22/46] tools/testing/cxl: Expand CFMWS windows Dan Williams
2022-06-29 16:14 ` Jonathan Cameron
2022-06-24 2:47 ` [PATCH 23/46] tools/testing/cxl: Add partition support Dan Williams
2022-06-29 16:20 ` Jonathan Cameron
2022-06-24 2:48 ` [PATCH 24/46] tools/testing/cxl: Fix decoder default state Dan Williams
2022-06-29 16:22 ` Jonathan Cameron
2022-07-10 17:33 ` Dan Williams
2022-06-24 2:48 ` [PATCH 25/46] cxl/port: Record dport in endpoint references Dan Williams
2022-06-29 16:49 ` Jonathan Cameron
2022-07-10 18:40 ` Dan Williams
2022-06-24 4:19 ` [PATCH 26/46] cxl/port: Record parent dport when adding ports Dan Williams
2022-06-29 17:02 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 27/46] cxl/port: Move 'cxl_ep' references to an xarray per port Dan Williams
2022-06-29 17:19 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 28/46] cxl/port: Move dport tracking to an xarray Dan Williams
2022-06-30 9:18 ` Jonathan Cameron
2022-07-10 19:06 ` Dan Williams [this message]
2022-06-24 4:19 ` [PATCH 29/46] cxl/port: Cache CXL host bridge data Dan Williams
2022-06-30 9:21 ` Jonathan Cameron
2022-07-10 19:09 ` Dan Williams
2022-06-24 4:19 ` [PATCH 30/46] cxl/hdm: Add sysfs attributes for interleave ways + granularity Dan Williams
2022-06-30 9:26 ` Jonathan Cameron
2022-07-10 20:40 ` Dan Williams
2022-07-19 14:32 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 31/46] cxl/hdm: Initialize decoder type for memory expander devices Dan Williams
2022-06-30 9:33 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 32/46] cxl/mem: Enumerate port targets before adding endpoints Dan Williams
2022-06-30 9:48 ` Jonathan Cameron
2022-07-10 21:01 ` Dan Williams
2022-06-24 4:19 ` [PATCH 33/46] resource: Introduce alloc_free_mem_region() Dan Williams
2022-06-30 10:35 ` Jonathan Cameron
2022-07-10 21:58 ` Dan Williams
2022-06-24 4:19 ` [PATCH 34/46] cxl/region: Add region creation support Dan Williams
2022-06-30 13:17 ` Jonathan Cameron
2022-07-11 0:08 ` Dan Williams
2022-07-19 14:42 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 35/46] cxl/region: Add a 'uuid' attribute Dan Williams
2022-06-28 10:29 ` Jonathan Cameron
2022-06-28 14:24 ` Dan Williams
2022-06-24 4:19 ` [PATCH 36/46] cxl/region: Add interleave ways attribute Dan Williams
2022-06-30 13:44 ` Jonathan Cameron
2022-07-11 0:32 ` Dan Williams
2022-07-19 14:47 ` Jonathan Cameron
2022-07-19 22:15 ` Dan Williams
2022-07-20 9:59 ` Jonathan Cameron
2022-06-30 13:45 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 37/46] cxl/region: Allocate host physical address (HPA) capacity to new regions Dan Williams
2022-06-30 13:56 ` Jonathan Cameron
2022-07-11 0:47 ` Dan Williams
2022-06-24 4:19 ` [PATCH 38/46] cxl/region: Enable the assignment of endpoint decoders to regions Dan Williams
2022-06-30 14:31 ` Jonathan Cameron
2022-07-11 1:12 ` Dan Williams
2022-06-24 4:19 ` [PATCH 39/46] cxl/acpi: Add a host-bridge index lookup mechanism Dan Williams
2022-06-30 15:48 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 40/46] cxl/region: Attach endpoint decoders Dan Williams
2022-06-24 18:25 ` Jonathan Cameron
2022-06-24 18:49 ` Dan Williams
2022-06-24 20:51 ` Dan Williams
2022-06-24 23:21 ` Dan Williams
2022-06-30 16:34 ` Jonathan Cameron
2022-07-11 2:02 ` Dan Williams
2022-06-24 4:19 ` [PATCH 41/46] cxl/region: Program target lists Dan Williams
2022-06-24 4:19 ` [PATCH 42/46] cxl/hdm: Commit decoder state to hardware Dan Williams
2022-06-30 17:05 ` Jonathan Cameron
2022-07-11 3:02 ` Dan Williams
2022-06-24 4:19 ` [PATCH 43/46] cxl/region: Add region driver boiler plate Dan Williams
2022-06-30 17:09 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 44/46] cxl/pmem: Delete unused nvdimm attribute Dan Williams
2022-06-30 17:10 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 45/46] cxl/pmem: Fix offline_nvdimm_bus() to offline by bridge Dan Williams
2022-06-30 17:14 ` Jonathan Cameron
2022-07-11 19:49 ` Dan Williams
2022-06-24 4:19 ` [PATCH 46/46] cxl/region: Introduce cxl_pmem_region objects Dan Williams
2022-06-30 17:34 ` Jonathan Cameron
2022-07-11 20:05 ` Dan Williams
2022-06-24 15:13 ` [PATCH 00/46] CXL PMEM Region Provisioning Jonathan Cameron
2022-06-24 15:32 ` Dan Williams
2022-06-28 3:12 ` Alison Schofield
2022-06-28 3:34 ` Dan Williams
2022-07-02 2:26 ` Alison Schofield
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