From: <Claudiu.Beznea@microchip.com>
To: <Varshini.Rajendran@microchip.com>, <tglx@linutronix.de>,
<maz@kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
<Nicolas.Ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<davem@davemloft.net>, <edumazet@google.com>, <kuba@kernel.org>,
<pabeni@redhat.com>, <gregkh@linuxfoundation.org>,
<linux@armlinux.org.uk>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <sre@kernel.org>, <broonie@kernel.org>,
<arnd@arndb.de>, <gregory.clement@bootlin.com>,
<sudeep.holla@arm.com>, <Balamanikandan.Gunasundar@microchip.com>,
<Mihai.Sain@microchip.com>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <netdev@vger.kernel.org>,
<linux-usb@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-pm@vger.kernel.org>
Cc: <Hari.PrasathGE@microchip.com>, <Cristian.Birsan@microchip.com>,
<Durai.ManickamKR@microchip.com>, <Manikandan.M@microchip.com>,
<Dharma.B@microchip.com>, <Nayabbasha.Sayed@microchip.com>,
<Balakrishnan.S@microchip.com>
Subject: Re: [PATCH 12/21] clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs
Date: Thu, 15 Jun 2023 07:54:46 +0000 [thread overview]
Message-ID: <49840bbc-99a9-4e40-d409-0f8216ed76dc@microchip.com> (raw)
In-Reply-To: <20230603200243.243878-13-varshini.rajendran@microchip.com>
On 03.06.2023 23:02, Varshini Rajendran wrote:
> -Support SoCs with different core frequency outputs for different PLL IDs
> by adding a separate parameter for handling the same in the PLL driver
> -Align sam9x60 and sama7g5 Soc PMC driver to PLL driver by adding core
> output freq range in the PLL characteristics configurations
Having this with "-" here makes me think you did multiple things in the
same patch. Please explain comprehensively what you've did, why and how.
>
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> drivers/clk/at91/clk-sam9x60-pll.c | 12 ++++++------
> drivers/clk/at91/pmc.h | 1 +
> drivers/clk/at91/sam9x60.c | 7 +++++++
> drivers/clk/at91/sama7g5.c | 7 +++++++
> 4 files changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index 0882ed01d5c2..b3012641214c 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -23,9 +23,6 @@
> #define UPLL_DIV 2
> #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
>
> -#define FCORE_MIN (600000000)
> -#define FCORE_MAX (1200000000)
> -
> #define PLL_MAX_ID 7
>
> struct sam9x60_pll_core {
> @@ -194,7 +191,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
> unsigned long nmul = 0;
> unsigned long nfrac = 0;
>
> - if (rate < FCORE_MIN || rate > FCORE_MAX)
> + if (rate < core->characteristics->core_output[0].min ||
> + rate > core->characteristics->core_output[0].max)
> return -ERANGE;
>
> /*
> @@ -214,7 +212,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
> }
>
> /* Check if resulted rate is a valid. */
> - if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)
> + if (tmprate < core->characteristics->core_output[0].min ||
> + tmprate > core->characteristics->core_output[0].max)
> return -ERANGE;
>
> if (update) {
> @@ -666,7 +665,8 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
> goto free;
> }
>
> - ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,
> + ret = sam9x60_frac_pll_compute_mul_frac(&frac->core,
> + characteristics->core_output[0].min,
> parent_rate, true);
> if (ret < 0) {
> hw = ERR_PTR(ret);
> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
> index 1b3ca7dd9b57..3e36dcc464c1 100644
> --- a/drivers/clk/at91/pmc.h
> +++ b/drivers/clk/at91/pmc.h
> @@ -75,6 +75,7 @@ struct clk_pll_characteristics {
> struct clk_range input;
> int num_output;
> const struct clk_range *output;
> + const struct clk_range *core_output;
> u16 *icpll;
> u8 *out;
> u8 upll : 1;
> diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
> index ac070db58195..452ad45cf251 100644
> --- a/drivers/clk/at91/sam9x60.c
> +++ b/drivers/clk/at91/sam9x60.c
> @@ -26,10 +26,16 @@ static const struct clk_range plla_outputs[] = {
> { .min = 2343750, .max = 1200000000 },
> };
>
> +/* Fractional PLL core output range. */
> +static const struct clk_range core_outputs[] = {
> + { .min = 600000000, .max = 1200000000 },
> +};
> +
> static const struct clk_pll_characteristics plla_characteristics = {
> .input = { .min = 12000000, .max = 48000000 },
> .num_output = ARRAY_SIZE(plla_outputs),
> .output = plla_outputs,
> + .core_output = core_outputs,
> };
>
> static const struct clk_range upll_outputs[] = {
> @@ -40,6 +46,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
> .input = { .min = 12000000, .max = 48000000 },
> .num_output = ARRAY_SIZE(upll_outputs),
> .output = upll_outputs,
> + .core_output = core_outputs,
> .upll = true,
> };
>
> diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
> index f135b662f1ff..468a3c5449b5 100644
> --- a/drivers/clk/at91/sama7g5.c
> +++ b/drivers/clk/at91/sama7g5.c
> @@ -104,11 +104,17 @@ static const struct clk_range pll_outputs[] = {
> { .min = 2343750, .max = 1200000000 },
> };
>
> +/* Fractional PLL core output range. */
> +static const struct clk_range core_outputs[] = {
> + { .min = 600000000, .max = 1200000000 },
> +};
> +
> /* CPU PLL characteristics. */
> static const struct clk_pll_characteristics cpu_pll_characteristics = {
> .input = { .min = 12000000, .max = 50000000 },
> .num_output = ARRAY_SIZE(cpu_pll_outputs),
> .output = cpu_pll_outputs,
> + .core_output = core_outputs,
> };
>
> /* PLL characteristics. */
> @@ -116,6 +122,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
> .input = { .min = 12000000, .max = 50000000 },
> .num_output = ARRAY_SIZE(pll_outputs),
> .output = pll_outputs,
> + .core_output = core_outputs,
> };
>
> /*
next prev parent reply other threads:[~2023-06-15 7:55 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-03 20:02 [PATCH 00/21] Add support for sam9x7 SoC family Varshini Rajendran
2023-06-03 20:02 ` [PATCH 01/21] dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x60 compatible Varshini Rajendran
2023-06-05 6:35 ` Krzysztof Kozlowski
2023-06-05 7:04 ` Arnd Bergmann
2023-06-05 7:34 ` Krzysztof Kozlowski
2023-06-14 19:37 ` Rob Herring
2023-06-03 20:02 ` [PATCH 02/21] dt-bindings: usb: ehci: Add atmel at91sam9g45-ehci compatible Varshini Rajendran
2023-06-14 19:38 ` Rob Herring
2023-06-03 20:02 ` [PATCH 03/21] dt-bindings: usb: generic-ehci: Document clock-names property Varshini Rajendran
2023-06-03 21:15 ` Conor Dooley
2023-06-05 12:54 ` Nicolas Ferre
2023-06-05 6:36 ` Krzysztof Kozlowski
2023-06-03 20:02 ` [PATCH 04/21] ARM: dts: at91: sam9x7: add device tree for soc Varshini Rajendran
2023-06-03 21:35 ` Conor Dooley
2023-06-05 6:39 ` Krzysztof Kozlowski
2023-06-05 6:41 ` Krzysztof Kozlowski
2023-06-09 5:35 ` Dharma.B
2023-06-15 7:36 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 05/21] ARM: configs: at91: enable config flags for sam9x7 SoC Varshini Rajendran
2023-06-03 20:02 ` [PATCH 06/21] ARM: configs: at91: add mcan support Varshini Rajendran
2023-06-05 6:40 ` Krzysztof Kozlowski
2023-06-03 20:02 ` [PATCH 07/21] ARM: configs: at91: Enable csi and isc support Varshini Rajendran
2023-06-03 20:02 ` [PATCH 08/21] ARM: at91: pm: add support for sam9x7 soc family Varshini Rajendran
2023-06-15 7:42 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 09/21] ARM: at91: pm: add sam9x7 soc init config Varshini Rajendran
2023-06-15 7:43 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 10/21] ARM: at91: Kconfig: add config flag for SAM9X7 SoC Varshini Rajendran
2023-06-15 7:46 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 11/21] ARM: at91: add support in soc driver for new sam9x7 Varshini Rajendran
2023-06-15 7:48 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 12/21] clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs Varshini Rajendran
2023-06-15 7:54 ` Claudiu.Beznea [this message]
2023-06-03 20:02 ` [PATCH 13/21] clk: at91: sam9x7: add support for HW PLL freq dividers Varshini Rajendran
2023-06-15 8:00 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 14/21] clk: at91: sam9x7: add sam9x7 pmc driver Varshini Rajendran
2023-06-04 18:00 ` Simon Horman
2023-06-15 8:39 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 15/21] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic Varshini Rajendran
2023-06-03 21:19 ` Conor Dooley
2023-06-03 21:23 ` Conor Dooley
2023-06-04 9:49 ` Arnd Bergmann
2023-06-04 21:08 ` Conor Dooley
2023-06-05 12:37 ` Nicolas Ferre
2023-06-14 19:41 ` Rob Herring
2023-06-03 20:02 ` [PATCH 16/21] " Varshini Rajendran
2023-06-03 20:02 ` [PATCH 17/21] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7 Varshini Rajendran
2023-06-05 6:43 ` Krzysztof Kozlowski
2023-06-05 13:04 ` Nicolas Ferre
2023-06-05 13:26 ` Conor Dooley
2023-06-16 17:32 ` Varshini.Rajendran
2023-06-05 13:33 ` Krzysztof Kozlowski
2023-06-03 20:02 ` [PATCH 18/21] power: reset: at91-reset: add reset support for sam9x7 soc Varshini Rajendran
2023-06-03 20:02 ` [PATCH 19/21] power: reset: at91-reset: add sdhwc " Varshini Rajendran
2023-06-03 20:02 ` [PATCH 20/21] dt-bindings: net: cdns,macb: add documentation for sam9x7 ethernet interface Varshini Rajendran
2023-06-05 6:42 ` Krzysztof Kozlowski
2023-06-14 19:42 ` Rob Herring
2023-06-03 20:02 ` [PATCH 21/21] net: macb: add support for gmac to sam9x7 Varshini Rajendran
2023-06-05 6:42 ` Krzysztof Kozlowski
2023-06-05 12:07 ` Nicolas Ferre
2023-06-05 12:21 ` Arnd Bergmann
2023-06-05 13:34 ` Krzysztof Kozlowski
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