From: <Claudiu.Beznea@microchip.com>
To: <Varshini.Rajendran@microchip.com>, <tglx@linutronix.de>,
<maz@kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
<Nicolas.Ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<davem@davemloft.net>, <edumazet@google.com>, <kuba@kernel.org>,
<pabeni@redhat.com>, <gregkh@linuxfoundation.org>,
<linux@armlinux.org.uk>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <sre@kernel.org>, <broonie@kernel.org>,
<arnd@arndb.de>, <gregory.clement@bootlin.com>,
<sudeep.holla@arm.com>, <Balamanikandan.Gunasundar@microchip.com>,
<Mihai.Sain@microchip.com>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <netdev@vger.kernel.org>,
<linux-usb@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-pm@vger.kernel.org>
Cc: <Hari.PrasathGE@microchip.com>, <Cristian.Birsan@microchip.com>,
<Durai.ManickamKR@microchip.com>, <Manikandan.M@microchip.com>,
<Dharma.B@microchip.com>, <Nayabbasha.Sayed@microchip.com>,
<Balakrishnan.S@microchip.com>
Subject: Re: [PATCH 13/21] clk: at91: sam9x7: add support for HW PLL freq dividers
Date: Thu, 15 Jun 2023 08:00:45 +0000 [thread overview]
Message-ID: <71d6e453-16bd-a5ce-bb95-8e615a944fb2@microchip.com> (raw)
In-Reply-To: <20230603200243.243878-14-varshini.rajendran@microchip.com>
On 03.06.2023 23:02, Varshini Rajendran wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add support for hardware dividers for PLL IDs in sam9x7 Soc
dot at the end of line, probably.
s/Soc/SoC. Also, please explain it as clear as possible.
> PLL_ID_PLLA and PLL_ID_PLLA_DIV2 has /2 hardware dividers each
At the time of this patch PLL_ID_PLLA and PLL_ID_PLLA_DIV2 does't exist
thus would be more clear if you reference datasheet naming.
Other than this code looks good to me.
Thank you,
Claudiu
>
> fcorepllack -----> HW Div = 2 -+--> fpllack
> |
> +--> HW Div = 2 ---> fplladiv2ck
>
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> drivers/clk/at91/clk-sam9x60-pll.c | 38 ++++++++++++++++++++++++++----
> drivers/clk/at91/pmc.h | 1 +
> 2 files changed, 34 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index b3012641214c..76273ea74f8b 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
> {
> struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
> struct sam9x60_frac *frac = to_sam9x60_frac(core);
> + unsigned long freq;
>
> - return parent_rate * (frac->mul + 1) +
> + freq = parent_rate * (frac->mul + 1) +
> DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
> +
> + if (core->layout->div2)
> + freq >>= 1;
> +
> + return freq;
> }
>
> static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
> @@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw,
> return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1));
> }
>
> +static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + return parent_rate >> 1;
> +}
> +
> static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
> unsigned long *parent_rate,
> unsigned long rate)
> @@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = {
> .restore_context = sam9x60_div_pll_restore_context,
> };
>
> +static const struct clk_ops sam9x60_fixed_div_pll_ops = {
> + .prepare = sam9x60_div_pll_prepare,
> + .unprepare = sam9x60_div_pll_unprepare,
> + .is_prepared = sam9x60_div_pll_is_prepared,
> + .recalc_rate = sam9x60_fixed_div_pll_recalc_rate,
> + .round_rate = sam9x60_div_pll_round_rate,
> + .save_context = sam9x60_div_pll_save_context,
> + .restore_context = sam9x60_div_pll_restore_context,
> +};
> +
> struct clk_hw * __init
> sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
> const char *name, const char *parent_name,
> @@ -718,10 +740,16 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
> init.name = name;
> init.parent_names = &parent_name;
> init.num_parents = 1;
> - if (flags & CLK_SET_RATE_GATE)
> - init.ops = &sam9x60_div_pll_ops;
> - else
> - init.ops = &sam9x60_div_pll_ops_chg;
> +
> + if (layout->div2) {
> + init.ops = &sam9x60_fixed_div_pll_ops;
> + } else {
> + if (flags & CLK_SET_RATE_GATE)
> + init.ops = &sam9x60_div_pll_ops;
> + else
> + init.ops = &sam9x60_div_pll_ops_chg;
> + }
> +
> init.flags = flags;
>
> div->core.id = id;
> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
> index 3e36dcc464c1..1dd01f30bdee 100644
> --- a/drivers/clk/at91/pmc.h
> +++ b/drivers/clk/at91/pmc.h
> @@ -64,6 +64,7 @@ struct clk_pll_layout {
> u8 frac_shift;
> u8 div_shift;
> u8 endiv_shift;
> + u8 div2;
> };
>
> extern const struct clk_pll_layout at91rm9200_pll_layout;
> --
> 2.25.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-06-15 8:01 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-03 20:02 [PATCH 00/21] Add support for sam9x7 SoC family Varshini Rajendran
2023-06-03 20:02 ` [PATCH 01/21] dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x60 compatible Varshini Rajendran
2023-06-05 6:35 ` Krzysztof Kozlowski
2023-06-05 7:04 ` Arnd Bergmann
2023-06-05 7:34 ` Krzysztof Kozlowski
2023-06-14 19:37 ` Rob Herring
2023-06-03 20:02 ` [PATCH 02/21] dt-bindings: usb: ehci: Add atmel at91sam9g45-ehci compatible Varshini Rajendran
2023-06-14 19:38 ` Rob Herring
2023-06-03 20:02 ` [PATCH 03/21] dt-bindings: usb: generic-ehci: Document clock-names property Varshini Rajendran
2023-06-03 21:15 ` Conor Dooley
2023-06-05 12:54 ` Nicolas Ferre
2023-06-05 6:36 ` Krzysztof Kozlowski
2023-06-03 20:02 ` [PATCH 04/21] ARM: dts: at91: sam9x7: add device tree for soc Varshini Rajendran
2023-06-03 21:35 ` Conor Dooley
2023-06-05 6:39 ` Krzysztof Kozlowski
2023-06-05 6:41 ` Krzysztof Kozlowski
2023-06-09 5:35 ` Dharma.B
2023-06-15 7:36 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 05/21] ARM: configs: at91: enable config flags for sam9x7 SoC Varshini Rajendran
2023-06-03 20:02 ` [PATCH 06/21] ARM: configs: at91: add mcan support Varshini Rajendran
2023-06-05 6:40 ` Krzysztof Kozlowski
2023-06-03 20:02 ` [PATCH 07/21] ARM: configs: at91: Enable csi and isc support Varshini Rajendran
2023-06-03 20:02 ` [PATCH 08/21] ARM: at91: pm: add support for sam9x7 soc family Varshini Rajendran
2023-06-15 7:42 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 09/21] ARM: at91: pm: add sam9x7 soc init config Varshini Rajendran
2023-06-15 7:43 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 10/21] ARM: at91: Kconfig: add config flag for SAM9X7 SoC Varshini Rajendran
2023-06-15 7:46 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 11/21] ARM: at91: add support in soc driver for new sam9x7 Varshini Rajendran
2023-06-15 7:48 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 12/21] clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs Varshini Rajendran
2023-06-15 7:54 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 13/21] clk: at91: sam9x7: add support for HW PLL freq dividers Varshini Rajendran
2023-06-15 8:00 ` Claudiu.Beznea [this message]
2023-06-03 20:02 ` [PATCH 14/21] clk: at91: sam9x7: add sam9x7 pmc driver Varshini Rajendran
2023-06-04 18:00 ` Simon Horman
2023-06-15 8:39 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 15/21] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic Varshini Rajendran
2023-06-03 21:19 ` Conor Dooley
2023-06-03 21:23 ` Conor Dooley
2023-06-04 9:49 ` Arnd Bergmann
2023-06-04 21:08 ` Conor Dooley
2023-06-05 12:37 ` Nicolas Ferre
2023-06-14 19:41 ` Rob Herring
2023-06-03 20:02 ` [PATCH 16/21] " Varshini Rajendran
2023-06-03 20:02 ` [PATCH 17/21] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7 Varshini Rajendran
2023-06-05 6:43 ` Krzysztof Kozlowski
2023-06-05 13:04 ` Nicolas Ferre
2023-06-05 13:26 ` Conor Dooley
2023-06-16 17:32 ` Varshini.Rajendran
2023-06-05 13:33 ` Krzysztof Kozlowski
2023-06-03 20:02 ` [PATCH 18/21] power: reset: at91-reset: add reset support for sam9x7 soc Varshini Rajendran
2023-06-03 20:02 ` [PATCH 19/21] power: reset: at91-reset: add sdhwc " Varshini Rajendran
2023-06-03 20:02 ` [PATCH 20/21] dt-bindings: net: cdns,macb: add documentation for sam9x7 ethernet interface Varshini Rajendran
2023-06-05 6:42 ` Krzysztof Kozlowski
2023-06-14 19:42 ` Rob Herring
2023-06-03 20:02 ` [PATCH 21/21] net: macb: add support for gmac to sam9x7 Varshini Rajendran
2023-06-05 6:42 ` Krzysztof Kozlowski
2023-06-05 12:07 ` Nicolas Ferre
2023-06-05 12:21 ` Arnd Bergmann
2023-06-05 13:34 ` Krzysztof Kozlowski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=71d6e453-16bd-a5ce-bb95-8e615a944fb2@microchip.com \
--to=claudiu.beznea@microchip.com \
--cc=Balakrishnan.S@microchip.com \
--cc=Balamanikandan.Gunasundar@microchip.com \
--cc=Cristian.Birsan@microchip.com \
--cc=Dharma.B@microchip.com \
--cc=Durai.ManickamKR@microchip.com \
--cc=Hari.PrasathGE@microchip.com \
--cc=Manikandan.M@microchip.com \
--cc=Mihai.Sain@microchip.com \
--cc=Nayabbasha.Sayed@microchip.com \
--cc=Nicolas.Ferre@microchip.com \
--cc=Varshini.Rajendran@microchip.com \
--cc=alexandre.belloni@bootlin.com \
--cc=arnd@arndb.de \
--cc=broonie@kernel.org \
--cc=conor+dt@kernel.org \
--cc=davem@davemloft.net \
--cc=devicetree@vger.kernel.org \
--cc=edumazet@google.com \
--cc=gregkh@linuxfoundation.org \
--cc=gregory.clement@bootlin.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kuba@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=linux-usb@vger.kernel.org \
--cc=linux@armlinux.org.uk \
--cc=maz@kernel.org \
--cc=mturquette@baylibre.com \
--cc=netdev@vger.kernel.org \
--cc=pabeni@redhat.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=sre@kernel.org \
--cc=sudeep.holla@arm.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).