From: Conor Dooley <conor@kernel.org>
To: Xingyu Wu <xingyu.wu@starfivetech.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
William Qiu <william.qiu@starfivetech.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v7 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC
Date: Mon, 17 Jul 2023 19:14:16 +0100 [thread overview]
Message-ID: <20230717-easel-pessimist-5b7c4e5bed0a@spud> (raw)
In-Reply-To: <20230717023040.78860-1-xingyu.wu@starfivetech.com>
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Hey Xingyu,
On Mon, Jul 17, 2023 at 10:30:33AM +0800, Xingyu Wu wrote:
> This patch serises are to add PLL clocks driver and providers by writing
> and reading syscon registers for the StarFive JH7110 RISC-V SoC. And add
> documentation and nodes to describe StarFive System Controller(syscon)
> Registers. This patch serises are based on Linux 6.4.
>
> PLLs are high speed, low jitter frequency synthesizers in JH7110.
> Each PLL clock works in integer mode or fraction mode by some dividers,
> and the dividers are set in several syscon registers.
> The formula for calculating frequency is:
> Fvco = Fref * (NI + NF) / M / Q1
>
> The first patch adds docunmentation to describe PLL clock bindings,
> and the second patch adds documentation to decribe syscon registers.
> The patch 3 modifies the SYSCRG bindings and adds PLL clock inputs.
> The patch 4 adds driver to support PLL clocks for JH7110.
> The patch 5 modifies the system clock driver and can select the PLL clock
> source from PLL clocks driver. And the patch 6 adds the
> stg/sys/aon syscon nodes for JH7110 SoC. The last patch modifies the
> syscrg node in JH7110 dts file.
Just FYI, I have picked up the binding & clock portions of this series
and your other one adding the stg syscon. I've pushed them out here for
the test robots to have a look:
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=clk-starfive
If that passes, my plan is to send Stephen a PR for the lot, later this
week.
Thanks,
Conor.
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next prev parent reply other threads:[~2023-07-17 18:14 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-17 2:30 [PATCH v7 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu
2023-07-17 2:30 ` [PATCH v7 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-07-19 15:45 ` Emil Renner Berthing
2023-07-17 2:30 ` [PATCH v7 2/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu
2023-07-17 2:30 ` [PATCH v7 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-07-17 2:30 ` [PATCH v7 4/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-07-17 2:30 ` [PATCH v7 5/7] clk: starfive: jh7110-sys: Add PLL clocks source from DTS Xingyu Wu
2023-07-19 15:49 ` Emil Renner Berthing
2023-07-17 2:30 ` [PATCH v7 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu
2023-07-17 2:30 ` [PATCH v7 7/7] riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node Xingyu Wu
2023-07-17 18:14 ` Conor Dooley [this message]
2023-07-18 5:48 ` [PATCH v7 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu
2023-07-20 16:29 ` (subset) " Conor Dooley
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