From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
"Rob Herring" <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Conor Dooley <conor@kernel.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
Xingyu Wu <xingyu.wu@starfivetech.com>,
"William Qiu" <william.qiu@starfivetech.com>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: [PATCH v7 6/7] riscv: dts: starfive: jh7110: Add syscon nodes
Date: Mon, 17 Jul 2023 10:30:39 +0800 [thread overview]
Message-ID: <20230717023040.78860-7-xingyu.wu@starfivetech.com> (raw)
In-Reply-To: <20230717023040.78860-1-xingyu.wu@starfivetech.com>
From: William Qiu <william.qiu@starfivetech.com>
Add stg_syscon/sys_syscon/aon_syscon/PLL nodes for JH7110 SoC.
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index ec2e70011a73..c49f5570625c 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -386,6 +386,11 @@ i2c2: i2c@10050000 {
status = "disabled";
};
+ stg_syscon: syscon@10240000 {
+ compatible = "starfive,jh7110-stg-syscon", "syscon";
+ reg = <0x0 0x10240000 0x0 0x1000>;
+ };
+
uart3: serial@12000000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x12000000 0x0 0x10000>;
@@ -490,6 +495,17 @@ syscrg: clock-controller@13020000 {
#reset-cells = <1>;
};
+ sys_syscon: syscon@13030000 {
+ compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
+ reg = <0x0 0x13030000 0x0 0x1000>;
+
+ pllclk: clock-controller {
+ compatible = "starfive,jh7110-pll";
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+ };
+
sysgpio: pinctrl@13040000 {
compatible = "starfive,jh7110-sys-pinctrl";
reg = <0x0 0x13040000 0x0 0x10000>;
@@ -529,6 +545,12 @@ aoncrg: clock-controller@17000000 {
#reset-cells = <1>;
};
+ aon_syscon: syscon@17010000 {
+ compatible = "starfive,jh7110-aon-syscon", "syscon";
+ reg = <0x0 0x17010000 0x0 0x1000>;
+ #power-domain-cells = <1>;
+ };
+
aongpio: pinctrl@17020000 {
compatible = "starfive,jh7110-aon-pinctrl";
reg = <0x0 0x17020000 0x0 0x10000>;
--
2.25.1
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next prev parent reply other threads:[~2023-07-17 2:31 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-17 2:30 [PATCH v7 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu
2023-07-17 2:30 ` [PATCH v7 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-07-19 15:45 ` Emil Renner Berthing
2023-07-17 2:30 ` [PATCH v7 2/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu
2023-07-17 2:30 ` [PATCH v7 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-07-17 2:30 ` [PATCH v7 4/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-07-17 2:30 ` [PATCH v7 5/7] clk: starfive: jh7110-sys: Add PLL clocks source from DTS Xingyu Wu
2023-07-19 15:49 ` Emil Renner Berthing
2023-07-17 2:30 ` Xingyu Wu [this message]
2023-07-17 2:30 ` [PATCH v7 7/7] riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node Xingyu Wu
2023-07-17 18:14 ` [PATCH v7 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Conor Dooley
2023-07-18 5:48 ` Xingyu Wu
2023-07-20 16:29 ` (subset) " Conor Dooley
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