From: Andrew Jones <ajones@ventanamicro.com>
To: guoren@kernel.org
Cc: wefu@redhat.com, keescook@chromium.org, peterz@infradead.org,
unicorn_wang@outlook.com, atishp@atishpatra.org,
chao.wei@sophgo.com, bjorn@rivosinc.com,
linux-kernel@vger.kernel.org, xiaoguang.xing@sophgo.com,
conor.dooley@microchip.com, leobras@redhat.com,
palmer@dabbelt.com, jszhang@kernel.org, paul.walmsley@sifive.com,
Guo Ren <guoren@linux.alibaba.com>,
panqinglin2020@iscas.ac.cn, linux-riscv@lists.infradead.org,
wuwei2016@iscas.ac.cn
Subject: Re: Re: [PATCH V2 2/3] riscv: Add ARCH_HAS_PRETCHW support with Zibop
Date: Fri, 5 Jan 2024 14:31:39 +0100 [thread overview]
Message-ID: <20240105-6dba80fb50413c0869b0beb3@orel> (raw)
In-Reply-To: <20240102-7e62facbd8322db4dee4b0dd@orel>
On Tue, Jan 02, 2024 at 11:45:08AM +0100, Andrew Jones wrote:
>
> s/Zibop/Zicbop/ <<<$SUBJECT
>
> On Sun, Dec 31, 2023 at 03:29:52AM -0500, guoren@kernel.org wrote:
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > Enable Linux prefetchw primitive with Zibop cpufeature, which preloads
>
> Also s/Zibop/Zicbop/ here
>
> > cache line into L1 cache for the next write operation.
> >
> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> > Signed-off-by: Guo Ren <guoren@kernel.org>
> > ---
> > arch/riscv/include/asm/processor.h | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> > index f19f861cda54..8d3a2ab37678 100644
> > --- a/arch/riscv/include/asm/processor.h
> > +++ b/arch/riscv/include/asm/processor.h
> > @@ -13,6 +13,9 @@
> > #include <vdso/processor.h>
> >
> > #include <asm/ptrace.h>
> > +#include <asm/insn-def.h>
> > +#include <asm/alternative-macros.h>
> > +#include <asm/hwcap.h>
> >
> > #ifdef CONFIG_64BIT
> > #define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1))
> > @@ -106,6 +109,19 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset,
> > #define KSTK_EIP(tsk) (task_pt_regs(tsk)->epc)
> > #define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp)
> >
> > +#ifdef CONFIG_RISCV_ISA_ZICBOP
> > +#define ARCH_HAS_PREFETCHW
> > +
> > +#define PREFETCHW_ASM(x) \
> > + ALTERNATIVE(__nops(1), CBO_PREFETCH_W(x, 0), 0, \
> > + RISCV_ISA_EXT_ZICBOP, CONFIG_RISCV_ISA_ZICBOP)
> > +
> > +
> > +static inline void prefetchw(const void *x)
> > +{
> > + __asm__ __volatile__(PREFETCHW_ASM(%0) : : "r" (x) : "memory");
> > +}
>
> Shouldn't we create an interface which exposes the offset input of
> the instruction, allowing a sequence of calls to be unrolled? But
> I guess that could be put off until there's a need for it.
If we did expose offset, then, because it must be constant and also must
only have bits 5-11 set, then we could add a static assert. Something like
#define prefetchw_offset(base, offset) \
({ \
static_assert(__builtin_constant_p(offset) && !(offset & ~GENMASK(11, 5))); \
__asm__ __volatile__(PREFETCHW_ASM(%0, %1) : : "r" (x), "I" (offset) : "memory"); \
})
Probably overkill though...
Thanks,
drew
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next prev parent reply other threads:[~2024-01-05 13:31 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-31 8:29 [PATCH V2 0/3] riscv: Add Zicbop & prefetchw support guoren
2023-12-31 8:29 ` [PATCH V2 1/3] riscv: Add Zicbop instruction definitions & cpufeature guoren
2024-01-02 10:32 ` Andrew Jones
2024-01-03 6:13 ` Guo Ren
2024-01-03 6:49 ` Andrew Jones
2024-01-03 19:44 ` Andrew Jones
2024-01-03 19:06 ` Leonardo Bras
2024-01-03 9:31 ` Clément Léger
2024-01-03 12:00 ` Andrew Jones
2024-01-11 10:31 ` Clément Léger
2024-01-11 10:45 ` Andrew Jones
2024-01-11 10:49 ` Clément Léger
2024-01-11 11:12 ` Conor Dooley
2024-01-03 18:52 ` Leonardo Bras
2024-01-03 19:29 ` Andrew Jones
2024-01-03 20:33 ` Leonardo Bras
2024-01-04 9:47 ` Andrew Jones
2024-01-04 15:03 ` Leonardo Bras
2024-01-04 16:40 ` Andrew Jones
2024-01-04 17:43 ` Leonardo Bras
2024-01-05 13:24 ` Andrew Jones
2024-01-08 14:34 ` Leonardo Bras
2024-01-08 15:24 ` Andrew Jones
2024-01-08 16:14 ` Leonardo Bras
2024-01-03 19:48 ` Andrew Jones
2024-01-03 20:34 ` Leonardo Bras
2023-12-31 8:29 ` [PATCH V2 2/3] riscv: Add ARCH_HAS_PRETCHW support with Zibop guoren
2024-01-01 2:29 ` Guo Ren
2024-01-03 19:04 ` Leonardo Bras
2024-01-02 10:45 ` Andrew Jones
2024-01-03 6:19 ` Guo Ren
2024-01-03 19:56 ` Andrew Jones
2024-01-05 13:31 ` Andrew Jones [this message]
2023-12-31 8:29 ` [PATCH V2 3/3] riscv: xchg: Prefetch the destination word for sc.w guoren
2024-01-02 11:18 ` Andrew Jones
2024-01-03 6:15 ` Guo Ren
2024-01-03 19:45 ` Leonardo Bras
2024-01-04 1:24 ` Guo Ren
2024-01-04 3:56 ` Leonardo Bras
2024-01-04 8:14 ` Guo Ren
2024-01-04 14:17 ` Leonardo Bras
2024-01-05 1:13 ` Guo Ren
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