Re: [PATCH V2 2/3] riscv: Add ARCH_HAS_PRETCHW support with Zibop

From: Guo Ren <guoren@kernel.org>
To: paul.walmsley@sifive.com, palmer@dabbelt.com, guoren@kernel.org,
	 panqinglin2020@iscas.ac.cn, bjorn@rivosinc.com,
	conor.dooley@microchip.com,  leobras@redhat.com,
	peterz@infradead.org, keescook@chromium.org,
	 wuwei2016@iscas.ac.cn, xiaoguang.xing@sophgo.com,
	chao.wei@sophgo.com,  unicorn_wang@outlook.com, uwu@icenowy.me,
	jszhang@kernel.org, wefu@redhat.com,  atishp@atishpatra.org,
	ajones@ventanamicro.com
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	 Guo Ren <guoren@linux.alibaba.com>
Subject: Re: [PATCH V2 2/3] riscv: Add ARCH_HAS_PRETCHW support with Zibop
Date: Mon, 1 Jan 2024 10:29:21 +0800	[thread overview]
Message-ID: <CAJF2gTTZeN+rfG6szdB+J1QySQ2tAadwpG_zt2cRir7Bn+Yh4g@mail.gmail.com> (raw)
In-Reply-To: <20231231082955.16516-3-guoren@kernel.org>

On Sun, Dec 31, 2023 at 4:30 PM <guoren@kernel.org> wrote:
>
> From: Guo Ren <guoren@linux.alibaba.com>
>
> Enable Linux prefetchw primitive with Zibop cpufeature, which preloads
> cache line into L1 cache for the next write operation.
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@kernel.org>
> ---
>  arch/riscv/include/asm/processor.h | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> index f19f861cda54..8d3a2ab37678 100644
> --- a/arch/riscv/include/asm/processor.h
> +++ b/arch/riscv/include/asm/processor.h
> @@ -13,6 +13,9 @@
>  #include <vdso/processor.h>
>
>  #include <asm/ptrace.h>
> +#include <asm/insn-def.h>
> +#include <asm/alternative-macros.h>
> +#include <asm/hwcap.h>
>
>  #ifdef CONFIG_64BIT
>  #define DEFAULT_MAP_WINDOW     (UL(1) << (MMAP_VA_BITS - 1))
> @@ -106,6 +109,19 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset,
>  #define KSTK_EIP(tsk)          (task_pt_regs(tsk)->epc)
>  #define KSTK_ESP(tsk)          (task_pt_regs(tsk)->sp)
>
> +#ifdef CONFIG_RISCV_ISA_ZICBOP
> +#define ARCH_HAS_PREFETCHW
> +
> +#define PREFETCHW_ASM(x)                                               \
> +       ALTERNATIVE(__nops(1), CBO_PREFETCH_W(x, 0), 0,                 \
> +                   RISCV_ISA_EXT_ZICBOP, CONFIG_RISCV_ISA_ZICBOP)
The PREFETCHW_ASM(x) definition should be out of "ifdef
CONFIG_RISCV_ISA_ZICBOP... #endif", because xchg_small may use this
macro without CONFIG_RISCV_ISA_ZICBOP.

> +
> +
> +static inline void prefetchw(const void *x)
> +{
> +       __asm__ __volatile__(PREFETCHW_ASM(%0) : : "r" (x) : "memory");
> +}
> +#endif /* CONFIG_RISCV_ISA_ZICBOP */
>
>  /* Do necessary setup to start up a newly executed thread. */
>  extern void start_thread(struct pt_regs *regs,
> --
> 2.40.1
>


-- 
Best Regards
 Guo Ren

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