Re: [PATCH V2 3/3] riscv: xchg: Prefetch the destination word for sc.w

From: Guo Ren <guoren@kernel.org>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: wefu@redhat.com, keescook@chromium.org, peterz@infradead.org,
	unicorn_wang@outlook.com, atishp@atishpatra.org,
	chao.wei@sophgo.com, bjorn@rivosinc.com,
	linux-kernel@vger.kernel.org, xiaoguang.xing@sophgo.com,
	conor.dooley@microchip.com, leobras@redhat.com,
	palmer@dabbelt.com, jszhang@kernel.org, paul.walmsley@sifive.com,
	Guo Ren <guoren@linux.alibaba.com>,
	panqinglin2020@iscas.ac.cn, linux-riscv@lists.infradead.org,
	wuwei2016@iscas.ac.cn
Subject: Re: [PATCH V2 3/3] riscv: xchg: Prefetch the destination word for sc.w
Date: Wed, 3 Jan 2024 14:15:45 +0800	[thread overview]
Message-ID: <CAJF2gTQ7Oo8UKdPRs0GAAUsh9mDCgGucS8g8kuPzByaWVOtigw@mail.gmail.com> (raw)
In-Reply-To: <20240102-81391283df04c430d76c0eb0@orel>

On Tue, Jan 2, 2024 at 7:19 PM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Sun, Dec 31, 2023 at 03:29:53AM -0500, guoren@kernel.org wrote:
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > The cost of changing a cacheline from shared to exclusive state can be
> > significant, especially when this is triggered by an exclusive store,
> > since it may result in having to retry the transaction.
> >
> > This patch makes use of prefetch.w to prefetch cachelines for write
> > prior to lr/sc loops when using the xchg_small atomic routine.
> >
> > This patch is inspired by commit: 0ea366f5e1b6 ("arm64: atomics:
> > prefetch the destination word for write prior to stxr").
> >
> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> > Signed-off-by: Guo Ren <guoren@kernel.org>
> > ---
> >  arch/riscv/include/asm/cmpxchg.h | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
> > index 26cea2395aae..d7b9d7951f08 100644
> > --- a/arch/riscv/include/asm/cmpxchg.h
> > +++ b/arch/riscv/include/asm/cmpxchg.h
> > @@ -10,6 +10,7 @@
> >
> >  #include <asm/barrier.h>
> >  #include <asm/fence.h>
> > +#include <asm/processor.h>
> >
> >  #define __arch_xchg_masked(prepend, append, r, p, n)                 \
>
> Are you sure this is based on v6.7-rc7? Because I don't see this macro.
Oh, it is based on Leobras' patches. I would remove it in the next of version.

>
> >  ({                                                                   \
> > @@ -23,6 +24,7 @@
> >                                                                       \
> >       __asm__ __volatile__ (                                          \
> >              prepend                                                  \
> > +            PREFETCHW_ASM(%5)                                        \
> >              "0:      lr.w %0, %2\n"                                  \
> >              "        and  %1, %0, %z4\n"                             \
> >              "        or   %1, %1, %z3\n"                             \
> > @@ -30,7 +32,7 @@
> >              "        bnez %1, 0b\n"                                  \
> >              append                                                   \
> >              : "=&r" (__retx), "=&r" (__rc), "+A" (*(__ptr32b))       \
> > -            : "rJ" (__newx), "rJ" (~__mask)                          \
> > +            : "rJ" (__newx), "rJ" (~__mask), "rJ" (__ptr32b)         \
>
> I'm pretty sure we don't want to allow the J constraint for __ptr32b.
>
> >              : "memory");                                             \
> >                                                                       \
> >       r = (__typeof__(*(p)))((__retx & __mask) >> __s);               \
> > --
> > 2.40.1
> >
>
> Thanks,
> drew


-- 
Best Regards
 Guo Ren

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