From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
To: kernel@esmil.dk, conor@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu,
mturquette@baylibre.com, sboyd@kernel.org,
p.zabel@pengutronix.de, emil.renner.berthing@canonical.com,
hal.feng@starfivetech.com, xingyu.wu@starfivetech.com
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
jeeheng.sia@starfivetech.com, leyfoon.tan@starfivetech.com,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: [RFC v3 13/16] dt-bindings: clock: Add StarFive JH8100 Always-On clock and reset generator
Date: Wed, 10 Jan 2024 21:31:25 +0800 [thread overview]
Message-ID: <20240110133128.286657-14-jeeheng.sia@starfivetech.com> (raw)
In-Reply-To: <20240110133128.286657-1-jeeheng.sia@starfivetech.com>
Add bindings for the Always-On clock and reset generator (AONCRG) on
JH8100 SoC.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../clock/starfive,jh8100-aoncrg.yaml | 74 +++++++++++++++++++
.../dt-bindings/clock/starfive,jh8100-crg.h | 67 +++++++++++++++++
.../dt-bindings/reset/starfive,jh8100-crg.h | 16 ++++
3 files changed, 157 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml
new file mode 100644
index 000000000000..4ae1ef827fc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh8100-aoncrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH8100 Always-On Clock and Reset Generator
+
+maintainers:
+ - Sia Jee Heng <jeeheng.sia@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jh8100-aoncrg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main Oscillator (24 MHz)
+ - description: GMAC0 RMII func
+ - description: GMAC0 RGMII func
+ - description: AON 125MHz clock
+ - description: AON 2000MHz clock
+ - description: AON 200MHz clock
+ - description: AON 667MHz clock
+ - description: RTC clock
+
+ clock-names:
+ items:
+ - const: osc
+ - const: gmac0-rmii-func
+ - const: gmac0-rgmii-func
+ - const: aon125
+ - const: aon2000
+ - const: aon200
+ - const: aon667
+ - const: rtc
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh8100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive,jh8100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive,jh8100-crg.h>
+
+ clock-controller@1f310000 {
+ compatible = "starfive,jh8100-aoncrg";
+ reg = <0x1f310000 0x10000>;
+ clocks = <&osc>, <&gmac0_rmii_func>, <&gmac0_rgmii_func>, <&aon125>,
+ <&aon2000>, <&aon200>, <&aon667>, <&rtc>;
+ clock-names = "osc", "gmac0-rmii-func", "gmac0-rgmii-func", "aon125",
+ "aon2000", "aon200", "aon667", "rtc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h
index 7b337c1495be..8207d5a2f4b3 100644
--- a/include/dt-bindings/clock/starfive,jh8100-crg.h
+++ b/include/dt-bindings/clock/starfive,jh8100-crg.h
@@ -351,4 +351,71 @@
#define JH8100_SWCLK_JPEG_ICG_EN 8
#define JH8100_SWCLK_VDEC_ICG_EN 9
+/* AONCRG clocks */
+#define JH8100_AONCLK_GMAC0_RMII_REFIN 0
+#define JH8100_AONCLK_GMAC0_RGMII_RXIN 1
+#define JH8100_AONCLK_GMAC0_GTXCLK 2
+#define JH8100_AONCLK_AON_1000 3
+#define JH8100_AONCLK_AON_400 4
+#define JH8100_AONCLK_AON_400_POSTOSC 5
+#define JH8100_AONCLK_AON_500 6
+#define JH8100_AONCLK_AON_500_POSTOSC 7
+#define JH8100_AONCLK_XSPI_PHY 8
+#define JH8100_AONCLK_AON_100 9
+#define JH8100_AONCLK_AON_100_POSTOSC 10
+#define JH8100_AONCLK_AON_50_POSTOSC 11
+#define JH8100_AONCLK_DDR50_POSTOCC_ICG 12
+#define JH8100_AONCLK_DDR100_POSTOCC_ICG 13
+#define JH8100_AONCLK_PUFRT_APB 14
+#define JH8100_AONCLK_RTC_HMS_APB 15
+#define JH8100_AONCLK_RTC_INTERNAL 16
+#define JH8100_AONCLK_RTC_HMS_OSC32K 17
+#define JH8100_AONCLK_RTC_HMS_CAL 18
+#define JH8100_AONCLK_GMAC0_AXI128_AHB 19
+#define JH8100_AONCLK_GMAC0_AXI128_MSTRCLK 20
+#define JH8100_AONCLK_GMAC0_AXI128_AXI 21
+#define JH8100_AONCLK_GMAC0_RMII_RTX 22
+#define JH8100_AONCLK_GMAC0_AXI128_TX 23
+#define JH8100_AONCLK_GMAC0_AXI128_TX_INV 24
+#define JH8100_AONCLK_GMAC0_AXI128_RX 25
+#define JH8100_AONCLK_GMAC0_AXI128_RX_INV 26
+#define JH8100_AONCLK_GMAC0_GTXC 27
+#define JH8100_AONCLK_XSPI_AXI 28
+#define JH8100_AONCLK_XSPI_APB 29
+#define JH8100_AONCLK_XSPI_XSPI_PHY 30
+#define JH8100_AONCLK_TVSENSOR_PCLK 31
+#define JH8100_AONCLK_TVSENSOR_TSADC 32
+#define JH8100_AONCLK_TVSENSOR_BG 33
+#define JH8100_AONCLK_MEU_PCLK_AP 34
+#define JH8100_AONCLK_MEU_PCLK_SCP 35
+#define JH8100_AONCLK_MEU_MEM_AXI 36
+#define JH8100_AONCLK_AXIMEM_128B_ACLK 37
+#define JH8100_AONCLK_APB2BISR_APB 38
+#define JH8100_AONCLK_APB2BISR_BISR 39
+#define JH8100_AONCLK_EMMC_S_PCLK 40
+#define JH8100_AONCLK_EMMC_MSTRCLK 41
+#define JH8100_AONCLK_EMMC 42
+#define JH8100_AONCLK_EMMC_SDMCLK 43
+#define JH8100_AONCLK_EMMC_SDPHY_PCLK 44
+#define JH8100_AONCLK_SDIO0_PCLK 45
+#define JH8100_AONCLK_SDIO0_MSTRCLK 46
+#define JH8100_AONCLK_SDIO0 47
+#define JH8100_AONCLK_SDIO0_SDMCLK 48
+#define JH8100_AONCLK_SDIO0_SDPHY_PCLK 49
+#define JH8100_AONCLK_HCLK 50
+#define JH8100_AONCLK_ACLK 51
+#define JH8100_AONCLK_PERF_MSTRCLK 52
+#define JH8100_AONCLK_PERF_SLVCLK 53
+#define JH8100_AONCLK_GCLK0 54
+#define JH8100_AONCLK_GCLK_OSC 55
+#define JH8100_AONCLK_RTC_ICG_EN 56
+#define JH8100_AONCLK_GMAC0_ICG_EN 57
+#define JH8100_AONCLK_XSPI_ICG_EN 58
+#define JH8100_AONCLK_TVSENSOR0_ICG_EN 59
+#define JH8100_AONCLK_MEU_ICG_EN 60
+#define JH8100_AONCLK_APB2BISR_ICG_EN 61
+#define JH8100_AONCLK_EMMC_ICG_EN 62
+#define JH8100_AONCLK_SDIO0_ICG_EN 63
+#define JH8100_AONCLK_TOP_ICG_EN 64
+
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */
diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h
index de4f25dc301d..23f15d4be22f 100644
--- a/include/dt-bindings/reset/starfive,jh8100-crg.h
+++ b/include/dt-bindings/reset/starfive,jh8100-crg.h
@@ -99,4 +99,20 @@
#define JH8100_SWRST_VC9000D 2
#define JH8100_SWRST_DDR_TVSENSOR 3
+/*
+ * AONCRG resets: assert0
+ */
+#define JH8100_AONRST_AON_IOMUX_PRESETN 0
+#define JH8100_AONRST_RTC 1
+#define JH8100_AONRST_GMAC0 2
+#define JH8100_AONRST_XSPI 3
+#define JH8100_AONRST_TVSENSOR 4
+#define JH8100_AONRST_MEU 5
+#define JH8100_AONRST_AXIMEM_128B_ARESET 6
+#define JH8100_AONRST_DFT_APB2BISR_APB 7
+#define JH8100_AONRST_SDIO0 8
+#define JH8100_AONRST_EMMC 9
+#define JH8100_AONRST_TOP 10
+#define JH8100_AONRST_IRQ_CTRL 11
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-01-10 13:32 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-10 13:31 [RFC v3 00/16] Basic clock and reset support for StarFive JH8100 RISC-V SoC Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 01/16] reset: starfive: Rename file name "jh71x0" to "common" Sia Jee Heng
2024-03-22 9:19 ` Hal Feng
2024-01-10 13:31 ` [RFC v3 02/16] reset: starfive: Convert the word "jh71x0" to "starfive" Sia Jee Heng
2024-03-22 9:33 ` Hal Feng
2024-01-10 13:31 ` [RFC v3 03/16] clk: starfive: Rename file name "jh71x0" to "common" Sia Jee Heng
2024-03-22 9:34 ` Hal Feng
2024-01-10 13:31 ` [RFC v3 04/16] clk: starfive: Convert the word "jh71x0" to "starfive" Sia Jee Heng
2024-03-22 9:36 ` Hal Feng
2024-01-10 13:31 ` [RFC v3 05/16] dt-bindings: clock: Add StarFive JH8100 System clock and reset generator Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 06/16] clk: starfive: Add JH8100 System clock generator driver Sia Jee Heng
2024-04-11 7:45 ` Stephen Boyd
2024-01-10 13:31 ` [RFC v3 07/16] dt-bindings: clock: Add StarFive JH8100 North-West clock and reset generator Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 08/16] clk: starfive: Add JH8100 North-West clock generator driver Sia Jee Heng
2024-04-11 7:49 ` Stephen Boyd
2024-01-10 13:31 ` [RFC v3 09/16] dt-bindings: clock: Add StarFive JH8100 North-East clock and reset generator Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 10/16] clk: starfive: Add JH8100 North-East clock generator driver Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 11/16] dt-bindings: clock: Add StarFive JH8100 South-West clock and reset generator Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 12/16] clk: starfive: Add JH8100 South-West clock generator driver Sia Jee Heng
2024-01-10 13:31 ` Sia Jee Heng [this message]
2024-01-10 13:31 ` [RFC v3 14/16] clk: starfive: Add JH8100 Always-On " Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 15/16] reset: starfive: Add StarFive JH8100 reset driver Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes Sia Jee Heng
2024-04-11 7:40 ` [RFC v3 00/16] Basic clock and reset support for StarFive JH8100 RISC-V SoC Stephen Boyd
2024-04-11 10:29 ` Conor Dooley
2024-04-12 3:00 ` Stephen Boyd
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240110133128.286657-14-jeeheng.sia@starfivetech.com \
--to=jeeheng.sia@starfivetech.com \
--cc=aou@eecs.berkeley.edu \
--cc=conor@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=emil.renner.berthing@canonical.com \
--cc=hal.feng@starfivetech.com \
--cc=kernel@esmil.dk \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=krzysztof.kozlowski@linaro.org \
--cc=leyfoon.tan@starfivetech.com \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=mturquette@baylibre.com \
--cc=p.zabel@pengutronix.de \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=xingyu.wu@starfivetech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).