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From: Stephen Boyd <sboyd@kernel.org>
To: Sia Jee Heng <jeeheng.sia@starfivetech.com>,
	aou@eecs.berkeley.edu, conor@kernel.org,
	emil.renner.berthing@canonical.com, hal.feng@starfivetech.com,
	kernel@esmil.dk, krzysztof.kozlowski+dt@linaro.org,
	mturquette@baylibre.com, p.zabel@pengutronix.de,
	palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org,
	xingyu.wu@starfivetech.com
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	jeeheng.sia@starfivetech.com, leyfoon.tan@starfivetech.com
Subject: Re: [RFC v3 06/16] clk: starfive: Add JH8100 System clock generator driver
Date: Thu, 11 Apr 2024 00:45:43 -0700	[thread overview]
Message-ID: <deb23094f40df7df9e7330e95af4e64d.sboyd@kernel.org> (raw)
In-Reply-To: <20240110133128.286657-7-jeeheng.sia@starfivetech.com>

Quoting Sia Jee Heng (2024-01-10 05:31:18)
> diff --git a/drivers/clk/starfive/clk-starfive-jh8100-sys.c b/drivers/clk/starfive/clk-starfive-jh8100-sys.c
> new file mode 100644
> index 000000000000..6d7e750dce82
> --- /dev/null
> +++ b/drivers/clk/starfive/clk-starfive-jh8100-sys.c
> @@ -0,0 +1,415 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * StarFive JH8100 System Clock Driver
> + *
> + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> + *
> + * Author: Jee Heng Sia <jeeheng.sia@starfivetech.com>
> + *
> + */
> +
> +#include <linux/clk.h>

Drop this unused include.

> +#include <linux/auxiliary_bus.h>
> +#include <linux/clk-provider.h>
> +#include <linux/init.h>
> +#include <linux/io.h>

Is this include used in this file?

> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include <soc/starfive/reset-starfive-common.h>
> +
> +#include <dt-bindings/clock/starfive,jh8100-crg.h>
> +
> +#include "clk-starfive-jh8100.h"
> +
> +#define JH8100_SYSCLK_NUM_CLKS                 (JH8100_SYSCLK_NNE_ICG_EN + 1)
> +
[...]
> +
> +static void jh8100_reset_adev_release(struct device *dev)
> +{
> +       struct auxiliary_device *adev = to_auxiliary_dev(dev);
> +       struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev);
> +
> +       kfree(rdev);
> +}
> +
> +int jh8100_reset_controller_register(struct starfive_clk_priv *priv,

Just pass 'dev' and 'base' instead.

> +                                    const char *adev_name,
> +                                    u32 adev_id)
> +{
> +       struct starfive_reset_adev *rdev;
> +       struct auxiliary_device *adev;
> +       int ret;
> +
> +       rdev = kzalloc(sizeof(*rdev), GFP_KERNEL);
> +       if (!rdev)
> +               return -ENOMEM;
> +
> +       rdev->base = priv->base;
> +
> +       adev = &rdev->adev;
> +       adev->name = adev_name;
> +       adev->dev.parent = priv->dev;
> +       adev->dev.release = jh8100_reset_adev_release;
> +       adev->id = adev_id;
> +
> +       ret = auxiliary_device_init(adev);
> +       if (ret)
> +               return ret;
> +
> +       ret = auxiliary_device_add(adev);
> +       if (ret) {
> +               auxiliary_device_uninit(adev);
> +               return ret;
> +       }
> +
> +       return devm_add_action_or_reset(priv->dev,
> +                                       jh8100_reset_unregister_adev, adev);
> +}
> +EXPORT_SYMBOL_GPL(jh8100_reset_controller_register);

Move this to drivers/reset/ please.

> +
> +static int __init jh8100_syscrg_probe(struct platform_device *pdev)
> +{
> +       struct starfive_clk_priv *priv;
> +       unsigned int idx;
> +       int ret;
> +
> +       priv = devm_kzalloc(&pdev->dev,
> +                           struct_size(priv, reg, JH8100_SYSCLK_NUM_CLKS),
> +                           GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       spin_lock_init(&priv->rmw_lock);
> +       priv->dev = &pdev->dev;
> +       priv->base = devm_platform_ioremap_resource(pdev, 0);
> +       if (IS_ERR(priv->base))
> +               return PTR_ERR(priv->base);
[...]
> +
> +       ret = devm_of_clk_add_hw_provider(&pdev->dev, jh8100_sysclk_get, priv);
> +       if (ret)
> +               return ret;
> +
> +       return jh8100_reset_controller_register(priv, "rst-sys", 0);
> +}
> +
> +static const struct of_device_id jh8100_syscrg_match[] = {
> +       { .compatible = "starfive,jh8100-syscrg" },
> +       { /* sentinel */ }
> +};
> +
> +static struct platform_driver jh8100_syscrg_driver = {
> +       .driver = {
> +               .name = "clk-starfive-jh8100-sys",
> +               .of_match_table = jh8100_syscrg_match,
> +               .suppress_bind_attrs = true,
> +       },
> +};
> +builtin_platform_driver_probe(jh8100_syscrg_driver, jh8100_syscrg_probe);
> diff --git a/drivers/clk/starfive/clk-starfive-jh8100.h b/drivers/clk/starfive/clk-starfive-jh8100.h
> new file mode 100644
> index 000000000000..9b69a56fe5fc
> --- /dev/null
> +++ b/drivers/clk/starfive/clk-starfive-jh8100.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __CLK_STARFIVE_JH8100_H
> +#define __CLK_STARFIVE_JH8100_H
> +
> +#include "clk-starfive-common.h"

Drop this include.

> +
> +int jh8100_reset_controller_register(struct starfive_clk_priv *priv,

Forward declare starfive_clk_priv instead.

> +                                    const char *adev_name,
> +                                    u32 adev_id);

Why is this header here at all?

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  reply	other threads:[~2024-04-11  7:45 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-10 13:31 [RFC v3 00/16] Basic clock and reset support for StarFive JH8100 RISC-V SoC Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 01/16] reset: starfive: Rename file name "jh71x0" to "common" Sia Jee Heng
2024-03-22  9:19   ` Hal Feng
2024-01-10 13:31 ` [RFC v3 02/16] reset: starfive: Convert the word "jh71x0" to "starfive" Sia Jee Heng
2024-03-22  9:33   ` Hal Feng
2024-01-10 13:31 ` [RFC v3 03/16] clk: starfive: Rename file name "jh71x0" to "common" Sia Jee Heng
2024-03-22  9:34   ` Hal Feng
2024-01-10 13:31 ` [RFC v3 04/16] clk: starfive: Convert the word "jh71x0" to "starfive" Sia Jee Heng
2024-03-22  9:36   ` Hal Feng
2024-01-10 13:31 ` [RFC v3 05/16] dt-bindings: clock: Add StarFive JH8100 System clock and reset generator Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 06/16] clk: starfive: Add JH8100 System clock generator driver Sia Jee Heng
2024-04-11  7:45   ` Stephen Boyd [this message]
2024-01-10 13:31 ` [RFC v3 07/16] dt-bindings: clock: Add StarFive JH8100 North-West clock and reset generator Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 08/16] clk: starfive: Add JH8100 North-West clock generator driver Sia Jee Heng
2024-04-11  7:49   ` Stephen Boyd
2024-01-10 13:31 ` [RFC v3 09/16] dt-bindings: clock: Add StarFive JH8100 North-East clock and reset generator Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 10/16] clk: starfive: Add JH8100 North-East clock generator driver Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 11/16] dt-bindings: clock: Add StarFive JH8100 South-West clock and reset generator Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 12/16] clk: starfive: Add JH8100 South-West clock generator driver Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 13/16] dt-bindings: clock: Add StarFive JH8100 Always-On clock and reset generator Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 14/16] clk: starfive: Add JH8100 Always-On clock generator driver Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 15/16] reset: starfive: Add StarFive JH8100 reset driver Sia Jee Heng
2024-01-10 13:31 ` [RFC v3 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes Sia Jee Heng
2024-04-11  7:40 ` [RFC v3 00/16] Basic clock and reset support for StarFive JH8100 RISC-V SoC Stephen Boyd
2024-04-11 10:29   ` Conor Dooley
2024-04-12  3:00     ` Stephen Boyd

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