Re: [RFC v3 00/16] Basic clock and reset support for StarFive JH8100 RISC-V SoC

From: Stephen Boyd <sboyd@kernel.org>
To: Sia Jee Heng <jeeheng.sia@starfivetech.com>,
	aou@eecs.berkeley.edu, conor@kernel.org,
	emil.renner.berthing@canonical.com, hal.feng@starfivetech.com,
	kernel@esmil.dk, krzysztof.kozlowski+dt@linaro.org,
	mturquette@baylibre.com, p.zabel@pengutronix.de,
	palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org,
	xingyu.wu@starfivetech.com
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	jeeheng.sia@starfivetech.com, leyfoon.tan@starfivetech.com
Subject: Re: [RFC v3 00/16] Basic clock and reset support for StarFive JH8100 RISC-V SoC
Date: Thu, 11 Apr 2024 00:40:09 -0700	[thread overview]
Message-ID: <a83130157adf70f6f58f4d2e6b9d25db.sboyd@kernel.org> (raw)
In-Reply-To: <20240110133128.286657-1-jeeheng.sia@starfivetech.com>

Quoting Sia Jee Heng (2024-01-10 05:31:12)
> This patch series enabled basic clock & reset support for StarFive
> JH8100 SoC.
> 
> This patch series depends on the Initial device tree support for
> StarFive JH8100 SoC patch series which can be found at [1].
> 
> As it is recommended to refrain from merging fundamental patches like
> Device Tree, Clock & Reset, and PINCTRL tested on FPGA/Emulator, into the
> RISC-V Mainline, this patch series has been renamed to "RFC" patches. Yet,
> thanks to the reviewers who have reviewed the patches at [2]. The changes
> are captured below.

I don't think that's what should be happening. Instead, clk patches
should be sent to clk maintainers, reset patches to reset maintainers,
pinctrl patches to pinctrl maintainers, etc. The DTS can be sent later
when it's no longer an FPGA/Emulator? Right now I'm ignoring this series
because it's tagged as an RFC.

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