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From: Samuel Holland <samuel.holland@sifive.com>
To: Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	Alexandre Ghiti <alexghiti@rivosinc.com>,
	Jisheng Zhang <jszhang@kernel.org>,
	Yunhui Cui <cuiyunhui@bytedance.com>,
	Samuel Holland <samuel.holland@sifive.com>
Subject: [PATCH v5 01/13] riscv: Flush the instruction cache during SMP bringup
Date: Thu, 29 Feb 2024 15:21:42 -0800	[thread overview]
Message-ID: <20240229232211.161961-2-samuel.holland@sifive.com> (raw)
In-Reply-To: <20240229232211.161961-1-samuel.holland@sifive.com>

Instruction cache flush IPIs are sent only to CPUs in cpu_online_mask,
so they will not target a CPU until it calls set_cpu_online() earlier in
smp_callin(). As a result, if instruction memory is modified between the
CPU coming out of reset and that point, then its instruction cache may
contain stale data. Therefore, the instruction cache must be flushed
after the set_cpu_online() synchronization point.

Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable")
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

(no changes since v4)

Changes in v4:
 - New patch for v4

 arch/riscv/kernel/smpboot.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index cfbe4b840d42..e1b612f37dd9 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -26,7 +26,7 @@
 #include <linux/sched/task_stack.h>
 #include <linux/sched/mm.h>
 
-#include <asm/cpufeature.h>
+#include <asm/cacheflush.h>
 #include <asm/cpu_ops.h>
 #include <asm/irq.h>
 #include <asm/mmu_context.h>
@@ -238,9 +238,10 @@ asmlinkage __visible void smp_callin(void)
 	riscv_user_isa_enable();
 
 	/*
-	 * Remote TLB flushes are ignored while the CPU is offline, so emit
-	 * a local TLB flush right now just in case.
+	 * Remote cache and TLB flushes are ignored while the CPU is offline,
+	 * so flush them both right now just in case.
 	 */
+	local_flush_icache_all();
 	local_flush_tlb_all();
 	complete(&cpu_running);
 	/*
-- 
2.43.1


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  reply	other threads:[~2024-02-29 23:22 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-29 23:21 [PATCH v5 00/13] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2024-02-29 23:21 ` Samuel Holland [this message]
2024-02-29 23:21 ` [PATCH v5 02/13] riscv: Factor out page table TLB synchronization Samuel Holland
2024-02-29 23:21 ` [PATCH v5 03/13] riscv: Use IPIs for remote cache/TLB flushes by default Samuel Holland
2024-03-11  3:06   ` Stefan O'Rear
2024-03-11  4:04     ` Anup Patel
2024-03-11  4:12       ` Anup Patel
2024-03-11  4:42         ` Samuel Holland
2024-02-29 23:21 ` [PATCH v5 04/13] riscv: mm: Broadcast kernel TLB flushes only when needed Samuel Holland
2024-02-29 23:21 ` [PATCH v5 05/13] riscv: Only send remote fences when some other CPU is online Samuel Holland
2024-02-29 23:21 ` [PATCH v5 06/13] riscv: mm: Combine the SMP and UP TLB flush code Samuel Holland
2024-03-01  2:12   ` [External] " yunhui cui
2024-03-01  2:34     ` Samuel Holland
2024-02-29 23:21 ` [PATCH v5 07/13] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2024-02-29 23:21 ` [PATCH v5 08/13] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 Samuel Holland
2024-03-01  2:48   ` [External] " yunhui cui
2024-03-12  0:35     ` Samuel Holland
2024-03-12  1:51       ` yunhui cui
2024-02-29 23:21 ` [PATCH v5 09/13] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2024-02-29 23:21 ` [PATCH v5 10/13] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2024-02-29 23:21 ` [PATCH v5 11/13] riscv: mm: Make asid_bits a local variable Samuel Holland
2024-02-29 23:21 ` [PATCH v5 12/13] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2024-02-29 23:21 ` [PATCH v5 13/13] riscv: mm: Always use an ASID to flush mm contexts Samuel Holland
2024-03-01  9:31 ` [PATCH v5 00/13] riscv: ASID-related and UP-related TLB flush enhancements Conor Dooley

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