From: Conor Dooley <conor.dooley@microchip.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<linux-mm@kvack.org>, Alexandre Ghiti <alexghiti@rivosinc.com>,
Jisheng Zhang <jszhang@kernel.org>,
Yunhui Cui <cuiyunhui@bytedance.com>
Subject: Re: [PATCH v5 00/13] riscv: ASID-related and UP-related TLB flush enhancements
Date: Fri, 1 Mar 2024 09:31:04 +0000 [thread overview]
Message-ID: <20240301-dreadful-discourse-6f1bb453d9c6@wendy> (raw)
In-Reply-To: <20240229232211.161961-1-samuel.holland@sifive.com>
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On Thu, Feb 29, 2024 at 03:21:41PM -0800, Samuel Holland wrote:
> Samuel Holland (13):
> riscv: Flush the instruction cache during SMP bringup
> riscv: Factor out page table TLB synchronization
From here onwards, fails on 32-bit, bunch of
implicit-function-declaration stuff.
> riscv: Use IPIs for remote cache/TLB flushes by default
> riscv: mm: Broadcast kernel TLB flushes only when needed
> riscv: Only send remote fences when some other CPU is online
> riscv: mm: Combine the SMP and UP TLB flush code
> riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma
> riscv: Avoid TLB flush loops when affected by SiFive CIP-1200
> riscv: mm: Introduce cntx2asid/cntx2version helper macros
> riscv: mm: Use a fixed layout for the MM context ID
> riscv: mm: Make asid_bits a local variable
> riscv: mm: Preserve global TLB entries when switching contexts
> riscv: mm: Always use an ASID to flush mm contexts
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prev parent reply other threads:[~2024-03-01 9:32 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-29 23:21 [PATCH v5 00/13] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2024-02-29 23:21 ` [PATCH v5 01/13] riscv: Flush the instruction cache during SMP bringup Samuel Holland
2024-02-29 23:21 ` [PATCH v5 02/13] riscv: Factor out page table TLB synchronization Samuel Holland
2024-02-29 23:21 ` [PATCH v5 03/13] riscv: Use IPIs for remote cache/TLB flushes by default Samuel Holland
2024-03-11 3:06 ` Stefan O'Rear
2024-03-11 4:04 ` Anup Patel
2024-03-11 4:12 ` Anup Patel
2024-03-11 4:42 ` Samuel Holland
2024-02-29 23:21 ` [PATCH v5 04/13] riscv: mm: Broadcast kernel TLB flushes only when needed Samuel Holland
2024-02-29 23:21 ` [PATCH v5 05/13] riscv: Only send remote fences when some other CPU is online Samuel Holland
2024-02-29 23:21 ` [PATCH v5 06/13] riscv: mm: Combine the SMP and UP TLB flush code Samuel Holland
2024-03-01 2:12 ` [External] " yunhui cui
2024-03-01 2:34 ` Samuel Holland
2024-02-29 23:21 ` [PATCH v5 07/13] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2024-02-29 23:21 ` [PATCH v5 08/13] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 Samuel Holland
2024-03-01 2:48 ` [External] " yunhui cui
2024-03-12 0:35 ` Samuel Holland
2024-03-12 1:51 ` yunhui cui
2024-02-29 23:21 ` [PATCH v5 09/13] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2024-02-29 23:21 ` [PATCH v5 10/13] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2024-02-29 23:21 ` [PATCH v5 11/13] riscv: mm: Make asid_bits a local variable Samuel Holland
2024-02-29 23:21 ` [PATCH v5 12/13] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2024-02-29 23:21 ` [PATCH v5 13/13] riscv: mm: Always use an ASID to flush mm contexts Samuel Holland
2024-03-01 9:31 ` Conor Dooley [this message]
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