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From: Samuel Holland <samuel.holland@sifive.com>
To: Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	Alexandre Ghiti <alexghiti@rivosinc.com>,
	Jisheng Zhang <jszhang@kernel.org>,
	Yunhui Cui <cuiyunhui@bytedance.com>,
	Samuel Holland <samuel.holland@sifive.com>
Subject: [PATCH v5 04/13] riscv: mm: Broadcast kernel TLB flushes only when needed
Date: Thu, 29 Feb 2024 15:21:45 -0800	[thread overview]
Message-ID: <20240229232211.161961-5-samuel.holland@sifive.com> (raw)
In-Reply-To: <20240229232211.161961-1-samuel.holland@sifive.com>

__flush_tlb_range() avoids broadcasting TLB flushes when an mm context
is only active on the local CPU. Apply this same optimization to TLB
flushes of kernel memory when only one CPU is online. This check can be
constant-folded when SMP is disabled.

Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

(no changes since v4)

Changes in v4:
 - New patch for v4

 arch/riscv/mm/tlbflush.c | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)

diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 0373661bd1c4..8cdb082f00ca 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -102,22 +102,15 @@ static void __flush_tlb_range(struct cpumask *cmask, unsigned long asid,
 			      unsigned long start, unsigned long size,
 			      unsigned long stride)
 {
-	bool broadcast;
+	unsigned int cpu;
 
 	if (cpumask_empty(cmask))
 		return;
 
-	if (cmask != cpu_online_mask) {
-		unsigned int cpuid;
+	cpu = get_cpu();
 
-		cpuid = get_cpu();
-		/* check if the tlbflush needs to be sent to other CPUs */
-		broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids;
-	} else {
-		broadcast = true;
-	}
-
-	if (!broadcast) {
+	/* Check if the TLB flush needs to be sent to other CPUs. */
+	if (cpumask_any_but(cmask, cpu) >= nr_cpu_ids) {
 		local_flush_tlb_range_asid(start, size, stride, asid);
 	} else if (riscv_use_sbi_for_rfence()) {
 		sbi_remote_sfence_vma_asid(cmask, start, size, asid);
@@ -131,8 +124,7 @@ static void __flush_tlb_range(struct cpumask *cmask, unsigned long asid,
 		on_each_cpu_mask(cmask, __ipi_flush_tlb_range_asid, &ftd, 1);
 	}
 
-	if (cmask != cpu_online_mask)
-		put_cpu();
+	put_cpu();
 }
 
 static inline unsigned long get_mm_asid(struct mm_struct *mm)
-- 
2.43.1


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  parent reply	other threads:[~2024-02-29 23:22 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-29 23:21 [PATCH v5 00/13] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2024-02-29 23:21 ` [PATCH v5 01/13] riscv: Flush the instruction cache during SMP bringup Samuel Holland
2024-02-29 23:21 ` [PATCH v5 02/13] riscv: Factor out page table TLB synchronization Samuel Holland
2024-02-29 23:21 ` [PATCH v5 03/13] riscv: Use IPIs for remote cache/TLB flushes by default Samuel Holland
2024-03-11  3:06   ` Stefan O'Rear
2024-03-11  4:04     ` Anup Patel
2024-03-11  4:12       ` Anup Patel
2024-03-11  4:42         ` Samuel Holland
2024-02-29 23:21 ` Samuel Holland [this message]
2024-02-29 23:21 ` [PATCH v5 05/13] riscv: Only send remote fences when some other CPU is online Samuel Holland
2024-02-29 23:21 ` [PATCH v5 06/13] riscv: mm: Combine the SMP and UP TLB flush code Samuel Holland
2024-03-01  2:12   ` [External] " yunhui cui
2024-03-01  2:34     ` Samuel Holland
2024-02-29 23:21 ` [PATCH v5 07/13] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2024-02-29 23:21 ` [PATCH v5 08/13] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 Samuel Holland
2024-03-01  2:48   ` [External] " yunhui cui
2024-03-12  0:35     ` Samuel Holland
2024-03-12  1:51       ` yunhui cui
2024-02-29 23:21 ` [PATCH v5 09/13] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2024-02-29 23:21 ` [PATCH v5 10/13] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2024-02-29 23:21 ` [PATCH v5 11/13] riscv: mm: Make asid_bits a local variable Samuel Holland
2024-02-29 23:21 ` [PATCH v5 12/13] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2024-02-29 23:21 ` [PATCH v5 13/13] riscv: mm: Always use an ASID to flush mm contexts Samuel Holland
2024-03-01  9:31 ` [PATCH v5 00/13] riscv: ASID-related and UP-related TLB flush enhancements Conor Dooley

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