Re: [PATCH 4/4] can: sun4i_can: Correctly set acceptance registers on the D1

From: "Jernej Škrabec" <jernej.skrabec@gmail.com>
To: linux-sunxi@lists.linux.dev, Jookia <contact@jookia.org>
Cc: John Watts <contact@jookia.org>,
	devicetree@vger.kernel.org, linux-can@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Fabien Poussin <fabien.poussin@gmail.com>,
	Samuel Holland <samuel@sholland.org>,
	Chen-Yu Tsai <wens@csie.org>
Subject: Re: [PATCH 4/4] can: sun4i_can: Correctly set acceptance registers on the D1
Date: Sun, 16 Jul 2023 18:45:25 +0200	[thread overview]
Message-ID: <4844353.31r3eYUQgx@jernej-laptop> (raw)
In-Reply-To: <20230715112523.2533742-5-contact@jookia.org>

Dne sobota, 15. julij 2023 ob 13:25:22 CEST je Jookia napisal(a):
> From: John Watts <contact@jookia.org>
> 
> The Allwinner D1's CAN controllers have the ACPC and ACPM registers
> moved down. Compensate for this by adding an offset quirk for the
> acceptance registers.
> 
> Signed-off-by: John Watts <contact@jookia.org>

This patch should precede patch 3, so in next patch you add full D1 support.

Best regards,
Jernej

> ---
>  drivers/net/can/sun4i_can.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/can/sun4i_can.c b/drivers/net/can/sun4i_can.c
> index 06f2cf05aaf5..c508a328e38d 100644
> --- a/drivers/net/can/sun4i_can.c
> +++ b/drivers/net/can/sun4i_can.c
> @@ -91,6 +91,8 @@
>  #define SUN4I_REG_BUF12_ADDR	0x0070	/* CAN Tx/Rx Buffer 12 */
>  #define SUN4I_REG_ACPC_ADDR	0x0040	/* CAN Acceptance Code 0 */
>  #define SUN4I_REG_ACPM_ADDR	0x0044	/* CAN Acceptance Mask 0 */
> +#define SUN4I_REG_ACPC_ADDR_D1	0x0028	/* CAN Acceptance Code 0 on the D1 
*/
> +#define SUN4I_REG_ACPM_ADDR_D1	0x002C	/* CAN Acceptance Mask 0 
on the D1
> */ #define SUN4I_REG_RBUF_RBACK_START_ADDR	0x0180	/* CAN transmit buffer
> start */ #define SUN4I_REG_RBUF_RBACK_END_ADDR	0x01b0	/* CAN 
transmit
> buffer end */
> 
> @@ -205,9 +207,11 @@
>   * struct sun4ican_quirks - Differences between SoC variants.
>   *
>   * @has_reset: SoC needs reset deasserted.
> + * @acp_offset: Offset of ACPC and ACPM registers
>   */
>  struct sun4ican_quirks {
>  	bool has_reset;
> +	int acp_offset;
>  };
> 
>  struct sun4ican_priv {
> @@ -216,6 +220,7 @@ struct sun4ican_priv {
>  	struct clk *clk;
>  	struct reset_control *reset;
>  	spinlock_t cmdreg_lock;	/* lock for concurrent cmd register 
writes */
> +	int acp_offset;
>  };
> 
>  static const struct can_bittiming_const sun4ican_bittiming_const = {
> @@ -338,8 +343,8 @@ static int sun4i_can_start(struct net_device *dev)
>  	}
> 
>  	/* set filters - we accept all */
> -	writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR);
> -	writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR);
> +	writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR + priv-
>acp_offset);
> +	writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR + priv-
>acp_offset);
> 
>  	/* clear error counters and error code capture */
>  	writel(0, priv->base + SUN4I_REG_ERRC_ADDR);
> @@ -768,14 +773,17 @@ static const struct ethtool_ops sun4ican_ethtool_ops =
> {
> 
>  static const struct sun4ican_quirks sun4ican_quirks_a10 = {
>  	.has_reset = false,
> +	.acp_offset = 0,
>  };
> 
>  static const struct sun4ican_quirks sun4ican_quirks_r40 = {
>  	.has_reset = true,
> +	.acp_offset = 0,
>  };
> 
>  static const struct sun4ican_quirks sun4ican_quirks_d1 = {
>  	.has_reset = true,
> +	.acp_offset = (SUN4I_REG_ACPC_ADDR_D1 - SUN4I_REG_ACPC_ADDR),
>  };
> 
>  static const struct of_device_id sun4ican_of_match[] = {
> @@ -877,6 +885,7 @@ static int sun4ican_probe(struct platform_device *pdev)
>  	priv->base = addr;
>  	priv->clk = clk;
>  	priv->reset = reset;
> +	priv->acp_offset = quirks->acp_offset;
>  	spin_lock_init(&priv->cmdreg_lock);
> 
>  	platform_set_drvdata(pdev, dev);

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