Re: [PATCH v4 2/4] clocksource/drivers: Add CLINT timer driver

From: Daniel Lezcano <daniel.lezcano@linaro.org>
To: Anup Patel <anup.patel@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Rob Herring <robh+dt@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>
Cc: devicetree@vger.kernel.org,
	Damien Le Moal <damien.lemoal@wdc.com>,
	Emil Renner Berhing <kernel@esmil.dk>,
	Anup Patel <anup@brainfault.org>,
	linux-kernel@vger.kernel.org, Atish Patra <atish.patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH v4 2/4] clocksource/drivers: Add CLINT timer driver
Date: Tue, 21 Jul 2020 13:02:45 +0200	[thread overview]
Message-ID: <63f65ddd-b7c4-b8fd-151c-a77e8c87efed@linaro.org> (raw)
In-Reply-To: <20200717075101.263332-3-anup.patel@wdc.com>

On 17/07/2020 09:50, Anup Patel wrote:
> We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e.
> RISC-V NoMMU kernel).
> 
> The CLINT MMIO device provides three things:
> 1. 64bit free running counter register
> 2. 64bit per-CPU time compare registers
> 3. 32bit per-CPU inter-processor interrupt registers
> 
> Unlike other timer devices, CLINT provides IPI registers along with
> timer registers. To use CLINT IPI registers, the CLINT timer driver
> provides IPI related callbacks to arch/riscv.
> 
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> Tested-by: Emil Renner Berhing <kernel@esmil.dk>
> ---
>  drivers/clocksource/Kconfig       |   9 ++
>  drivers/clocksource/Makefile      |   1 +
>  drivers/clocksource/timer-clint.c | 231 ++++++++++++++++++++++++++++++
>  include/linux/cpuhotplug.h        |   1 +
>  4 files changed, 242 insertions(+)
>  create mode 100644 drivers/clocksource/timer-clint.c
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 91418381fcd4..e1ce0d510a03 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -658,6 +658,15 @@ config RISCV_TIMER
>  	  is accessed via both the SBI and the rdcycle instruction.  This is
>  	  required for all RISC-V systems.
>  
> +config CLINT_TIMER
> +	bool "Timer for the RISC-V platform"
> +	depends on GENERIC_SCHED_CLOCK && RISCV_M_MODE
> +	select TIMER_PROBE
> +	select TIMER_OF
> +	help
> +	  This option enables the CLINT timer for RISC-V systems. The CLINT
> +	  driver is usually used for NoMMU RISC-V systems.

V3 has a comment about fixing the Kconfig option.

[ ... ]

> +{
> +	bool *registered = per_cpu_ptr(&clint_clock_event_registered, cpu);
> +	struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu);
> +
> +	if (!(*registered)) {
> +		ce->cpumask = cpumask_of(cpu);
> +		clockevents_config_and_register(ce, clint_timer_freq, 200,
> +						 ULONG_MAX);
> +		*registered = true;
> +	}

I was unsure about the clockevents_config_and_register() multiple calls
when doing the comment. It seems like it is fine to call it several
times and that is done in several places like riscv or arch_arm_timer.

It is probably safe to drop the 'registered' code here, sorry for the
confusion.

> +	enable_percpu_irq(clint_timer_irq,
> +			  irq_get_trigger_type(clint_timer_irq));
> +	return 0;
> +}
> +

[ ... ]

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