From: Anup Patel <anup@brainfault.org>
To: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: devicetree@vger.kernel.org,
Damien Le Moal <damien.lemoal@wdc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Emil Renner Berhing <kernel@esmil.dk>,
Anup Patel <anup.patel@wdc.com>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>, Atish Patra <atish.patra@wdc.com>,
Rob Herring <robh+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Thomas Gleixner <tglx@linutronix.de>,
linux-riscv <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v4 2/4] clocksource/drivers: Add CLINT timer driver
Date: Wed, 22 Jul 2020 09:06:24 +0530 [thread overview]
Message-ID: <CAAhSdy0fmtaExqEx-7qW6Bpzu23d6A4OnUY7b785VJW_5a6rdA@mail.gmail.com> (raw)
In-Reply-To: <107e3ef3-9f61-05d1-7a91-95d0dc7ea7b8@linaro.org>
On Tue, Jul 21, 2020 at 5:45 PM Daniel Lezcano
<daniel.lezcano@linaro.org> wrote:
>
> On 21/07/2020 13:49, Anup Patel wrote:
> > On Tue, Jul 21, 2020 at 4:32 PM Daniel Lezcano
> > <daniel.lezcano@linaro.org> wrote:
> >>
> >> On 17/07/2020 09:50, Anup Patel wrote:
> >>> We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e.
> >>> RISC-V NoMMU kernel).
> >>>
> >>> The CLINT MMIO device provides three things:
> >>> 1. 64bit free running counter register
> >>> 2. 64bit per-CPU time compare registers
> >>> 3. 32bit per-CPU inter-processor interrupt registers
> >>>
> >>> Unlike other timer devices, CLINT provides IPI registers along with
> >>> timer registers. To use CLINT IPI registers, the CLINT timer driver
> >>> provides IPI related callbacks to arch/riscv.
> >>>
> >>> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> >>> Tested-by: Emil Renner Berhing <kernel@esmil.dk>
> >>> ---
> >>> drivers/clocksource/Kconfig | 9 ++
> >>> drivers/clocksource/Makefile | 1 +
> >>> drivers/clocksource/timer-clint.c | 231 ++++++++++++++++++++++++++++++
> >>> include/linux/cpuhotplug.h | 1 +
> >>> 4 files changed, 242 insertions(+)
> >>> create mode 100644 drivers/clocksource/timer-clint.c
> >>>
> >>> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> >>> index 91418381fcd4..e1ce0d510a03 100644
> >>> --- a/drivers/clocksource/Kconfig
> >>> +++ b/drivers/clocksource/Kconfig
> >>> @@ -658,6 +658,15 @@ config RISCV_TIMER
> >>> is accessed via both the SBI and the rdcycle instruction. This is
> >>> required for all RISC-V systems.
> >>>
> >>> +config CLINT_TIMER
> >>> + bool "Timer for the RISC-V platform"
> >>> + depends on GENERIC_SCHED_CLOCK && RISCV_M_MODE
> >>> + select TIMER_PROBE
> >>> + select TIMER_OF
> >>> + help
> >>> + This option enables the CLINT timer for RISC-V systems. The CLINT
> >>> + driver is usually used for NoMMU RISC-V systems.
> >>
> >> V3 has a comment about fixing the Kconfig option.
> >
> > I have removed "default y" from the Kconfig option as-per your suggestions.
> >
> > I looked at other Timer Kconfig options. Most of them have menuconfig name.
> > Also, we can certainly have different timer MMIO timer drivers in future. Do
> > you still insist on making this kconfig option totally silent ??
>
> Yes, and there is an effort to change the entries to be silent as much
> as possible.
>
> Just add:
>
> bool "Timer for the RISC-V platform" if COMPILE_TEST
Okay, I will update.
>
> and remove the RISCV_M_MODE dependency.
CLINT driver depends on RISC-V specific symbols from asm/smp.h
so we should at least have "depends on RISCV" so that compile
test does not fail.
Agree ??
>
> Or alternatively:
>
> replace the RISCV_M_MODE dependency with COMPILE_TEST
>
> The goal is to be able to compile the driver on different platforms for
> compilation test covering.
Please see the above comment.
>
> Then when more mmio drivers will added we will figure out.
>
> >> [ ... ]
> >>
> >>> +{
> >>> + bool *registered = per_cpu_ptr(&clint_clock_event_registered, cpu);
> >>> + struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu);
> >>> +
> >>> + if (!(*registered)) {
> >>> + ce->cpumask = cpumask_of(cpu);
> >>> + clockevents_config_and_register(ce, clint_timer_freq, 200,
> >>> + ULONG_MAX);
> >>> + *registered = true;
> >>> + }
> >>
> >>
> >> I was unsure about the clockevents_config_and_register() multiple calls
> >> when doing the comment. It seems like it is fine to call it several
> >> times and that is done in several places like riscv or arch_arm_timer.
> >>
> >> It is probably safe to drop the 'registered' code here, sorry for the
> >> confusion.
> >
> > Okay, will revert these changes.
> >
> >>
> >>> + enable_percpu_irq(clint_timer_irq,
> >>> + irq_get_trigger_type(clint_timer_irq));
> >>> + return 0;
> >>> +}
> >>> +
> >>
> >> [ ... ]
> >>
> >>
> >> --
> >> <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
> >>
> >> Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
> >> <http://twitter.com/#!/linaroorg> Twitter |
> >> <http://www.linaro.org/linaro-blog/> Blog
> >
> > Regards,
> > Anup
> >
>
>
> --
> <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>
> Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog
Regards,
Anup
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next prev parent reply other threads:[~2020-07-22 3:36 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-17 7:50 [PATCH v4 0/4] Dedicated CLINT timer driver Anup Patel
2020-07-17 7:50 ` [PATCH v4 1/4] RISC-V: Add mechanism to provide custom IPI operations Anup Patel
2020-07-21 0:46 ` Atish Patra
2020-07-17 7:50 ` [PATCH v4 2/4] clocksource/drivers: Add CLINT timer driver Anup Patel
2020-07-21 1:11 ` Atish Patra
2020-07-21 11:43 ` Anup Patel
2020-07-21 19:39 ` Atish Patra
2020-07-21 11:02 ` Daniel Lezcano
2020-07-21 11:49 ` Anup Patel
2020-07-21 12:15 ` Daniel Lezcano
2020-07-22 3:36 ` Anup Patel [this message]
2020-07-17 7:51 ` [PATCH v4 3/4] RISC-V: Remove CLINT related code from timer and arch Anup Patel
2020-07-17 7:51 ` [PATCH v4 4/4] dt-bindings: timer: Add CLINT bindings Anup Patel
2020-07-21 1:15 ` Atish Patra
2020-07-21 11:39 ` Anup Patel
2020-07-21 12:17 ` Sean Anderson
2020-07-22 3:55 ` Anup Patel
2020-07-26 18:37 ` Palmer Dabbelt
2020-07-27 11:47 ` Sean Anderson
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