From: Anup Patel <anup@brainfault.org>
To: Atish Patra <atishp@atishpatra.org>
Cc: devicetree@vger.kernel.org,
Damien Le Moal <damien.lemoal@wdc.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Emil Renner Berhing <kernel@esmil.dk>,
Anup Patel <anup.patel@wdc.com>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>, Atish Patra <atish.patra@wdc.com>,
Rob Herring <robh+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Thomas Gleixner <tglx@linutronix.de>,
linux-riscv <linux-riscv@lists.infradead.org>,
Albert Ou <aou@eecs.berkeley.edu>
Subject: Re: [PATCH v4 4/4] dt-bindings: timer: Add CLINT bindings
Date: Tue, 21 Jul 2020 17:09:41 +0530 [thread overview]
Message-ID: <CAAhSdy1cbKA9iwBPYMX5xaYFe_BxnB2Sm_ftHPPDq+96SeKbnA@mail.gmail.com> (raw)
In-Reply-To: <CAOnJCULcffij3-d-TsQixj5TZdatBdUcC-y73L=W-+5h41ytKQ@mail.gmail.com>
On Tue, Jul 21, 2020 at 6:45 AM Atish Patra <atishp@atishpatra.org> wrote:
>
> On Fri, Jul 17, 2020 at 12:52 AM Anup Patel <anup.patel@wdc.com> wrote:
> >
> > We add DT bindings documentation for CLINT device.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> > Tested-by: Emil Renner Berhing <kernel@esmil.dk>
> > ---
> > .../bindings/timer/sifive,clint.yaml | 58 +++++++++++++++++++
> > 1 file changed, 58 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > new file mode 100644
> > index 000000000000..8ad115611860
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > @@ -0,0 +1,58 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SiFive Core Local Interruptor
> > +
> > +maintainers:
> > + - Palmer Dabbelt <palmer@dabbelt.com>
> > + - Anup Patel <anup.patel@wdc.com>
> > +
> > +description:
> > + SiFive (and other RISC-V) SOCs include an implementation of the SiFive
> > + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
> > + interrupts. It directly connects to the timer and inter-processor interrupt
> > + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
> > + interrupt controller is the parent interrupt controller for CLINT device.
> > + The clock frequency of CLINT is specified via "timebase-frequency" DT
> > + property of "/cpus" DT node. The "timebase-frequency" DT property is
> > + described in Documentation/devicetree/bindings/riscv/cpus.yaml
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: sifive,clint0
> > + - const: sifive,fu540-c000-clint
> > +
> > + description:
> > + Should be "sifive,<chip>-clint" and "sifive,clint<version>".
> > + Supported compatible strings are -
> > + "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
> > + onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive
> > + CLINT v0 IP block with no chip integration tweaks.
> > + Please refer to sifive-blocks-ip-versioning.txt for details
> > +
>
> As the DT binding suggests that the clint device should be named as "sifive,**",
> I think we should change the DT property in kendryte dts as well.
Okay, I will do it as a separate patch.
>
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts-extended:
> > + minItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts-extended
> > +
> > +examples:
> > + - |
> > + clint@2000000 {
> > + compatible = "sifive,clint0", "sifive,fu540-c000-clint";
> > + interrupts-extended = <&cpu1intc 3 &cpu1intc 7
> > + &cpu2intc 3 &cpu2intc 7
> > + &cpu3intc 3 &cpu3intc 7
> > + &cpu4intc 3 &cpu4intc 7>;
> > + reg = <0x2000000 0x4000000>;
> > + };
> > +...
> > --
> > 2.25.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
>
> Otherwise,
>
> Reviewed-by: Atish Patra <atish.patra@wdc.com>
>
> --
> Regards,
> Atish
Regards,
Anup
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next prev parent reply other threads:[~2020-07-21 11:40 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-17 7:50 [PATCH v4 0/4] Dedicated CLINT timer driver Anup Patel
2020-07-17 7:50 ` [PATCH v4 1/4] RISC-V: Add mechanism to provide custom IPI operations Anup Patel
2020-07-21 0:46 ` Atish Patra
2020-07-17 7:50 ` [PATCH v4 2/4] clocksource/drivers: Add CLINT timer driver Anup Patel
2020-07-21 1:11 ` Atish Patra
2020-07-21 11:43 ` Anup Patel
2020-07-21 19:39 ` Atish Patra
2020-07-21 11:02 ` Daniel Lezcano
2020-07-21 11:49 ` Anup Patel
2020-07-21 12:15 ` Daniel Lezcano
2020-07-22 3:36 ` Anup Patel
2020-07-17 7:51 ` [PATCH v4 3/4] RISC-V: Remove CLINT related code from timer and arch Anup Patel
2020-07-17 7:51 ` [PATCH v4 4/4] dt-bindings: timer: Add CLINT bindings Anup Patel
2020-07-21 1:15 ` Atish Patra
2020-07-21 11:39 ` Anup Patel [this message]
2020-07-21 12:17 ` Sean Anderson
2020-07-22 3:55 ` Anup Patel
2020-07-26 18:37 ` Palmer Dabbelt
2020-07-27 11:47 ` Sean Anderson
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