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From: paul.walmsley@sifive.com (Paul Walmsley)
To: linux-riscv@lists.infradead.org
Subject: [RFC 1/4] pwm: sifive: Add DT documentation for SiFive PWM Controller.
Date: Tue, 16 Oct 2018 10:31:42 -0700	[thread overview]
Message-ID: <6e108e3c-15c1-b13b-ac3e-60c5eb209c7b@sifive.com> (raw)
In-Reply-To: <20181016110142.GC8852@ulmo>


On 10/16/18 4:01 AM, Thierry Reding wrote:
> On Mon, Oct 15, 2018 at 03:57:35PM -0700, Atish Patra wrote:
>> On 10/10/18 6:49 AM, Thierry Reding wrote:
>>> On Tue, Oct 09, 2018 at 11:51:22AM -0700, Atish Patra wrote:
>>>> +Required properties:
>>>> +- compatible: should be one of
>>>> +	"sifive,fu540-c000-pwm0","sifive,pwm0".
>>> What's the '0' in here? A version number?
>>>
>> I think yes. Since fu540 is the first Linux capable RISC-V core, SiFive Guys
>> decided mark it as version 0.
>>
>> @Wesly: Please correct me if I am wrong.
> It seems fairly superfluous to me to have a version number in additon to
> the fu540-c000, which already seems to be the core plus some sort of
> part number. Do you really expect there to be any changes in the SoC
> that would require a different compatible string at this point? If the
> SoC has taped out, how will you ever get a different version of the PWM
> IP in it?
>
> I would expect any improvements or changes to the PWM IP to show up in a
> different SoC generation, at which point it would be something like
> "sifive,fu640-c000" maybe, or perhaps "sifive,fu540-d000", or whatever
> the numbering is.


The "0" suffix refers to a revision number for the underlying PWM IP block.

It's certainly important to keep that version number on the 
"sifive,pwm0" compatible string that doesn't have the chip name 
associated with it.

As to whether there could ever be a FU540-C000 part with different IP 
block versions on it: FU540-C000 is ultimately a marketing name.? While 
theoretically we shouldn't have another "FU540-C000" chip with different 
peripheral IP block versions on it, I don't think any engineer can 
guarantee that it won't happen.


- Paul

WARNING: multiple messages have this Message-ID (diff)
From: Paul Walmsley <paul.walmsley@sifive.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Atish Patra <atish.patra@wdc.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: mark.rutland@arm.com, linux-pwm@vger.kernel.org,
	devicetree@vger.kernel.org, Wesley Terpstra <wesley@sifive.com>,
	linus.walleij@linaro.org, palmer@sifive.com,
	linux-kernel@vger.kernel.org, hch@infradead.org,
	linux-gpio@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [RFC 1/4] pwm: sifive: Add DT documentation for SiFive PWM Controller.
Date: Tue, 16 Oct 2018 10:31:42 -0700	[thread overview]
Message-ID: <6e108e3c-15c1-b13b-ac3e-60c5eb209c7b@sifive.com> (raw)
Message-ID: <20181016173142.uMZXHmNZI2RoWQbYnGSElUE0TiOuzWy9L3ubpLgwErU@z> (raw)
In-Reply-To: <20181016110142.GC8852@ulmo>


On 10/16/18 4:01 AM, Thierry Reding wrote:
> On Mon, Oct 15, 2018 at 03:57:35PM -0700, Atish Patra wrote:
>> On 10/10/18 6:49 AM, Thierry Reding wrote:
>>> On Tue, Oct 09, 2018 at 11:51:22AM -0700, Atish Patra wrote:
>>>> +Required properties:
>>>> +- compatible: should be one of
>>>> +	"sifive,fu540-c000-pwm0","sifive,pwm0".
>>> What's the '0' in here? A version number?
>>>
>> I think yes. Since fu540 is the first Linux capable RISC-V core, SiFive Guys
>> decided mark it as version 0.
>>
>> @Wesly: Please correct me if I am wrong.
> It seems fairly superfluous to me to have a version number in additon to
> the fu540-c000, which already seems to be the core plus some sort of
> part number. Do you really expect there to be any changes in the SoC
> that would require a different compatible string at this point? If the
> SoC has taped out, how will you ever get a different version of the PWM
> IP in it?
>
> I would expect any improvements or changes to the PWM IP to show up in a
> different SoC generation, at which point it would be something like
> "sifive,fu640-c000" maybe, or perhaps "sifive,fu540-d000", or whatever
> the numbering is.


The "0" suffix refers to a revision number for the underlying PWM IP block.

It's certainly important to keep that version number on the 
"sifive,pwm0" compatible string that doesn't have the chip name 
associated with it.

As to whether there could ever be a FU540-C000 part with different IP 
block versions on it: FU540-C000 is ultimately a marketing name.  While 
theoretically we shouldn't have another "FU540-C000" chip with different 
peripheral IP block versions on it, I don't think any engineer can 
guarantee that it won't happen.


- Paul


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  parent reply	other threads:[~2018-10-16 17:31 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-09 18:51 [RFC 0/4] GPIO & PWM support for HiFive Unleashed Atish Patra
2018-10-09 18:51 ` Atish Patra
2018-10-09 18:51 ` [RFC 1/4] pwm: sifive: Add DT documentation for SiFive PWM Controller Atish Patra
2018-10-09 18:51   ` Atish Patra
2018-10-10 13:49   ` Thierry Reding
2018-10-10 13:49     ` Thierry Reding
2018-10-15 22:57     ` Atish Patra
2018-10-15 22:57       ` Atish Patra
2018-10-15 23:19       ` Wesley Terpstra
2018-10-15 23:19         ` Wesley Terpstra
2018-10-16 11:13         ` Thierry Reding
2018-10-16 11:13           ` Thierry Reding
2018-10-16 11:01       ` Thierry Reding
2018-10-16 11:01         ` Thierry Reding
2018-10-16 17:31         ` Paul Walmsley [this message]
2018-10-16 17:31           ` Paul Walmsley
2018-10-16 22:04           ` Thierry Reding
2018-10-16 22:04             ` Thierry Reding
2018-10-16 22:20             ` Atish Patra
2018-10-16 22:20               ` Atish Patra
2018-10-17 15:58               ` Rob Herring
2018-10-17 15:58                 ` Rob Herring
2018-10-17 21:45                 ` Atish Patra
2018-10-17 21:45                   ` Atish Patra
2018-11-10  5:38             ` Paul Walmsley
2018-11-10  5:38               ` Paul Walmsley
2018-10-10 13:51   ` Thierry Reding
2018-10-10 13:51     ` Thierry Reding
2018-10-15 22:45     ` Atish Patra
2018-10-15 22:45       ` Atish Patra
2018-10-16 10:51       ` Thierry Reding
2018-10-16 10:51         ` Thierry Reding
2018-10-16 22:42         ` Atish Patra
2018-10-16 22:42           ` Atish Patra
2018-10-09 18:51 ` [RFC 2/4] pwm: sifive: Add a driver for SiFive SoC PWM Atish Patra
2018-10-09 18:51   ` Atish Patra
2018-10-10 13:11   ` Christoph Hellwig
2018-10-10 13:11     ` Christoph Hellwig
2018-10-10 13:44     ` Thierry Reding
2018-10-10 13:44       ` Thierry Reding
2018-10-16  6:28     ` Atish Patra
2018-10-16  6:28       ` Atish Patra
2018-10-10 14:13   ` Thierry Reding
2018-10-10 14:13     ` Thierry Reding
2018-10-16  6:24     ` Atish Patra
2018-10-16  6:24       ` Atish Patra
2018-10-09 18:51 ` [RFC 3/4] gpio: sifive: Add DT documentation for SiFive GPIO Atish Patra
2018-10-09 18:51   ` Atish Patra
2018-10-09 18:51 ` [RFC 4/4] gpio: sifive: Add GPIO driver for SiFive SoCs Atish Patra
2018-10-09 18:51   ` Atish Patra
2018-10-10 12:35   ` Linus Walleij
2018-10-10 12:35     ` Linus Walleij
2018-10-17  1:01     ` Atish Patra
2018-10-17  1:01       ` Atish Patra
2019-09-18  7:32       ` Bin Meng
2018-10-10 13:01   ` Andreas Schwab
2018-10-10 13:01     ` Andreas Schwab
2018-10-10 13:12     ` Christoph Hellwig
2018-10-10 13:12       ` Christoph Hellwig
2018-10-10 13:28       ` Andreas Schwab
2018-10-10 13:28         ` Andreas Schwab

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