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From: Anup Patel <anup@brainfault.org>
To: Gary Guo <gary@garyguo.net>
Cc: "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v3 4/4] RISC-V: Allow booting kernel from any 4KB aligned address
Date: Tue, 26 Mar 2019 15:13:21 +0530	[thread overview]
Message-ID: <CAAhSdy00nORndLg3mV9aodefUrLKd90fxV=Q70hH7DfLaz3w4Q@mail.gmail.com> (raw)
In-Reply-To: <e12f6bc2-c993-1dbf-37b8-9562870806f1@garyguo.net>

On Mon, Mar 25, 2019 at 11:06 PM Gary Guo <gary@garyguo.net> wrote:
>
>
>
> On 25/03/2019 16:16, Anup Patel wrote:
>  > 1G mappings will give better performance compared 2M mappings.
>  >
>  > This will be very useful for performance hungry system with lot of RAM.
>  >
>  > This patch selects 1G or 2M mapping at runtime based on load address
>  > alignment.
>  >
>  > Regards,
>  > Anup
>  >
>
> Not always the case. In general, if set-associative or direct mapped
> TLBs are used, then either
> 1) separate TLBs are used for different granularities. Usually very few
> entries will be there for 1G mappings. E.g. Intel CPU's D-TLB has a
> separate array of 1G page TLB which is only 4 entries.
> 2) a smaller-granularity PTE is "faked" by page walker and inserted into
> the TLB. E.g. Intel CPU's I-TLB can't hold 1G entry at all.
>
> In either cases the performance won't differ by much. In fact if 1) is
> used there are cases where performance can be negatively impacted by
> using larger pages.

The above is just one way of designing/organizing TLBs in HW. It is also
possible to have a unified-TLB (like ARM/ARM64 world SOCs) supporting
multiple page sizes in each TLB entry.

Depending on the TLB micro-architecture the performance gains will vary.

Irrespective to TLB design, there will always be some gains because
after all we are saving page-table walks by creating bigger mappings.

In case of virtualization with nested page tables, the savings can be
even bigger because it's a two dimensional page table walk. For example,
let's assume M = "number of levels in guest page table" and N = "number
of levels in hypervisor page table". Now, number descriptor access would
be "MxN + M + N" so if we are able to reduce M or N or both then it will
save lot of memory accesses.

Regards,
Anup

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  reply	other threads:[~2019-03-26  9:43 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-25  9:22 [PATCH v3 0/4] Boot RISC-V kernel from any 4KB aligned address Anup Patel
2019-03-25  9:23 ` [PATCH v3 1/4] RISC-V: Add separate defconfig for 32bit systems Anup Patel
2019-03-25  9:23 ` [PATCH v3 2/4] RISC-V: Fix memory reservation in setup_bootmem() Anup Patel
2019-03-25 11:38   ` Christoph Hellwig
2019-03-25 16:13   ` Mike Rapoport
2019-04-24 21:06   ` Palmer Dabbelt
2019-03-25  9:23 ` [PATCH v3 3/4] RISC-V: Remove redundant trampoline page table Anup Patel
2019-03-25 11:38   ` Christoph Hellwig
2019-03-25  9:23 ` [PATCH v3 4/4] RISC-V: Allow booting kernel from any 4KB aligned address Anup Patel
2019-03-25 11:39   ` Christoph Hellwig
2019-03-25 12:42     ` Anup Patel
2019-03-25 14:55       ` Christoph Hellwig
2019-03-25 12:48     ` Anup Patel
2019-03-25 14:59       ` Christoph Hellwig
2019-03-25 16:16         ` Anup Patel
2019-03-25 17:35           ` Gary Guo
2019-03-26  9:43             ` Anup Patel [this message]
2019-03-27  7:54           ` Christoph Hellwig
2019-03-28  7:55             ` Mike Rapoport
2019-03-28  9:52               ` Anup Patel
2019-03-28 10:24                 ` Anup Patel
2019-03-28 15:35 Anthony Coulter

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