From: Anup Patel <anup@brainfault.org>
To: Zong Li <zong.li@sifive.com>
Cc: linux-riscv <linux-riscv@lists.infradead.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>
Subject: Re: [RFC PATCH 1/6] dt-bindings: riscv: Add YAML documentation for PMU
Date: Mon, 29 Jun 2020 09:39:24 +0530 [thread overview]
Message-ID: <CAAhSdy3VBUTMg_b2tO12cTYuvHYtH=4dj9-qT-at35Whf3w_7w@mail.gmail.com> (raw)
In-Reply-To: <3de3a480517d167a3faae086aa8ab0c0c7141d99.1593397455.git.zong.li@sifive.com>
On Mon, Jun 29, 2020 at 8:49 AM Zong Li <zong.li@sifive.com> wrote:
>
> Add device tree bindings for performance monitor unit. And it passes the
> dt_binding_check verification.
>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
> .../devicetree/bindings/riscv/pmu.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/pmu.yaml
>
> diff --git a/Documentation/devicetree/bindings/riscv/pmu.yaml b/Documentation/devicetree/bindings/riscv/pmu.yaml
> new file mode 100644
> index 000000000000..f55ccbc6c685
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/pmu.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/pmu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V Performance Monitor Units
> +
> +maintainers:
> + - Zong Li <zong.li@sifive.com>
> + - Paul Walmsley <paul.walmsley@sifive.com>
> + - Palmer Dabbelt <palmer@dabbelt.com>
> +
> +properties:
> + compatible:
> + items:
> + - const: riscv,pmu
> +
> + riscv,width-base-cntr:
> + description: The width of cycle and instret CSRs.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + riscv,width-event-cntr:
> + description: The width of hpmcounter CSRs.
> + $ref: /schemas/types.yaml#/definitions/uint32
The terms "base" and "event" is confusing because
we only have counters with no interrupt associated with it.
The RISC-V spec defines 3 counters and rest are all
implementation specific counters.
I suggest using the terms "spec counters" and "impl counters"
instead of "base counters" and "event counters".
Further, "riscv,width" properties are redundant because
RISC-V spec clearly tells that counters are 64bit for both
RV32 and RV64.
> +
> + riscv,n-event-cntr:
> + description: The number of hpmcounter CSRs.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + riscv,hw-event-map:
> + description: The mapping of generic hardware events. Default is no mapping.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> +
> + riscv,hw-cache-event-map:
> + description: The mapping of generic hardware cache events.
> + Default is no mapping.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> +
> +required:
> + - compatible
> + - riscv,width-base-cntr
> + - riscv,width-event-cntr
> + - riscv,n-event-cntr
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pmu {
> + compatible = "riscv,pmu";
> + riscv,width-base-cntr = <64>;
> + riscv,width-event-cntr = <40>;
> + riscv,n-event-cntr = <2>;
> + riscv,hw-event-map = <0x0 0x0 0x1 0x1 0x3 0x0202 0x4 0x4000>;
> + riscv,hw-cache-event-map = <0x010201 0x0102 0x010204 0x0802>;
> + };
> +
> +...
> --
> 2.27.0
>
Regards,
Anup
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next prev parent reply other threads:[~2020-06-29 4:09 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-29 3:19 [RFC PATCH 0/6] Support raw event and DT for perf on RISC-V Zong Li
2020-06-29 3:19 ` [RFC PATCH 1/6] dt-bindings: riscv: Add YAML documentation for PMU Zong Li
2020-06-29 4:09 ` Anup Patel [this message]
2020-06-29 4:28 ` Zong Li
2020-06-29 4:37 ` Anup Patel
2020-06-29 6:35 ` Zong Li
2020-06-29 8:31 ` Anup Patel
2020-07-01 3:22 ` Zong Li
2020-06-29 3:19 ` [RFC PATCH 2/6] riscv: dts: sifive: Add DT support " Zong Li
2020-06-29 3:19 ` [RFC PATCH 3/6] riscv: add definition of hpmcounter CSRs Zong Li
2020-06-29 3:19 ` [RFC PATCH 4/6] riscv: perf: Add raw event support Zong Li
2020-06-29 4:17 ` Anup Patel
2020-06-29 4:35 ` Zong Li
2020-06-29 4:40 ` Anup Patel
2020-06-29 3:19 ` [RFC PATCH 5/6] riscv: perf: introduce DT mechanism Zong Li
2020-06-29 4:36 ` Anup Patel
2020-06-29 6:26 ` Zong Li
2020-06-29 3:19 ` [RFC PATCH 6/6] riscv: remove PMU menu of Kconfig Zong Li
2020-06-29 4:52 ` [RFC PATCH 0/6] Support raw event and DT for perf on RISC-V Anup Patel
2020-06-29 5:52 ` Zong Li
2020-06-29 8:27 ` Anup Patel
2020-06-29 12:53 ` Zong Li
2020-06-29 13:23 ` Anup Patel
2020-06-30 6:37 ` Zong Li
2020-06-30 7:39 ` Anup Patel
2020-06-30 8:04 ` Zong Li
2020-06-30 10:18 ` Anup Patel
2020-06-30 11:38 ` Anup Patel
2020-06-30 18:57 ` Atish Patra
2020-07-01 2:14 ` Zong Li
2020-07-01 11:43 ` Anup Patel
2020-07-01 2:11 ` Zong Li
2020-07-01 1:55 ` Zong Li
2020-07-01 0:51 ` Alan Kao
2020-07-01 1:02 ` Atish Patra
2020-07-01 2:45 ` Alan Kao
2020-07-01 3:15 ` Zong Li
2020-07-01 4:13 ` Anup Patel
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