Re: per-cpu thoughts

[Paul Walmsley <paul.walmsley@sifive.com>]

On Thu, 28 Feb 2019, Christopher Lameter wrote:

> On Thu, 28 Feb 2019, Paul Walmsley wrote:
> 
> > This is the AMO-based sequence that Palmer wrote in his E-mail:
> >
> >    li t0, 1
> >    la t1, counter
> >    amoadd.w zero, t0, 0(t1)
> >
> > The RMW takes place in the amoadd, and executes atomically from the point
> > of view of all cores in the cache coherency domain.
> >
> > Or am I misunderstanding you?
> 
> Yes Palmers example missed having the address of the per cpu space
> somewhere in a register (lets call it "tPerCpu"). Then you can do
> 
> 	li t0, 1
> 	la t1, offset of counter in percpu area
> 	amoadd.w zero,t0, 0(t1 + tPerCpu)
> 
> But as far as we know we do not have an amoadd that can do this. If you
> add the percpu space address earlier:
> 
> 	li t0, 1
> 	la t1, offset of counter in percpu area
> 	add t1, t1, tPerCPu
> 	amoadd.w zero, t0, 0(t1)
> 
> then you have the dnager of the amoadd being done on the wrong per cpu
> address because the scheduler may move the execution thread to a different
> processor betweeen the "add" and the amoadd.
> 
> If you do it without the amoadd with just lc/sc then there more potential
> issues exist.

Thanks for explaining that.

Is the offset of the counter from the start of my per-cpu area guaranteed 
to be the same across all CPUs?  If so, wouldn't there simply be a 
potential performance risk if preemption was left enabled, rather than a 
correctness risk?


- Paul

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