Re: [PATCH 0/6] pwm: sun4i: only wait 2 cycles prior to disabling

[Pascal Roeleven <dev@pascalroeleven.nl>]

On 2021-05-31 22:01, Emil Lenngren wrote:
> You could look at the devmem source code, and in C write a script that
> writes to pwm register to disable the pwm, insert a usleep, then
> disable the gating. This can be done for various sleep values, then
> retrying with same sleep value multiple times. Assuming the overhead
> is low (you can check the overhead by checking the current timestamp
> at the beginning and at the end of the program, take the diff and then
> subtract the sleep time), you will get one range where it never works,
> one range where it works sometimes, and one range where it always
> works. The uncertain range's condition for succeeding will depend on
> when in the cycle you run the code.
> Assuming we believe 3 cycles are enough on A10 and prescaler is 72000,
> the thresholds for these ranges are 0-6 ms, 6-9 ms and 9+ ms.

Thank you I will give this a shot if there is still an uncertainty about
the cycles in the end. I performed my tests with a Busybox rootfs, so I
assumed the overhead was low as well.

> About "being stuck", I'm not sure exactly what you mean but it's
> expected that writes to the period register won't be visible (if you
> read it after a write) when the clock gating is disabled. Three full
> cycles (with the gating is on) must take place before the change is
> visible (i.e. need to wait four cycles to be sure). At least on >=A13.
> I documented that here:
> https://linux-sunxi.org/PWM_Controller_Register_Guide.

By being stuck, I mean being in an state from which it can't recover.
The controller will keep outputting seemingly the same signal regardless
what you write to the period register. You can read the values back, but
they aren't effecting the output anymore. No matter in what order or
with what delay I try to re-enable and disable the gate or enable bit,
it'll keep outputting the same signal until you reset the device.