From: Daniel Drake <drake@endlessm.com>
To: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
Linux PCI <linux-pci@vger.kernel.org>,
"Wysocki, Rafael J" <rafael.j.wysocki@intel.com>,
Linux Upstreaming Team <linux@endlessm.com>,
Linux PM <linux-pm@vger.kernel.org>,
Linux USB Mailing List <linux-usb@vger.kernel.org>,
Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: Re: [PATCH] PCI: increase D3 delay for AMD Ryzen5/7 XHCI controllers
Date: Wed, 16 Oct 2019 14:14:19 +0800 [thread overview]
Message-ID: <CAD8Lp46BJvCo4c3c2XTrbPyF3k8p0QG24WbsWQ2Sc=7ikcyC8w@mail.gmail.com> (raw)
In-Reply-To: <CAJZ5v0jCh87azmBuhj1T_M+OV8tu7v7Y7WV_zaf56+fxhXU3KQ@mail.gmail.com>
On Wed, Oct 16, 2019 at 1:52 AM Rafael J. Wysocki <rafael@kernel.org> wrote:
> On Tue, Oct 15, 2019 at 7:31 AM Daniel Drake <drake@endlessm.com> wrote:
> > It's actually coming out of D3cold here, however what happens right
> > before this is that __pci_start_power_transition() calls
> > pci_platform_power_transition(D0) to leave D3cold state, then
> > pci_update_current_state() reads PMCSR and updates dev->current_state
> > to D3hot.
>
> Which pci_update_current_state() do you mean, exactly?
>
> Note that pci_platform_power_transition() itself contains one, which
> triggers after a successful change of the ACPI power state of the
> device (which should be the case here).
That's the one I mean.
pci_pm_default_resume_early
- pci_power_up
-- __pci_start_power_transition
--- pci_platform_power_transition
---- pci_update_current_state(D0)
At this point, PMCSR is read and dev->current_status is set to D3 accordingly.
Then, continuing in pci_power_up(), pci_raw_set_power_state(D0) is
called and the extra delay is needed there after writing PMCSR to
transition to D0.
I didn't go further along the call trace because at that point the
problem has already been triggered.
> That I agree with and the platform firmware doesn't compensate for
> that (which it could do, arguably).
I tried to get official AMD support on this but their response was
that they don't have available resources to dedicate to Linux support.
Without guidance from AMD I don't think there's any chance of a
firmware change from the platform vendor.
I think we just have to figure out how to work with it. It seems that
Windows 10 delays longer or uses some other scheme. Another
alternative that I just tried is retrying the PMCSR write & readback
if it didn't complete the transition on the first try. That works
fine, let me know if it's preferred to implement something along those
lines as a more generic workaround.
Daniel
next prev parent reply other threads:[~2019-10-16 6:14 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-14 6:13 [PATCH] PCI: increase D3 delay for AMD Ryzen5/7 XHCI controllers Daniel Drake
2019-10-14 15:43 ` Bjorn Helgaas
2019-10-15 5:31 ` Daniel Drake
2019-10-15 17:52 ` Rafael J. Wysocki
2019-10-16 6:14 ` Daniel Drake [this message]
2019-10-21 11:33 ` Mika Westerberg
2019-10-22 2:40 ` Daniel Drake
2019-10-22 9:33 ` Mika Westerberg
2019-10-23 22:40 ` Bjorn Helgaas
2019-10-24 3:28 ` Daniel Drake
2019-10-24 17:00 ` Bjorn Helgaas
2019-10-25 7:11 ` Daniel Drake
2019-10-25 16:28 ` Bjorn Helgaas
2019-10-28 6:32 ` Daniel Drake
2019-11-18 8:52 ` Daniel Drake
2019-11-20 0:28 ` Bjorn Helgaas
2019-11-21 18:15 ` Bjorn Helgaas
2019-11-22 3:00 ` Daniel Drake
2019-11-22 11:15 ` Rafael J. Wysocki
2019-11-25 3:45 ` Daniel Drake
2019-11-25 13:37 ` Rafael J. Wysocki
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