From: "Rafael J. Wysocki" <rafael@kernel.org>
To: Daniel Drake <drake@endlessm.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
Linux PCI <linux-pci@vger.kernel.org>,
"Wysocki, Rafael J" <rafael.j.wysocki@intel.com>,
Linux Upstreaming Team <linux@endlessm.com>,
Linux PM <linux-pm@vger.kernel.org>,
Linux USB Mailing List <linux-usb@vger.kernel.org>,
Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: Re: [PATCH] PCI: increase D3 delay for AMD Ryzen5/7 XHCI controllers
Date: Tue, 15 Oct 2019 19:52:41 +0200 [thread overview]
Message-ID: <CAJZ5v0jCh87azmBuhj1T_M+OV8tu7v7Y7WV_zaf56+fxhXU3KQ@mail.gmail.com> (raw)
In-Reply-To: <CAD8Lp45hmYhrj9v-=7NKrG2YHmxZKFExDsHCL67hap+Y2iM-uw@mail.gmail.com>
On Tue, Oct 15, 2019 at 7:31 AM Daniel Drake <drake@endlessm.com> wrote:
>
> On Mon, Oct 14, 2019 at 11:43 PM Bjorn Helgaas <helgaas@kernel.org> wrote:
> > Can you tell if this is because the Ryzen7 XHCI controller is out of
> > spec, or is the Linux PCI core missing some delay? If the latter,
> > fixing the core might fix other devices as well.
> >
> > Mika has this patch:
> > https://lore.kernel.org/r/20190821124519.71594-1-mika.westerberg@linux.intel.com
> > for similar issues, but I think that patch fixes D3cold->D0
> > transitions, and your patch appears to be concerned with D3hot->D0
> > transitions.
>
> It's actually coming out of D3cold here, however what happens right
> before this is that __pci_start_power_transition() calls
> pci_platform_power_transition(D0) to leave D3cold state, then
> pci_update_current_state() reads PMCSR and updates dev->current_state
> to D3hot.
Which pci_update_current_state() do you mean, exactly?
Note that pci_platform_power_transition() itself contains one, which
triggers after a successful change of the ACPI power state of the
device (which should be the case here).
Then, there is one in pci_power_up(), but before that the device's
PMCSR is read from and written to in pci_raw_set_power_state().
It looks like the reads from it after the ACPI power state change are
all successful, but the write isn't unless there is the delay between
it and the former platform_pci_set_power_state().
> The 20ms delay for these XHCI controllers is needed precisely at this
> point - after writing PMCSR to move to D0, and before reading it back
> to check the result.
> I tried moving the delay immediately before writing PMCSR, but that
> doesn't work. Based on that, it seems like it's just a little out of
> spec.
That I agree with and the platform firmware doesn't compensate for
that (which it could do, arguably).
next prev parent reply other threads:[~2019-10-15 17:52 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-14 6:13 [PATCH] PCI: increase D3 delay for AMD Ryzen5/7 XHCI controllers Daniel Drake
2019-10-14 15:43 ` Bjorn Helgaas
2019-10-15 5:31 ` Daniel Drake
2019-10-15 17:52 ` Rafael J. Wysocki [this message]
2019-10-16 6:14 ` Daniel Drake
2019-10-21 11:33 ` Mika Westerberg
2019-10-22 2:40 ` Daniel Drake
2019-10-22 9:33 ` Mika Westerberg
2019-10-23 22:40 ` Bjorn Helgaas
2019-10-24 3:28 ` Daniel Drake
2019-10-24 17:00 ` Bjorn Helgaas
2019-10-25 7:11 ` Daniel Drake
2019-10-25 16:28 ` Bjorn Helgaas
2019-10-28 6:32 ` Daniel Drake
2019-11-18 8:52 ` Daniel Drake
2019-11-20 0:28 ` Bjorn Helgaas
2019-11-21 18:15 ` Bjorn Helgaas
2019-11-22 3:00 ` Daniel Drake
2019-11-22 11:15 ` Rafael J. Wysocki
2019-11-25 3:45 ` Daniel Drake
2019-11-25 13:37 ` Rafael J. Wysocki
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