From: Daniel Drake <drake@endlessm.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>,
Linux PCI <linux-pci@vger.kernel.org>,
"Wysocki, Rafael J" <rafael.j.wysocki@intel.com>,
Linux Upstreaming Team <linux@endlessm.com>,
Linux PM <linux-pm@vger.kernel.org>,
Linux USB Mailing List <linux-usb@vger.kernel.org>
Subject: Re: [PATCH] PCI: increase D3 delay for AMD Ryzen5/7 XHCI controllers
Date: Fri, 25 Oct 2019 15:11:49 +0800 [thread overview]
Message-ID: <CAD8Lp47HgAi-86ni5WHhZT1-sEd7oJEZUiG6KNU66qpmRCfaXw@mail.gmail.com> (raw)
In-Reply-To: <20191024170023.GA135695@google.com>
On Fri, Oct 25, 2019 at 1:00 AM Bjorn Helgaas <helgaas@kernel.org> wrote:
> That's really strange. Your original message showed:
>
> xhci_hcd 0000:03:00.4: Refused to change power state, currently in D3
> xhci_hcd 0000:03:00.4: enabling device (0000 -> 0002)
>
> The first line is from pci_raw_set_power_state() reading PCI_PM_CTRL,
> but we can't tell whether the read failed and we got ~0, or it
> succeeded and we got something with just the low two bits set. Can
> you print out the whole value so we can see what happened?
>
> The second line is from pci_enable_resources() reading PCI_COMMAND,
> and it got *0*, not 0x0403 as you got from the CRS experiment.
Thanks for persisting here. In more detail:
pci_pm_resume_noirq
- pci_pm_default_resume_early
-- pci_raw_set_power_state(D0)
At this point, pci_dev_wait() reads PCI_COMMAND to be 0x100403 (32-bit
read) - so no wait.
pci_raw_set_power_state writes to PM_CTRL and then reads it back with value 0x3.
> xhci_hcd 0000:03:00.4: Refused to change power state, currently in D3
At the point of return from pci_pm_resume_noirq, an extra check I
added shows that PCI_COMMAND has value 0x403 (16-bit read).
35ms later, pci_pm_resume is entered, and I checked that at this
point, PCI_COMMAND has value 0.
It then goes on to reach pci_enable_resources().
> xhci_hcd 0000:03:00.4: enabling device (0000 -> 0002)
The change in PCI_COMMAND value is just down to timing.
At the end of pci_pm_resume_noirq(), if I log PCI_COMMAND, wait 10ms,
and log PCI_COMMAND again, I see it transition from 0x403 to 0.
Daniel
next prev parent reply other threads:[~2019-10-25 7:12 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-14 6:13 [PATCH] PCI: increase D3 delay for AMD Ryzen5/7 XHCI controllers Daniel Drake
2019-10-14 15:43 ` Bjorn Helgaas
2019-10-15 5:31 ` Daniel Drake
2019-10-15 17:52 ` Rafael J. Wysocki
2019-10-16 6:14 ` Daniel Drake
2019-10-21 11:33 ` Mika Westerberg
2019-10-22 2:40 ` Daniel Drake
2019-10-22 9:33 ` Mika Westerberg
2019-10-23 22:40 ` Bjorn Helgaas
2019-10-24 3:28 ` Daniel Drake
2019-10-24 17:00 ` Bjorn Helgaas
2019-10-25 7:11 ` Daniel Drake [this message]
2019-10-25 16:28 ` Bjorn Helgaas
2019-10-28 6:32 ` Daniel Drake
2019-11-18 8:52 ` Daniel Drake
2019-11-20 0:28 ` Bjorn Helgaas
2019-11-21 18:15 ` Bjorn Helgaas
2019-11-22 3:00 ` Daniel Drake
2019-11-22 11:15 ` Rafael J. Wysocki
2019-11-25 3:45 ` Daniel Drake
2019-11-25 13:37 ` Rafael J. Wysocki
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