From: Michael Ellerman <mpe@ellerman.id.au>
To: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Cc: mikey@neuling.org, maddy@linux.vnet.ibm.com,
linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH v2 03/10] powerpc/xmon: Add PowerISA v3.1 PMU SPRs
Date: Wed, 08 Jul 2020 21:04:46 +1000 [thread overview]
Message-ID: <871rlm469d.fsf@mpe.ellerman.id.au> (raw)
In-Reply-To: <1593595262-1433-4-git-send-email-atrajeev@linux.vnet.ibm.com>
Athira Rajeev <atrajeev@linux.vnet.ibm.com> writes:
> From: Madhavan Srinivasan <maddy@linux.ibm.com>
>
> PowerISA v3.1 added three new perfromance
> monitoring unit (PMU) speical purpose register (SPR).
> They are Monitor Mode Control Register 3 (MMCR3),
> Sampled Instruction Event Register 2 (SIER2),
> Sampled Instruction Event Register 3 (SIER3).
>
> Patch here adds a new dump function dump_310_sprs
> to print these SPR values.
>
> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
> ---
> arch/powerpc/xmon/xmon.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> index 7efe4bc..8917fe8 100644
> --- a/arch/powerpc/xmon/xmon.c
> +++ b/arch/powerpc/xmon/xmon.c
> @@ -2022,6 +2022,20 @@ static void dump_300_sprs(void)
> #endif
> }
>
> +static void dump_310_sprs(void)
> +{
> +#ifdef CONFIG_PPC64
> + if (!cpu_has_feature(CPU_FTR_ARCH_31))
> + return;
> +
> + printf("mmcr3 = %.16lx\n",
> + mfspr(SPRN_MMCR3));
> +
> + printf("sier2 = %.16lx sier3 = %.16lx\n",
> + mfspr(SPRN_SIER2), mfspr(SPRN_SIER3));
Why not all on one line like many of the others?
cheers
next prev parent reply other threads:[~2020-07-08 11:04 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-01 9:20 [PATCH v2 00/10] powerpc/perf: Add support for power10 PMU Hardware Athira Rajeev
2020-07-01 9:20 ` [PATCH v2 01/10] powerpc/perf: Add support for ISA3.1 PMU SPRs Athira Rajeev
2020-07-08 11:02 ` Michael Ellerman
2020-07-09 1:53 ` Athira Rajeev
2020-07-13 12:50 ` Michael Ellerman
2020-07-15 6:07 ` Athira Rajeev
2020-07-01 9:20 ` [PATCH v2 02/10] KVM: PPC: Book3S HV: Save/restore new PMU registers Athira Rajeev
2020-07-01 11:11 ` Paul Mackerras
2020-07-02 6:22 ` Athira Rajeev
2020-07-07 6:13 ` Michael Neuling
2020-07-01 9:20 ` [PATCH v2 03/10] powerpc/xmon: Add PowerISA v3.1 PMU SPRs Athira Rajeev
2020-07-08 11:04 ` Michael Ellerman [this message]
2020-07-09 1:57 ` Athira Rajeev
2020-07-01 9:20 ` [PATCH v2 04/10] powerpc/perf: Add power10_feat to dt_cpu_ftrs Athira Rajeev
2020-07-07 6:22 ` Michael Neuling
2020-07-08 2:13 ` Athira Rajeev
2020-07-08 11:15 ` Michael Ellerman
2020-07-09 11:07 ` Athira Rajeev
2020-07-01 9:20 ` [PATCH v2 05/10] powerpc/perf: Update Power PMU cache_events to u64 type Athira Rajeev
2020-07-01 9:20 ` [PATCH v2 06/10] powerpc/perf: power10 Performance Monitoring support Athira Rajeev
2020-07-02 9:06 ` kernel test robot
2020-07-07 6:50 ` Michael Neuling
2020-07-08 10:56 ` Athira Rajeev
2020-07-01 9:20 ` [PATCH v2 07/10] powerpc/perf: support BHRB disable bit and new filtering modes Athira Rajeev
2020-07-07 7:17 ` Michael Neuling
2020-07-08 7:41 ` Athira Rajeev
2020-07-08 7:43 ` Gautham R Shenoy
2020-07-09 2:01 ` Athira Rajeev
2020-07-08 11:42 ` Michael Ellerman
2020-07-09 2:43 ` Athira Rajeev
2020-07-01 9:21 ` [PATCH v2 08/10] powerpc/perf: Add support for outputting extended regs in perf intr_regs Athira Rajeev
2020-07-01 9:21 ` [PATCH v2 09/10] tools/perf: Add perf tools support for extended register capability in powerpc Athira Rajeev
2020-07-08 12:04 ` Michael Ellerman
2020-07-09 3:10 ` Athira Rajeev
2020-07-13 12:47 ` Michael Ellerman
2020-07-13 2:36 ` Athira Rajeev
2020-07-01 9:21 ` [PATCH v2 10/10] powerpc/perf: Add extended regs support for power10 platform Athira Rajeev
2020-07-02 9:40 ` kernel test robot
2020-07-08 1:53 ` Athira Rajeev
2020-07-08 12:04 ` Michael Ellerman
2020-07-09 6:29 ` Athira Rajeev
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