From: "Fenghua Yu" <fenghua.yu@intel.com>
To: "Thomas Gleixner" <tglx@linutronix.de>,
"Ingo Molnar" <mingo@elte.hu>,
"H. Peter Anvin" <h.peter.anvin@intel.com>,
"Tony Luck" <tony.luck@intel.com>, "Tejun Heo" <tj@kernel.org>,
"Borislav Petkov" <bp@suse.de>,
"Stephane Eranian" <eranian@google.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"David Carrillo-Cisneros" <davidcc@google.com>,
"Ravi V Shankar" <ravi.v.shankar@intel.com>,
"Vikas Shivappa" <vikas.shivappa@linux.intel.com>,
"Sai Prakhya" <sai.praneeth.prakhya@intel.com>
Cc: "linux-kernel" <linux-kernel@vger.kernel.org>,
"x86" <x86@kernel.org>, "Fenghua Yu" <fenghua.yu@intel.com>
Subject: [PATCH 17/32] x86, intel_cacheinfo: Enable cache id in x86
Date: Tue, 12 Jul 2016 18:02:50 -0700 [thread overview]
Message-ID: <1468371785-53231-18-git-send-email-fenghua.yu@intel.com> (raw)
In-Reply-To: <1468371785-53231-1-git-send-email-fenghua.yu@intel.com>
From: Fenghua Yu <fenghua.yu@intel.com>
Enable cache id in x86. Cache id comes from APIC ID and CPUID4.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Acked-by: Borislav Petkov <bp@suse.com>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index de6626c..8dc5720 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -153,6 +153,7 @@ struct _cpuid4_info_regs {
union _cpuid4_leaf_eax eax;
union _cpuid4_leaf_ebx ebx;
union _cpuid4_leaf_ecx ecx;
+ unsigned int id;
unsigned long size;
struct amd_northbridge *nb;
};
@@ -894,6 +895,8 @@ static void __cache_cpumap_setup(unsigned int cpu, int index,
static void ci_leaf_init(struct cacheinfo *this_leaf,
struct _cpuid4_info_regs *base)
{
+ this_leaf->id = base->id;
+ this_leaf->attributes = CACHE_ID;
this_leaf->level = base->eax.split.level;
this_leaf->type = cache_type_map[base->eax.split.type];
this_leaf->coherency_line_size =
@@ -920,6 +923,22 @@ static int __init_cache_level(unsigned int cpu)
return 0;
}
+/*
+ * The max shared threads number comes from CPUID.4:EAX[25-14] with input
+ * ECX as cache index. Then right shift apicid by the number's order to get
+ * cache id for this cache node.
+ */
+static void get_cache_id(int cpu, struct _cpuid4_info_regs *id4_regs)
+{
+ struct cpuinfo_x86 *c = &cpu_data(cpu);
+ unsigned long num_threads_sharing;
+ int index_msb;
+
+ num_threads_sharing = 1 + id4_regs->eax.split.num_threads_sharing;
+ index_msb = get_count_order(num_threads_sharing);
+ id4_regs->id = c->apicid >> index_msb;
+}
+
static int __populate_cache_leaves(unsigned int cpu)
{
unsigned int idx, ret;
@@ -931,6 +950,7 @@ static int __populate_cache_leaves(unsigned int cpu)
ret = cpuid4_cache_lookup_regs(idx, &id4_regs);
if (ret)
return ret;
+ get_cache_id(cpu, &id4_regs);
ci_leaf_init(this_leaf++, &id4_regs);
__cache_cpumap_setup(cpu, idx, &id4_regs);
}
--
2.5.0
next prev parent reply other threads:[~2016-07-12 22:04 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-13 1:02 [PATCH 00/32] Enable Intel Resource Allocation in Resource Director Technology Fenghua Yu
2016-07-13 1:02 ` [PATCH 01/32] x86/intel_rdt: Cache Allocation documentation Fenghua Yu
2016-07-13 1:02 ` [PATCH 02/32] x86/intel_rdt: Add support for Cache Allocation detection Fenghua Yu
2016-07-26 19:00 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 03/32] x86/intel_rdt: Add Class of service management Fenghua Yu
2016-07-13 1:02 ` [PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management Fenghua Yu
2016-07-22 7:12 ` Marcelo Tosatti
2016-07-22 21:43 ` Luck, Tony
2016-07-23 4:31 ` Marcelo Tosatti
2016-07-26 3:18 ` Luck, Tony
2016-07-26 17:10 ` Shivappa Vikas
2016-07-13 1:02 ` [PATCH 05/32] x86/intel_rdt: Implement scheduling support for Intel RDT Fenghua Yu
2016-07-25 16:25 ` Nilay Vaish
2016-07-25 16:31 ` Nilay Vaish
2016-07-25 18:05 ` Luck, Tony
2016-07-25 22:47 ` David Carrillo-Cisneros
2016-07-13 1:02 ` [PATCH 06/32] x86/intel_rdt: Hot cpu support for Cache Allocation Fenghua Yu
2016-07-13 9:19 ` Thomas Gleixner
2016-07-21 19:46 ` Shivappa Vikas
2016-07-14 0:40 ` David Carrillo-Cisneros
2016-07-14 22:58 ` Yu, Fenghua
2016-07-13 1:02 ` [PATCH 07/32] x86/intel_rdt: Intel haswell Cache Allocation enumeration Fenghua Yu
2016-07-13 1:02 ` [PATCH 08/32] Define CONFIG_INTEL_RDT Fenghua Yu
2016-07-13 10:25 ` Thomas Gleixner
2016-07-13 18:05 ` Yu, Fenghua
2016-07-13 21:09 ` Thomas Gleixner
2016-07-13 21:18 ` Yu, Fenghua
2016-07-13 1:02 ` [PATCH 09/32] x86/intel_rdt: Intel Code Data Prioritization detection Fenghua Yu
2016-07-13 1:02 ` [PATCH 10/32] x86/intel_rdt: Adds support to enable Code Data Prioritization Fenghua Yu
2016-07-26 19:23 ` Nilay Vaish
2016-07-26 20:32 ` Shivappa Vikas
2016-07-13 1:02 ` [PATCH 11/32] x86/intel_rdt: Class of service and capacity bitmask management for CDP Fenghua Yu
2016-07-13 1:02 ` [PATCH 12/32] x86/intel_rdt: Hot cpu update for code data prioritization Fenghua Yu
2016-07-13 1:02 ` [PATCH 13/32] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu
2016-07-13 12:47 ` Thomas Gleixner
2016-07-13 17:13 ` Luck, Tony
2016-07-14 6:53 ` Thomas Gleixner
2016-07-14 17:16 ` Luck, Tony
2016-07-19 12:32 ` Thomas Gleixner
2016-08-04 23:38 ` Yu, Fenghua
2016-07-27 16:20 ` Nilay Vaish
2016-07-27 16:57 ` Luck, Tony
2016-08-03 22:15 ` Marcelo Tosatti
2016-07-13 1:02 ` [PATCH 14/32] x86/cpufeatures: Get max closid and max cbm len and clean feature comments and code Fenghua Yu
2016-07-27 16:49 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 15/32] cacheinfo: Introduce cache id Fenghua Yu
2016-07-27 17:04 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 16/32] Documentation, ABI: Add a document entry for " Fenghua Yu
2016-07-13 1:02 ` Fenghua Yu [this message]
2016-07-28 5:41 ` [PATCH 17/32] x86, intel_cacheinfo: Enable cache id in x86 Nilay Vaish
2016-07-13 1:02 ` [PATCH 18/32] drivers/base/cacheinfo.c: Export some cacheinfo functions for others to use Fenghua Yu
2016-07-13 1:02 ` [PATCH 19/32] sched.h: Add rg_list and rdtgroup in task_struct Fenghua Yu
2016-07-13 12:56 ` Thomas Gleixner
2016-07-13 17:50 ` Yu, Fenghua
2016-07-28 5:53 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 20/32] magic number for rscctrl file system Fenghua Yu
2016-07-28 5:57 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 21/32] x86/intel_rdt.h: Header for inter_rdt.c Fenghua Yu
2016-07-28 14:07 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 22/32] x86/intel_rdt_rdtgroup.h: Header for user interface Fenghua Yu
2016-07-13 1:02 ` [PATCH 23/32] x86/intel_rdt.c: Extend RDT to per cache and per resources Fenghua Yu
2016-07-13 13:07 ` Thomas Gleixner
2016-07-13 17:40 ` Yu, Fenghua
2016-07-13 1:02 ` [PATCH 24/32] Task fork and exit for rdtgroup Fenghua Yu
2016-07-13 13:14 ` Thomas Gleixner
2016-07-13 17:32 ` Yu, Fenghua
2016-07-13 21:02 ` Thomas Gleixner
2016-07-13 21:22 ` Yu, Fenghua
2016-07-13 1:02 ` [PATCH 25/32] x86/intel_rdt_rdtgroup.c: User interface for RDT Fenghua Yu
2016-07-14 12:30 ` Thomas Gleixner
2016-07-13 1:02 ` [PATCH 26/32] x86/intel_rdt_rdtgroup.c: Create info directory Fenghua Yu
2016-07-13 1:03 ` [PATCH 27/32] x86/intel_rdt_rdtgroup.c: Implement rscctrl file system commands Fenghua Yu
2016-07-13 1:03 ` [PATCH 28/32] x86/intel_rdt_rdtgroup.c: Read and write cpus Fenghua Yu
2016-07-13 1:03 ` [PATCH 29/32] x86/intel_rdt_rdtgroup.c: Tasks iterator and write Fenghua Yu
2016-07-13 1:03 ` [PATCH 30/32] x86/intel_rdt_rdtgroup.c: Process schemas input from rscctrl interface Fenghua Yu
2016-07-14 0:41 ` David Carrillo-Cisneros
2016-07-14 6:11 ` Thomas Gleixner
2016-07-14 6:16 ` Yu, Fenghua
2016-07-14 6:32 ` Yu, Fenghua
2016-07-13 1:03 ` [PATCH 31/32] MAINTAINERS: Add maintainer for Intel RDT resource allocation Fenghua Yu
2016-07-13 1:03 ` [PATCH 32/32] x86/Makefile: Build intel_rdt_rdtgroup.c Fenghua Yu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1468371785-53231-18-git-send-email-fenghua.yu@intel.com \
--to=fenghua.yu@intel.com \
--cc=bp@suse.de \
--cc=davidcc@google.com \
--cc=eranian@google.com \
--cc=h.peter.anvin@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@elte.hu \
--cc=mtosatti@redhat.com \
--cc=peterz@infradead.org \
--cc=ravi.v.shankar@intel.com \
--cc=sai.praneeth.prakhya@intel.com \
--cc=tglx@linutronix.de \
--cc=tj@kernel.org \
--cc=tony.luck@intel.com \
--cc=vikas.shivappa@linux.intel.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).