From: Nilay Vaish <nilayvaish@gmail.com>
To: Fenghua Yu <fenghua.yu@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@elte.hu>,
"H. Peter Anvin" <h.peter.anvin@intel.com>,
Tony Luck <tony.luck@intel.com>, Tejun Heo <tj@kernel.org>,
Borislav Petkov <bp@suse.de>,
Stephane Eranian <eranian@google.com>,
Peter Zijlstra <peterz@infradead.org>,
Marcelo Tosatti <mtosatti@redhat.com>,
David Carrillo-Cisneros <davidcc@google.com>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
Vikas Shivappa <vikas.shivappa@linux.intel.com>,
Sai Prakhya <sai.praneeth.prakhya@intel.com>,
linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH 14/32] x86/cpufeatures: Get max closid and max cbm len and clean feature comments and code
Date: Wed, 27 Jul 2016 11:49:51 -0500 [thread overview]
Message-ID: <CACbG308m-Xpsihr872PPSJVKiM_NwGv6=JzMi6Wcgew+XufWcw@mail.gmail.com> (raw)
In-Reply-To: <1468371785-53231-15-git-send-email-fenghua.yu@intel.com>
On 12 July 2016 at 20:02, Fenghua Yu <fenghua.yu@intel.com> wrote:
> From: Fenghua Yu <fenghua.yu@intel.com>
>
> Define two new cpuid leaves for CAT and CDP. The leaves are used in
> x86_capability to avoid hard coded index.
>
> Clean comments for RDT, CAT_L3, and CDP_L3 cpufeatures.
>
> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
> Reviewed-by: Tony Luck <tony.luck@intel.com>
> ---
> arch/x86/include/asm/cpufeature.h | 2 ++
> arch/x86/include/asm/cpufeatures.h | 6 +++---
> arch/x86/include/asm/processor.h | 6 +++---
> arch/x86/kernel/cpu/common.c | 11 +++++++----
> 4 files changed, 15 insertions(+), 10 deletions(-)
>
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index 483fb54..cd3b0bd 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -28,6 +28,8 @@ enum cpuid_leafs
> CPUID_8000_000A_EDX,
> CPUID_7_ECX,
> CPUID_8000_0007_EBX,
> + CPUID_10_0_EBX,
> + CPUID_10_1_ECX,
> };
>
> #ifdef CONFIG_X86_FEATURE_NAMES
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 16489b3..588932a 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -220,7 +220,7 @@
> #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
> #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
> #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
> -#define X86_FEATURE_RDT ( 9*32+15) /* Resource Allocation */
> +#define X86_FEATURE_RDT ( 9*32+15) /* Resource Director Technology */
> #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
> #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
> #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
> @@ -289,10 +289,10 @@
> #define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */
>
> /* Intel-defined CPU features, CPUID level 0x00000010:0 (ebx), word 18 */
> -#define X86_FEATURE_CAT_L3 (18*32+ 1) /* Cache Allocation L3 */
> +#define X86_FEATURE_CAT_L3 (18*32+ 1) /* Cache Allocation L3 */
>
> /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x00000010:1 (ecx), word 19 */
> -#define X86_FEATURE_CDP_L3 (19*32+ 2) /* Code data prioritization L3 */
> +#define X86_FEATURE_CDP_L3 (19*32+ 2) /* Code Data Prioritization L3 */
>
> /*
> * BUG word(s)
> diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
> index 598c9bc..308aa03 100644
> --- a/arch/x86/include/asm/processor.h
> +++ b/arch/x86/include/asm/processor.h
> @@ -119,9 +119,9 @@ struct cpuinfo_x86 {
> int x86_cache_occ_scale; /* scale to bytes */
> int x86_power;
> unsigned long loops_per_jiffy;
> - /* Cache Allocation values: */
> - u16 x86_cache_max_cbm_len;
> - u16 x86_cache_max_closid;
> + /* Cache Allocation l3 values: */
> + u16 x86_l3_max_cbm_len;
> + u16 x86_l3_max_closid;
> /* cpuid returned max cores value: */
> u16 x86_max_cores;
> u16 apicid;
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index a695e58..e945e70 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -716,14 +716,17 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
> u32 eax, ebx, ecx, edx;
>
> cpuid_count(0x00000010, 0, &eax, &ebx, &ecx, &edx);
> - c->x86_capability[17] = ebx;
> + c->x86_capability[CPUID_10_0_EBX] = ebx;
>
> if (cpu_has(c, X86_FEATURE_CAT_L3)) {
>
> cpuid_count(0x00000010, 1, &eax, &ebx, &ecx, &edx);
> - c->x86_cache_max_closid = edx + 1;
> - c->x86_cache_max_cbm_len = eax + 1;
> - c->x86_capability[18] = ecx;
> + c->x86_l3_max_closid = edx + 1;
> + c->x86_l3_max_cbm_len = eax + 1;
> + c->x86_capability[CPUID_10_1_ECX] = ecx;
> + } else {
> + c->x86_l3_max_closid = -1;
> + c->x86_l3_max_cbm_len = -1;
> }
> }
>
I think this patch should be earlier in this patch series where the
constants 17 and 18 were first used. Similarly the renaming of
variables, I think, should be merged with the patch that originally
introduced them.
--
Nilay
next prev parent reply other threads:[~2016-07-27 16:50 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-13 1:02 [PATCH 00/32] Enable Intel Resource Allocation in Resource Director Technology Fenghua Yu
2016-07-13 1:02 ` [PATCH 01/32] x86/intel_rdt: Cache Allocation documentation Fenghua Yu
2016-07-13 1:02 ` [PATCH 02/32] x86/intel_rdt: Add support for Cache Allocation detection Fenghua Yu
2016-07-26 19:00 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 03/32] x86/intel_rdt: Add Class of service management Fenghua Yu
2016-07-13 1:02 ` [PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management Fenghua Yu
2016-07-22 7:12 ` Marcelo Tosatti
2016-07-22 21:43 ` Luck, Tony
2016-07-23 4:31 ` Marcelo Tosatti
2016-07-26 3:18 ` Luck, Tony
2016-07-26 17:10 ` Shivappa Vikas
2016-07-13 1:02 ` [PATCH 05/32] x86/intel_rdt: Implement scheduling support for Intel RDT Fenghua Yu
2016-07-25 16:25 ` Nilay Vaish
2016-07-25 16:31 ` Nilay Vaish
2016-07-25 18:05 ` Luck, Tony
2016-07-25 22:47 ` David Carrillo-Cisneros
2016-07-13 1:02 ` [PATCH 06/32] x86/intel_rdt: Hot cpu support for Cache Allocation Fenghua Yu
2016-07-13 9:19 ` Thomas Gleixner
2016-07-21 19:46 ` Shivappa Vikas
2016-07-14 0:40 ` David Carrillo-Cisneros
2016-07-14 22:58 ` Yu, Fenghua
2016-07-13 1:02 ` [PATCH 07/32] x86/intel_rdt: Intel haswell Cache Allocation enumeration Fenghua Yu
2016-07-13 1:02 ` [PATCH 08/32] Define CONFIG_INTEL_RDT Fenghua Yu
2016-07-13 10:25 ` Thomas Gleixner
2016-07-13 18:05 ` Yu, Fenghua
2016-07-13 21:09 ` Thomas Gleixner
2016-07-13 21:18 ` Yu, Fenghua
2016-07-13 1:02 ` [PATCH 09/32] x86/intel_rdt: Intel Code Data Prioritization detection Fenghua Yu
2016-07-13 1:02 ` [PATCH 10/32] x86/intel_rdt: Adds support to enable Code Data Prioritization Fenghua Yu
2016-07-26 19:23 ` Nilay Vaish
2016-07-26 20:32 ` Shivappa Vikas
2016-07-13 1:02 ` [PATCH 11/32] x86/intel_rdt: Class of service and capacity bitmask management for CDP Fenghua Yu
2016-07-13 1:02 ` [PATCH 12/32] x86/intel_rdt: Hot cpu update for code data prioritization Fenghua Yu
2016-07-13 1:02 ` [PATCH 13/32] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu
2016-07-13 12:47 ` Thomas Gleixner
2016-07-13 17:13 ` Luck, Tony
2016-07-14 6:53 ` Thomas Gleixner
2016-07-14 17:16 ` Luck, Tony
2016-07-19 12:32 ` Thomas Gleixner
2016-08-04 23:38 ` Yu, Fenghua
2016-07-27 16:20 ` Nilay Vaish
2016-07-27 16:57 ` Luck, Tony
2016-08-03 22:15 ` Marcelo Tosatti
2016-07-13 1:02 ` [PATCH 14/32] x86/cpufeatures: Get max closid and max cbm len and clean feature comments and code Fenghua Yu
2016-07-27 16:49 ` Nilay Vaish [this message]
2016-07-13 1:02 ` [PATCH 15/32] cacheinfo: Introduce cache id Fenghua Yu
2016-07-27 17:04 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 16/32] Documentation, ABI: Add a document entry for " Fenghua Yu
2016-07-13 1:02 ` [PATCH 17/32] x86, intel_cacheinfo: Enable cache id in x86 Fenghua Yu
2016-07-28 5:41 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 18/32] drivers/base/cacheinfo.c: Export some cacheinfo functions for others to use Fenghua Yu
2016-07-13 1:02 ` [PATCH 19/32] sched.h: Add rg_list and rdtgroup in task_struct Fenghua Yu
2016-07-13 12:56 ` Thomas Gleixner
2016-07-13 17:50 ` Yu, Fenghua
2016-07-28 5:53 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 20/32] magic number for rscctrl file system Fenghua Yu
2016-07-28 5:57 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 21/32] x86/intel_rdt.h: Header for inter_rdt.c Fenghua Yu
2016-07-28 14:07 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 22/32] x86/intel_rdt_rdtgroup.h: Header for user interface Fenghua Yu
2016-07-13 1:02 ` [PATCH 23/32] x86/intel_rdt.c: Extend RDT to per cache and per resources Fenghua Yu
2016-07-13 13:07 ` Thomas Gleixner
2016-07-13 17:40 ` Yu, Fenghua
2016-07-13 1:02 ` [PATCH 24/32] Task fork and exit for rdtgroup Fenghua Yu
2016-07-13 13:14 ` Thomas Gleixner
2016-07-13 17:32 ` Yu, Fenghua
2016-07-13 21:02 ` Thomas Gleixner
2016-07-13 21:22 ` Yu, Fenghua
2016-07-13 1:02 ` [PATCH 25/32] x86/intel_rdt_rdtgroup.c: User interface for RDT Fenghua Yu
2016-07-14 12:30 ` Thomas Gleixner
2016-07-13 1:02 ` [PATCH 26/32] x86/intel_rdt_rdtgroup.c: Create info directory Fenghua Yu
2016-07-13 1:03 ` [PATCH 27/32] x86/intel_rdt_rdtgroup.c: Implement rscctrl file system commands Fenghua Yu
2016-07-13 1:03 ` [PATCH 28/32] x86/intel_rdt_rdtgroup.c: Read and write cpus Fenghua Yu
2016-07-13 1:03 ` [PATCH 29/32] x86/intel_rdt_rdtgroup.c: Tasks iterator and write Fenghua Yu
2016-07-13 1:03 ` [PATCH 30/32] x86/intel_rdt_rdtgroup.c: Process schemas input from rscctrl interface Fenghua Yu
2016-07-14 0:41 ` David Carrillo-Cisneros
2016-07-14 6:11 ` Thomas Gleixner
2016-07-14 6:16 ` Yu, Fenghua
2016-07-14 6:32 ` Yu, Fenghua
2016-07-13 1:03 ` [PATCH 31/32] MAINTAINERS: Add maintainer for Intel RDT resource allocation Fenghua Yu
2016-07-13 1:03 ` [PATCH 32/32] x86/Makefile: Build intel_rdt_rdtgroup.c Fenghua Yu
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