From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<ludovic.desroches@microchip.com>
Cc: <bbrezillon@kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
"Claudiu Beznea" <claudiu.beznea@microchip.com>
Subject: [PATCH 00/19] clk: at91: add sama7g5 clock support
Date: Wed, 15 Jul 2020 14:24:08 +0300 [thread overview]
Message-ID: <1594812267-6697-1-git-send-email-claudiu.beznea@microchip.com> (raw)
Hi,
This series adds clock support for SAMA7G5. The first patches in
series, patches 1/19-9/19, contains some fixes (let me know if
you want to send them as a separate series).
For SAMA7G5 clock support some AT91 clock drivers needed changes
because:
1/ some of generated, master and peripheral clocks could have
changeable parents (being able to request frequency changes
from parent)
2/ generated and programmable clocks parents needed a mux table
as the hardware parent index doesn't correspond with software
parent index
3/ there are 4 new master clocks, MCK1..4 (compared with previous
AT91 architectures) which are controlled separately from MCK0
4/ some of the PLLs have 2 outputs the internal block schema being
as follows:
+------+ +--------+
| FRAC |-----+----->| DIVPMC |--->
+------+ | +--------+
|
| +--------+
+----->| DIVIO |--->
+--------+
For this, the clk-sam9x60-pll driver has been re-factored.
Claudiu Beznea (19):
clk: at91: clk-generated: continue if __clk_determine_rate() returns
error
clk: at91: clk-generated: check best_rate against ranges
clk: at91: clk-sam9x60-pll: fix mul mask
clk: at91: sam9x60-pll: use frac when computing pll frequency
clk: at91: sam9x60-pll: use logical or for range check
clk: at91: sam9x60-pll: check fcore against ranges
clk: at91: sam9x60-pll: use frac when setting frequency
clk: at91: sam9x60: fix main rc oscillator frequency
clk: at91: sckc: register slow_rc with accuracy option
clk: at91: replace conditional operator with double logical not
clk: at91: clk-generated: pass the id of changeable parent at
registration
clk: at91: clk-generated: add mux_table option
clk: at91: clk-master: add master clock support for SAMA7G5
clk: at91: clk-peripheral: add support for changeable parent rate
clk: at91: clk-programmable: add mux_table option
clk: at91: add macro for pll ids mask
clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple
outputs
clk: at91: clk-utmi: add utmi support for sama7g5
clk: at91: sama7g5: add clock support for sama7g5
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/at91rm9200.c | 3 +-
drivers/clk/at91/at91sam9260.c | 3 +-
drivers/clk/at91/at91sam9g45.c | 3 +-
drivers/clk/at91/at91sam9n12.c | 5 +-
drivers/clk/at91/at91sam9rl.c | 3 +-
drivers/clk/at91/at91sam9x5.c | 7 +-
drivers/clk/at91/clk-generated.c | 44 +-
drivers/clk/at91/clk-main.c | 6 +-
drivers/clk/at91/clk-master.c | 310 +++++++++-
drivers/clk/at91/clk-peripheral.c | 111 +++-
drivers/clk/at91/clk-programmable.c | 11 +-
drivers/clk/at91/clk-sam9x60-pll.c | 547 ++++++++++++------
drivers/clk/at91/clk-system.c | 4 +-
drivers/clk/at91/clk-utmi.c | 103 +++-
drivers/clk/at91/dt-compat.c | 25 +-
drivers/clk/at91/pmc.h | 43 +-
drivers/clk/at91/sam9x60.c | 64 ++-
drivers/clk/at91/sama5d2.c | 41 +-
drivers/clk/at91/sama5d3.c | 6 +-
drivers/clk/at91/sama5d4.c | 7 +-
drivers/clk/at91/sama7g5.c | 1059 +++++++++++++++++++++++++++++++++++
drivers/clk/at91/sckc.c | 5 +-
include/linux/clk/at91_pmc.h | 4 +
24 files changed, 2140 insertions(+), 275 deletions(-)
create mode 100644 drivers/clk/at91/sama7g5.c
--
2.7.4
next reply other threads:[~2020-07-15 11:24 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-15 11:24 Claudiu Beznea [this message]
2020-07-15 11:24 ` [PATCH 01/19] clk: at91: clk-generated: continue if __clk_determine_rate() returns error Claudiu Beznea
2020-07-17 9:09 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 02/19] clk: at91: clk-generated: check best_rate against ranges Claudiu Beznea
2020-07-17 9:10 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 03/19] clk: at91: clk-sam9x60-pll: fix mul mask Claudiu Beznea
2020-07-17 9:11 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 04/19] clk: at91: sam9x60-pll: use frac when computing pll frequency Claudiu Beznea
2020-07-15 11:24 ` [PATCH 05/19] clk: at91: sam9x60-pll: use logical or for range check Claudiu Beznea
2020-07-17 9:13 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 06/19] clk: at91: sam9x60-pll: check fcore against ranges Claudiu Beznea
2020-07-17 9:23 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 07/19] clk: at91: sam9x60-pll: use frac when setting frequency Claudiu Beznea
2020-07-17 9:12 ` Alexandre Belloni
2020-07-20 10:34 ` Claudiu.Beznea
2020-07-15 11:24 ` [PATCH 08/19] clk: at91: sam9x60: fix main rc oscillator frequency Claudiu Beznea
2020-07-17 9:17 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 09/19] clk: at91: sckc: register slow_rc with accuracy option Claudiu Beznea
2020-07-15 15:39 ` Claudiu.Beznea
2020-07-15 11:24 ` [PATCH 10/19] clk: at91: replace conditional operator with double logical not Claudiu Beznea
2020-07-17 15:07 ` Alexandre Belloni
2020-07-20 10:36 ` Claudiu.Beznea
2020-07-15 11:24 ` [PATCH 11/19] clk: at91: clk-generated: pass the id of changeable parent at registration Claudiu Beznea
2020-07-16 16:57 ` Codrin.Ciubotariu
2020-07-15 11:24 ` [PATCH 12/19] clk: at91: clk-generated: add mux_table option Claudiu Beznea
2020-07-15 11:24 ` [PATCH 13/19] clk: at91: clk-master: add master clock support for SAMA7G5 Claudiu Beznea
2020-07-15 11:24 ` [PATCH 14/19] clk: at91: clk-peripheral: add support for changeable parent rate Claudiu Beznea
2020-07-15 11:24 ` [PATCH 15/19] clk: at91: clk-programmable: add mux_table option Claudiu Beznea
2020-07-15 11:24 ` [PATCH 16/19] clk: at91: add macro for pll ids mask Claudiu Beznea
2020-07-15 11:24 ` [PATCH 17/19] clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs Claudiu Beznea
2020-07-15 11:24 ` [PATCH 18/19] clk: at91: clk-utmi: add utmi support for sama7g5 Claudiu Beznea
2020-07-15 11:24 ` [PATCH 19/19] clk: at91: sama7g5: add clock " Claudiu Beznea
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