* [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs @ 2017-11-28 15:26 Alexandre Belloni 2017-11-28 15:26 ` [PATCH 01/13] dt-bindings: Add vendor prefix for Microsemi Corporation Alexandre Belloni ` (12 more replies) 0 siblings, 13 replies; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 15:26 UTC (permalink / raw) To: Ralf Baechle Cc: linux-mips, linux-kernel, Alexandre Belloni, Rob Herring, devicetree, Thomas Gleixner, Jason Cooper, Linus Walleij, linux-gpio, Sebastian Reichel, linux-pm Hi, This patch series adds initial support for the Microsemi MIPS SoCs. It is currently focusing on the Microsemi Ocelot (VSC7513, VSC7514). It adds support for the IRQ controller, pinmux and gpio controller and reset control. This produces a kernel that can boot to the console. This is a single series for reference but it can also be taken separately by each maintainer as each drivers are independant. Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: Sebastian Reichel <sre@kernel.org> Cc: linux-pm@vger.kernel.org Alexandre Belloni (13): dt-bindings: Add vendor prefix for Microsemi Corporation dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller irqchip: Add a driver for the Microsemi Ocelot controller dt-bindings: pinctrl: Add bindings for Microsemi Ocelot pinctrl: Add Microsemi Ocelot SoC driver dt-bindings: power: reset: Document ocelot-reset binding power: reset: Add a driver for the Microsemi Ocelot reset dt-bindings: mips: Add bindings for Microsemi SoCs MIPS: mscc: Add initial support for Microsemi MIPS SoCs MIPS: mscc: add ocelot dtsi MIPS: mscc: add ocelot PCB123 device tree MIPS: defconfigs: add a defconfig for Microsemi SoCs MAINTAINERS: Add entry for Microsemi MIPS SoCs .../interrupt-controller/mscc,ocelot-icpu-intr.txt | 22 + Documentation/devicetree/bindings/mips/mscc.txt | 6 + .../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 39 ++ .../bindings/power/reset/ocelot-reset.txt | 24 + .../devicetree/bindings/vendor-prefixes.txt | 1 + MAINTAINERS | 7 + arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 24 + arch/mips/boot/dts/Makefile | 1 + arch/mips/boot/dts/mscc/Makefile | 6 + arch/mips/boot/dts/mscc/ocelot.dtsi | 118 +++++ arch/mips/boot/dts/mscc/ocelot_pcb123.dts | 30 ++ arch/mips/configs/mscc_defconfig | 84 ++++ arch/mips/mscc/Makefile | 11 + arch/mips/mscc/Platform | 12 + arch/mips/mscc/setup.c | 106 +++++ drivers/irqchip/Kconfig | 5 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-mscc-ocelot.c | 109 +++++ drivers/pinctrl/Kconfig | 10 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-ocelot.c | 505 +++++++++++++++++++++ drivers/power/reset/Kconfig | 7 + drivers/power/reset/Makefile | 1 + drivers/power/reset/ocelot-reset.c | 87 ++++ 25 files changed, 1218 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt create mode 100644 arch/mips/boot/dts/mscc/Makefile create mode 100644 arch/mips/boot/dts/mscc/ocelot.dtsi create mode 100644 arch/mips/boot/dts/mscc/ocelot_pcb123.dts create mode 100644 arch/mips/configs/mscc_defconfig create mode 100644 arch/mips/mscc/Makefile create mode 100644 arch/mips/mscc/Platform create mode 100644 arch/mips/mscc/setup.c create mode 100644 drivers/irqchip/irq-mscc-ocelot.c create mode 100644 drivers/pinctrl/pinctrl-ocelot.c create mode 100644 drivers/power/reset/ocelot-reset.c -- 2.15.0 ^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 01/13] dt-bindings: Add vendor prefix for Microsemi Corporation 2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni @ 2017-11-28 15:26 ` Alexandre Belloni 2017-11-28 16:10 ` James Hogan 2017-11-28 15:26 ` [PATCH 02/13] dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller Alexandre Belloni ` (11 subsequent siblings) 12 siblings, 1 reply; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 15:26 UTC (permalink / raw) To: Ralf Baechle Cc: linux-mips, linux-kernel, Alexandre Belloni, Rob Herring, devicetree Microsemi Corporation provides semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 0994bdd82cd3..7b880084fd37 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -219,6 +219,7 @@ motorola Motorola, Inc. moxa Moxa Inc. mpl MPL AG mqmaker mqmaker Inc. +mscc Microsemi Corporation msi Micro-Star International Co. Ltd. mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.) multi-inno Multi-Inno Technology Co.,Ltd -- 2.15.0 ^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH 01/13] dt-bindings: Add vendor prefix for Microsemi Corporation 2017-11-28 15:26 ` [PATCH 01/13] dt-bindings: Add vendor prefix for Microsemi Corporation Alexandre Belloni @ 2017-11-28 16:10 ` James Hogan 2017-11-28 16:22 ` Alexandre Belloni 0 siblings, 1 reply; 31+ messages in thread From: James Hogan @ 2017-11-28 16:10 UTC (permalink / raw) To: Alexandre Belloni Cc: Ralf Baechle, linux-mips, linux-kernel, Rob Herring, devicetree [-- Attachment #1: Type: text/plain, Size: 1271 bytes --] On Tue, Nov 28, 2017 at 04:26:31PM +0100, Alexandre Belloni wrote: > Microsemi Corporation provides semiconductor and system solutions for > aerospace & defense, communications, data center and industrial markets. > > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > --- > Cc: Rob Herring <robh+dt@kernel.org> > Cc: devicetree@vger.kernel.org Nit: Usually the Cc list goes before the --- line so that it is included in the git history (i.e. these people had the opportunity to comment). Cheers James > > > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt > index 0994bdd82cd3..7b880084fd37 100644 > --- a/Documentation/devicetree/bindings/vendor-prefixes.txt > +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt > @@ -219,6 +219,7 @@ motorola Motorola, Inc. > moxa Moxa Inc. > mpl MPL AG > mqmaker mqmaker Inc. > +mscc Microsemi Corporation > msi Micro-Star International Co. Ltd. > mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.) > multi-inno Multi-Inno Technology Co.,Ltd > -- > 2.15.0 > > [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 01/13] dt-bindings: Add vendor prefix for Microsemi Corporation 2017-11-28 16:10 ` James Hogan @ 2017-11-28 16:22 ` Alexandre Belloni 2017-12-01 1:14 ` Rob Herring 0 siblings, 1 reply; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 16:22 UTC (permalink / raw) To: James Hogan Cc: Ralf Baechle, linux-mips, linux-kernel, Rob Herring, devicetree On 28/11/2017 at 16:10:14 +0000, James Hogan wrote: > On Tue, Nov 28, 2017 at 04:26:31PM +0100, Alexandre Belloni wrote: > > Microsemi Corporation provides semiconductor and system solutions for > > aerospace & defense, communications, data center and industrial markets. > > > > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > > --- > > Cc: Rob Herring <robh+dt@kernel.org> > > Cc: devicetree@vger.kernel.org > > Nit: Usually the Cc list goes before the --- line so that it is included > in the git history (i.e. these people had the opportunity to comment). > Ok, it depends on the maintainer, some people prefer leaving that out of commit log. I'm fine with adding those back in. > Cheers > James > > > > > > > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt > > index 0994bdd82cd3..7b880084fd37 100644 > > --- a/Documentation/devicetree/bindings/vendor-prefixes.txt > > +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt > > @@ -219,6 +219,7 @@ motorola Motorola, Inc. > > moxa Moxa Inc. > > mpl MPL AG > > mqmaker mqmaker Inc. > > +mscc Microsemi Corporation > > msi Micro-Star International Co. Ltd. > > mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.) > > multi-inno Multi-Inno Technology Co.,Ltd > > -- > > 2.15.0 > > > > -- Alexandre Belloni, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 01/13] dt-bindings: Add vendor prefix for Microsemi Corporation 2017-11-28 16:22 ` Alexandre Belloni @ 2017-12-01 1:14 ` Rob Herring 0 siblings, 0 replies; 31+ messages in thread From: Rob Herring @ 2017-12-01 1:14 UTC (permalink / raw) To: Alexandre Belloni Cc: James Hogan, Ralf Baechle, linux-mips, linux-kernel, devicetree On Tue, Nov 28, 2017 at 05:22:45PM +0100, Alexandre Belloni wrote: > On 28/11/2017 at 16:10:14 +0000, James Hogan wrote: > > On Tue, Nov 28, 2017 at 04:26:31PM +0100, Alexandre Belloni wrote: > > > Microsemi Corporation provides semiconductor and system solutions for > > > aerospace & defense, communications, data center and industrial markets. > > > > > > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > > > --- > > > Cc: Rob Herring <robh+dt@kernel.org> > > > Cc: devicetree@vger.kernel.org > > > > Nit: Usually the Cc list goes before the --- line so that it is included > > in the git history (i.e. these people had the opportunity to comment). > > > > Ok, it depends on the maintainer, some people prefer leaving that out of commit log. > I'm fine with adding those back in. Really? First, I've heard that. In any case, Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 02/13] dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller 2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni 2017-11-28 15:26 ` [PATCH 01/13] dt-bindings: Add vendor prefix for Microsemi Corporation Alexandre Belloni @ 2017-11-28 15:26 ` Alexandre Belloni 2017-12-01 1:15 ` Rob Herring 2017-11-28 15:26 ` [PATCH 03/13] irqchip: Add a driver for the Microsemi Ocelot controller Alexandre Belloni ` (10 subsequent siblings) 12 siblings, 1 reply; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 15:26 UTC (permalink / raw) To: Ralf Baechle Cc: linux-mips, linux-kernel, Alexandre Belloni, Rob Herring, devicetree, Jason Cooper Add the Device Tree binding documentation for the Microsemi Ocelot interrupt controller that is part of the ICPU. It is connected directly to the MIPS core interrupt controller. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org To: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> .../interrupt-controller/mscc,ocelot-icpu-intr.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt new file mode 100644 index 000000000000..b47a8a02b17b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt @@ -0,0 +1,22 @@ +Microsemi Ocelot SoC ICPU Interrupt Controller + +Required properties: + +- compatible : should be "mscc,ocelot-icpu-intr" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. +- interrupt-parent : phandle of the CPU interrupt controller. +- interrupts : Specifies the CPU interrupt the controller is connected to. + +Example: + + intc: interrupt-controller@70000070 { + compatible = "mscc,ocelot-icpu-intr"; + reg = <0x70000070 0x70>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; -- 2.15.0 ^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH 02/13] dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller 2017-11-28 15:26 ` [PATCH 02/13] dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller Alexandre Belloni @ 2017-12-01 1:15 ` Rob Herring 0 siblings, 0 replies; 31+ messages in thread From: Rob Herring @ 2017-12-01 1:15 UTC (permalink / raw) To: Alexandre Belloni Cc: Ralf Baechle, linux-mips, linux-kernel, devicetree, Jason Cooper On Tue, Nov 28, 2017 at 04:26:32PM +0100, Alexandre Belloni wrote: > Add the Device Tree binding documentation for the Microsemi Ocelot > interrupt controller that is part of the ICPU. It is connected directly to > the MIPS core interrupt controller. > > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > --- > Cc: Rob Herring <robh+dt@kernel.org> > Cc: devicetree@vger.kernel.org > To: Thomas Gleixner <tglx@linutronix.de> > Cc: Jason Cooper <jason@lakedaemon.net> > > .../interrupt-controller/mscc,ocelot-icpu-intr.txt | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 03/13] irqchip: Add a driver for the Microsemi Ocelot controller 2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni 2017-11-28 15:26 ` [PATCH 01/13] dt-bindings: Add vendor prefix for Microsemi Corporation Alexandre Belloni 2017-11-28 15:26 ` [PATCH 02/13] dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller Alexandre Belloni @ 2017-11-28 15:26 ` Alexandre Belloni 2017-11-28 15:26 ` [PATCH 04/13] dt-bindings: pinctrl: Add bindings for Microsemi Ocelot Alexandre Belloni ` (9 subsequent siblings) 12 siblings, 0 replies; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 15:26 UTC (permalink / raw) To: Ralf Baechle; +Cc: linux-mips, linux-kernel, Alexandre Belloni, Jason Cooper The Microsemi Ocelot SoC has a pretty simple IRQ controller in its ICPU block. Add a driver for it. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- To: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> drivers/irqchip/Kconfig | 5 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-mscc-ocelot.c | 109 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 115 insertions(+) create mode 100644 drivers/irqchip/irq-mscc-ocelot.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index c70476b34a53..9605a872da1c 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -286,6 +286,11 @@ config IRQ_MXS select IRQ_DOMAIN select STMP_DEVICE +config MSCC_OCELOT_IRQ + bool + select IRQ_DOMAIN + select GENERIC_IRQ_CHIP + config MVEBU_GICP bool diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index d2df34a54d38..dc549701782d 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -72,6 +72,7 @@ obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o +obj-$(CONFIG_MSCC_OCELOT_IRQ) += irq-mscc-ocelot.o obj-$(CONFIG_MVEBU_GICP) += irq-mvebu-gicp.o obj-$(CONFIG_MVEBU_ICU) += irq-mvebu-icu.o obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c new file mode 100644 index 000000000000..c2cf46758a59 --- /dev/null +++ b/drivers/irqchip/irq-mscc-ocelot.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Microsemi Ocelot IRQ controller driver + * + * License: Dual MIT/GPL + * Copyright (c) 2017 Microsemi Corporation + */ +#include <linux/bitops.h> +#include <linux/irq.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/irqchip.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/interrupt.h> + +#define ICPU_CFG_INTR_INTR_STICKY 0x10 +#define ICPU_CFG_INTR_INTR_ENA 0x18 +#define ICPU_CFG_INTR_INTR_ENA_CLR 0x1c +#define ICPU_CFG_INTR_INTR_ENA_SET 0x20 +#define ICPU_CFG_INTR_DST_INTR_IDENT(x) (0x38 + 0x4 * (x)) +#define ICPU_CFG_INTR_INTR_TRIGGER(x) (0x5c + 0x4 * (x)) + +#define OCELOT_NR_IRQ 24 + +static void ocelot_irq_unmask(struct irq_data *data) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); + struct irq_chip_type *ct = irq_data_get_chip_type(data); + unsigned int mask = data->mask; + u32 val; + + irq_gc_lock(gc); + val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(0)) | + irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(1)); + if ((val & mask) == 0) + irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_STICKY); + + *ct->mask_cache &= ~mask; + irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_ENA_SET); + irq_gc_unlock(gc); +} + +static void ocelot_irq_handler(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct irq_domain *d = irq_desc_get_handler_data(desc); + struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0); + u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(0)); + + chained_irq_enter(chip, desc); + + while (reg) { + u32 hwirq = __fls(reg); + + generic_handle_irq(irq_find_mapping(d, hwirq)); + reg &= ~(BIT(hwirq)); + } + + chained_irq_exit(chip, desc); +} + +static int __init ocelot_irq_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_domain *domain; + struct irq_chip_generic *gc; + int parent_irq, ret; + + domain = irq_domain_add_linear(node, OCELOT_NR_IRQ, + &irq_generic_chip_ops, NULL); + if (!domain) { + pr_err("%s: unable to add irq domain\n", node->name); + return -ENOMEM; + } + + ret = irq_alloc_domain_generic_chips(domain, OCELOT_NR_IRQ, 1, + "icpu", handle_level_irq, + 0, 0, 0); + if (ret) { + pr_err("%s: unable to alloc irq domain gc\n", node->name); + return ret; + } + + gc = irq_get_domain_generic_chip(domain, 0); + gc->reg_base = of_iomap(node, 0); + if (!gc->reg_base) { + pr_err("%s: unable to map resource\n", node->name); + return -ENOMEM; + } + + gc->chip_types[0].regs.ack = ICPU_CFG_INTR_INTR_STICKY; + gc->chip_types[0].regs.mask = ICPU_CFG_INTR_INTR_ENA_CLR; + gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; + gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; + gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask; + + irq_reg_writel(gc, 0, ICPU_CFG_INTR_INTR_ENA); /* Mask all */ + irq_reg_writel(gc, 0xffffffff, ICPU_CFG_INTR_INTR_STICKY); /* Ack pending */ + + parent_irq = irq_of_parse_and_map(node, 0); + if (!parent_irq) + return -EINVAL; + + irq_set_chained_handler_and_data(parent_irq, ocelot_irq_handler, + domain); + + return 0; +} +IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init); -- 2.15.0 ^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 04/13] dt-bindings: pinctrl: Add bindings for Microsemi Ocelot 2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni ` (2 preceding siblings ...) 2017-11-28 15:26 ` [PATCH 03/13] irqchip: Add a driver for the Microsemi Ocelot controller Alexandre Belloni @ 2017-11-28 15:26 ` Alexandre Belloni 2017-12-01 1:16 ` Rob Herring 2017-11-28 15:26 ` [PATCH 05/13] pinctrl: Add Microsemi Ocelot SoC driver Alexandre Belloni ` (8 subsequent siblings) 12 siblings, 1 reply; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 15:26 UTC (permalink / raw) To: Ralf Baechle Cc: linux-mips, linux-kernel, Alexandre Belloni, Rob Herring, devicetree, linux-gpio Add the documentation for the Microsemi Ocelot pinmuxing and gpio controller. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org To: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org .../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt new file mode 100644 index 000000000000..24a210e0c59a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -0,0 +1,39 @@ +Microsemi Ocelot pin controller Device Tree Bindings +---------------------------------------------------- + +Required properties: + - compatible : Should be "mscc,ocelot-pinctrl" + - reg : Address and length of the register set for the device + - gpio-controller : Indicates this device is a GPIO controller + - #gpio-cells : Must be 2. + The first cell is the pin number and the + second cell specifies GPIO flags, as defined in + <dt-bindings/gpio/gpio.h>. + - gpio-ranges : Range of pins managed by the GPIO controller. + + +The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin +configuration documented in pinctrl-bindings.txt. + +The following generic properties are supported: + - function + - pins + +Example: + gpio: pinctrl@71070034 { + compatible = "mscc,ocelot-pinctrl"; + reg = <0x71070034 0x28>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + + uart_pins: uart-pins { + pins = "GPIO_6", "GPIO_7"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_12", "GPIO_13"; + function = "uart2"; + }; + }; -- 2.15.0 ^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH 04/13] dt-bindings: pinctrl: Add bindings for Microsemi Ocelot 2017-11-28 15:26 ` [PATCH 04/13] dt-bindings: pinctrl: Add bindings for Microsemi Ocelot Alexandre Belloni @ 2017-12-01 1:16 ` Rob Herring 0 siblings, 0 replies; 31+ messages in thread From: Rob Herring @ 2017-12-01 1:16 UTC (permalink / raw) To: Alexandre Belloni Cc: Ralf Baechle, linux-mips, linux-kernel, devicetree, linux-gpio On Tue, Nov 28, 2017 at 04:26:34PM +0100, Alexandre Belloni wrote: > Add the documentation for the Microsemi Ocelot pinmuxing and gpio > controller. > > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > --- > Cc: Rob Herring <robh+dt@kernel.org> > Cc: devicetree@vger.kernel.org > To: Linus Walleij <linus.walleij@linaro.org> > Cc: linux-gpio@vger.kernel.org > > .../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 39 ++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 05/13] pinctrl: Add Microsemi Ocelot SoC driver 2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni ` (3 preceding siblings ...) 2017-11-28 15:26 ` [PATCH 04/13] dt-bindings: pinctrl: Add bindings for Microsemi Ocelot Alexandre Belloni @ 2017-11-28 15:26 ` Alexandre Belloni 2017-11-28 15:26 ` [PATCH 06/13] dt-bindings: power: reset: Document ocelot-reset binding Alexandre Belloni ` (7 subsequent siblings) 12 siblings, 0 replies; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 15:26 UTC (permalink / raw) To: Ralf Baechle; +Cc: linux-mips, linux-kernel, Alexandre Belloni, linux-gpio The Microsemi Ocelot SoC has a few pins that can be used as GPIOs or take multiple other functions. Add a driver for the pinmuxing and the GPIOs. There is currently no support for interrupts. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- To: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org drivers/pinctrl/Kconfig | 10 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-ocelot.c | 505 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 516 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-ocelot.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 4571cc098b76..99c36baedbad 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -343,6 +343,16 @@ config PINCTRL_RK805 help This selects the pinctrl driver for RK805. +config PINCTRL_OCELOT + bool "Pinctrl driver for the Microsemi Ocelot SoCs" + default y + depends on OF + depends on MSCC_OCELOT || COMPILE_TEST + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select REGMAP_MMIO + source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" source "drivers/pinctrl/berlin/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d0d4844f8022..b1cae074a949 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o +obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-y += bcm/ diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c new file mode 100644 index 000000000000..677e172bb945 --- /dev/null +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -0,0 +1,505 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Microsemi SoCs pinctrl driver + * + * Author: <alexandre.belloni@free-electrons.com> + * License: Dual MIT/GPL + * Copyright (c) 2017 Microsemi Corporation + */ + +#include <linux/compiler.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +#include "core.h" +#include "pinconf.h" +#include "pinmux.h" + +#define OCELOT_GPIO_OUT_SET 0x0 +#define OCELOT_GPIO_OUT_CLR 0x4 +#define OCELOT_GPIO_OUT 0x8 +#define OCELOT_GPIO_IN 0xc +#define OCELOT_GPIO_OE 0x10 +#define OCELOT_GPIO_INTR 0x14 +#define OCELOT_GPIO_INTR_ENA 0x18 +#define OCELOT_GPIO_INTR_IDENT 0x1c +#define OCELOT_GPIO_ALT0 0x20 +#define OCELOT_GPIO_ALT1 0x24 +#define OCELOT_GPIO_SD_MAP 0x28 + +#define OCELOT_PINS 22 +#define OCELOT_FUNC_PER_PIN 4 + +enum { + FUNC_NONE, + FUNC_GPIO, + FUNC_IRQ0_IN, + FUNC_IRQ0_OUT, + FUNC_IRQ1_IN, + FUNC_IRQ1_OUT, + FUNC_MIIM1, + FUNC_PCI_WAKE, + FUNC_PTP0, + FUNC_PTP1, + FUNC_PTP2, + FUNC_PTP3, + FUNC_PWM, + FUNC_RECO_CLK0, + FUNC_RECO_CLK1, + FUNC_SFP0, + FUNC_SFP1, + FUNC_SFP2, + FUNC_SFP3, + FUNC_SFP4, + FUNC_SFP5, + FUNC_SG0, + FUNC_SI, + FUNC_TACHO, + FUNC_TWI, + FUNC_TWI_SCL_M, + FUNC_UART, + FUNC_UART2, + FUNC_MAX +}; + +static const char *const ocelot_function_names[] = { + [FUNC_NONE] = "none", + [FUNC_GPIO] = "gpio", + [FUNC_IRQ0_IN] = "irq0_in", + [FUNC_IRQ0_OUT] = "irq0_out", + [FUNC_IRQ1_IN] = "irq1_in", + [FUNC_IRQ1_OUT] = "irq1_out", + [FUNC_MIIM1] = "miim1", + [FUNC_PCI_WAKE] = "pci_wake", + [FUNC_PTP0] = "ptp0", + [FUNC_PTP1] = "ptp1", + [FUNC_PTP2] = "ptp2", + [FUNC_PTP3] = "ptp3", + [FUNC_PWM] = "pwm", + [FUNC_RECO_CLK0] = "reco_clk0", + [FUNC_RECO_CLK1] = "reco_clk1", + [FUNC_SFP0] = "sfp0", + [FUNC_SFP1] = "sfp1", + [FUNC_SFP2] = "sfp2", + [FUNC_SFP3] = "sfp3", + [FUNC_SFP4] = "sfp4", + [FUNC_SFP5] = "sfp5", + [FUNC_SG0] = "sg0", + [FUNC_SI] = "si", + [FUNC_TACHO] = "tacho", + [FUNC_TWI] = "twi", + [FUNC_TWI_SCL_M] = "twi_scl_m", + [FUNC_UART] = "uart", + [FUNC_UART2] = "uart2", +}; + +struct ocelot_pmx_func { + const char **groups; + unsigned int ngroups; +}; + +struct ocelot_pin_caps { + unsigned int pin; + unsigned char functions[OCELOT_FUNC_PER_PIN]; +}; + +struct ocelot_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + struct gpio_chip gpio_chip; + struct regmap *map; + struct ocelot_pmx_func func[FUNC_MAX]; +}; + +#define OCELOT_P(p, f0, f1, f2) \ +static struct ocelot_pin_caps ocelot_pin_##p = { \ + .pin = p, \ + .functions = { \ + FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ + }, \ +} + +OCELOT_P(0, SG0, NONE, NONE); +OCELOT_P(1, SG0, NONE, NONE); +OCELOT_P(2, SG0, NONE, NONE); +OCELOT_P(3, SG0, NONE, NONE); +OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI); +OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); +OCELOT_P(6, UART, TWI_SCL_M, NONE); +OCELOT_P(7, UART, TWI_SCL_M, NONE); +OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); +OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); +OCELOT_P(10, PTP2, TWI_SCL_M, SFP0); +OCELOT_P(11, PTP3, TWI_SCL_M, SFP1); +OCELOT_P(12, UART2, TWI_SCL_M, SFP2); +OCELOT_P(13, UART2, TWI_SCL_M, SFP3); +OCELOT_P(14, MIIM1, TWI_SCL_M, SFP4); +OCELOT_P(15, MIIM1, TWI_SCL_M, SFP5); +OCELOT_P(16, TWI, NONE, SI); +OCELOT_P(17, TWI, TWI_SCL_M, SI); +OCELOT_P(18, PTP0, TWI_SCL_M, NONE); +OCELOT_P(19, PTP1, TWI_SCL_M, NONE); +OCELOT_P(20, RECO_CLK0, TACHO, NONE); +OCELOT_P(21, RECO_CLK1, PWM, NONE); + +#define OCELOT_PIN(n) { \ + .number = n, \ + .name = "GPIO_"#n, \ + .drv_data = &ocelot_pin_##n \ +} + +static const struct pinctrl_pin_desc ocelot_pins[] = { + OCELOT_PIN(0), + OCELOT_PIN(1), + OCELOT_PIN(2), + OCELOT_PIN(3), + OCELOT_PIN(4), + OCELOT_PIN(5), + OCELOT_PIN(6), + OCELOT_PIN(7), + OCELOT_PIN(8), + OCELOT_PIN(9), + OCELOT_PIN(10), + OCELOT_PIN(11), + OCELOT_PIN(12), + OCELOT_PIN(13), + OCELOT_PIN(14), + OCELOT_PIN(15), + OCELOT_PIN(16), + OCELOT_PIN(17), + OCELOT_PIN(18), + OCELOT_PIN(19), + OCELOT_PIN(20), + OCELOT_PIN(21), +}; + +static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(ocelot_function_names); +} + +static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + return ocelot_function_names[function]; +} + +static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char *const **groups, + unsigned *const num_groups) +{ + struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + *groups = info->func[function].groups; + *num_groups = info->func[function].ngroups; + + return 0; +} + +static int ocelot_pin_function_idx(unsigned int pin, unsigned int function) +{ + struct ocelot_pin_caps *p = ocelot_pins[pin].drv_data; + int i; + + for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { + if (function == p->functions[i]) + return i; + } + + return -1; +} + +static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int selector, unsigned int group) +{ + struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct ocelot_pin_caps *pin = ocelot_pins[group].drv_data; + int f; + + f = ocelot_pin_function_idx(group, selector); + if (f < 0) + return -EINVAL; + + regmap_update_bits(info->map, OCELOT_GPIO_ALT0, BIT(pin->pin), + f << pin->pin); + regmap_update_bits(info->map, OCELOT_GPIO_ALT1, BIT(pin->pin), + f << (pin->pin - 1)); + + return 0; +} + +static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin, bool input) +{ + struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + regmap_update_bits(info->map, OCELOT_GPIO_OE, BIT(pin), + input ? BIT(pin) : 0); + + return 0; +} + +static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + regmap_update_bits(info->map, OCELOT_GPIO_ALT0, BIT(offset), 0); + regmap_update_bits(info->map, OCELOT_GPIO_ALT1, BIT(offset), 0); + + return 0; +} + +static const struct pinmux_ops ocelot_pmx_ops = { + .get_functions_count = ocelot_get_functions_count, + .get_function_name = ocelot_get_function_name, + .get_function_groups = ocelot_get_function_groups, + .set_mux = ocelot_pinmux_set_mux, + .gpio_set_direction = ocelot_gpio_set_direction, + .gpio_request_enable = ocelot_gpio_request_enable, +}; + +static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(ocelot_pins); +} + +static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + return ocelot_pins[group].name; +} + +static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) +{ + *pins = &ocelot_pins[group].number; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops ocelot_pctl_ops = { + .get_groups_count = ocelot_pctl_get_groups_count, + .get_group_name = ocelot_pctl_get_group_name, + .get_group_pins = ocelot_pctl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +static struct pinctrl_desc ocelot_desc = { + .name = "ocelot-pinctrl", + .pins = ocelot_pins, + .npins = ARRAY_SIZE(ocelot_pins), + .pctlops = &ocelot_pctl_ops, + .pmxops = &ocelot_pmx_ops, + .owner = THIS_MODULE, +}; + +static int ocelot_create_group_func_map(struct device *dev, + struct ocelot_pinctrl *info) +{ + u16 pins[ARRAY_SIZE(ocelot_pins)]; + int f, npins, i; + + for (f = 0; f < FUNC_MAX; f++) { + for (npins = 0, i = 0; i < ARRAY_SIZE(ocelot_pins); i++) { + if (ocelot_pin_function_idx(i, f) >= 0) + pins[npins++] = i; + } + + info->func[f].ngroups = npins; + info->func[f].groups = devm_kzalloc(dev, npins * + sizeof(char *), + GFP_KERNEL); + if (!info->func[f].groups) + return -ENOMEM; + + for (i = 0; i < npins; i++) + info->func[f].groups[i] = ocelot_pins[pins[i]].name; + } + + return 0; +} + +static int ocelot_pinctrl_register(struct platform_device *pdev, + struct ocelot_pinctrl *info) +{ + int ret; + + ret = ocelot_create_group_func_map(&pdev->dev, info); + if (ret) { + dev_err(&pdev->dev, "Unable to create group func map.\n"); + return ret; + } + + info->pctl = devm_pinctrl_register(&pdev->dev, &ocelot_desc, info); + if (IS_ERR(info->pctl)) { + dev_err(&pdev->dev, "Failed to register pinctrl\n"); + return PTR_ERR(info->pctl); + } + + return 0; +} + +static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct ocelot_pinctrl *info = gpiochip_get_data(chip); + unsigned int val; + + regmap_read(info->map, OCELOT_GPIO_IN, &val); + + return !!(val & BIT(offset)); +} + +static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct ocelot_pinctrl *info = gpiochip_get_data(chip); + + if (value) + regmap_write(info->map, OCELOT_GPIO_OUT_SET, BIT(offset)); + else + regmap_write(info->map, OCELOT_GPIO_OUT_CLR, BIT(offset)); +} + +static int ocelot_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + struct ocelot_pinctrl *info = gpiochip_get_data(chip); + unsigned int val; + + regmap_read(info->map, OCELOT_GPIO_OE, &val); + + return !(val & BIT(offset)); +} + +static int ocelot_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct ocelot_pinctrl *info = gpiochip_get_data(chip); + + return regmap_update_bits(info->map, OCELOT_GPIO_OE, BIT(offset), 0); +} + +static int ocelot_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct ocelot_pinctrl *info = gpiochip_get_data(chip); + unsigned int pin = BIT(offset); + + if (value) + regmap_write(info->map, OCELOT_GPIO_OUT_SET, pin); + else + regmap_write(info->map, OCELOT_GPIO_OUT_CLR, pin); + + return regmap_update_bits(info->map, OCELOT_GPIO_OE, pin, pin); +} + +static const struct gpio_chip ocelot_gpiolib_chip = { + .request = gpiochip_generic_request, + .free = gpiochip_generic_free, + .set = ocelot_gpio_set, + .get = ocelot_gpio_get, + .get_direction = ocelot_gpio_get_direction, + .direction_input = ocelot_gpio_direction_input, + .direction_output = ocelot_gpio_direction_output, + .owner = THIS_MODULE, +}; + +static int ocelot_gpiochip_register(struct platform_device *pdev, + struct ocelot_pinctrl *info) +{ + struct gpio_chip *gc; + int ret; + + info->gpio_chip = ocelot_gpiolib_chip; + + gc = &info->gpio_chip; + gc->ngpio = OCELOT_PINS; + gc->parent = &pdev->dev; + gc->base = 0; + gc->of_node = info->dev->of_node; + gc->label = "ocelot-gpio"; + + ret = devm_gpiochip_add_data(&pdev->dev, gc, info); + if (ret) + return ret; + //TODO irqchip + + return 0; +} + +static const struct regmap_config ocelot_pinctrl_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static const struct of_device_id ocelot_pinctrl_of_match[] = { + { .compatible = "mscc,ocelot-pinctrl" }, + {}, +}; + +int ocelot_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ocelot_pinctrl *info; + void __iomem *base; + int ret; + + info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + base = devm_ioremap_resource(dev, + platform_get_resource(pdev, IORESOURCE_MEM, 0)); + if (IS_ERR(base)) { + dev_err(dev, "Failed to ioremap registers\n"); + return PTR_ERR(base); + } + + info->map = devm_regmap_init_mmio(dev, base, + &ocelot_pinctrl_regmap_config); + if (IS_ERR(info->map)) { + dev_err(dev, "Failed to create regmap\n"); + return PTR_ERR(info->map); + } + dev_set_drvdata(dev, info->map); + info->dev = dev; + + ret = ocelot_pinctrl_register(pdev, info); + if (ret) + return ret; + + ret = ocelot_gpiochip_register(pdev, info); + if (ret) + return ret; + + return 0; +} + +static struct platform_driver ocelot_pinctrl_driver = { + .driver = { + .name = "pinctrl-ocelot", + .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), + .suppress_bind_attrs = true, + }, + .probe = ocelot_pinctrl_probe, +}; +builtin_platform_driver(ocelot_pinctrl_driver); -- 2.15.0 ^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 06/13] dt-bindings: power: reset: Document ocelot-reset binding 2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni ` (4 preceding siblings ...) 2017-11-28 15:26 ` [PATCH 05/13] pinctrl: Add Microsemi Ocelot SoC driver Alexandre Belloni @ 2017-11-28 15:26 ` Alexandre Belloni 2017-12-01 1:54 ` Rob Herring 2017-11-28 15:26 ` [PATCH 07/13] power: reset: Add a driver for the Microsemi Ocelot reset Alexandre Belloni ` (6 subsequent siblings) 12 siblings, 1 reply; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 15:26 UTC (permalink / raw) To: Ralf Baechle Cc: linux-mips, linux-kernel, Alexandre Belloni, Rob Herring, devicetree, linux-pm Add binding documentation for the Microsemi Ocelot reset block. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org To: Sebastian Reichel <sre@kernel.org> Cc: linux-pm@vger.kernel.org .../bindings/power/reset/ocelot-reset.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt new file mode 100644 index 000000000000..2d3f2c21fadd --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -0,0 +1,24 @@ +Microsemi Ocelot reset driver + +The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the +SoC MIPS core. + +Required Properties: + - compatible: "mscc,ocelot-chip-reset" + - mscc,cpucontrol: phandle to the CPU system control syscon block + +Example: + cpu_ctrl: syscon@70000000 { + compatible = "syscon"; + reg = <0x70000000 0x2c>; + }; + + syscon@71070000 { + compatible = "simple-mfd", "syscon"; + reg = <0x71070000 0x1c>; + + reset { + compatible = "mscc,ocelot-chip-reset"; + mscc,cpucontrol = <&cpu_ctrl>; + }; + }; -- 2.15.0 ^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH 06/13] dt-bindings: power: reset: Document ocelot-reset binding 2017-11-28 15:26 ` [PATCH 06/13] dt-bindings: power: reset: Document ocelot-reset binding Alexandre Belloni @ 2017-12-01 1:54 ` Rob Herring 0 siblings, 0 replies; 31+ messages in thread From: Rob Herring @ 2017-12-01 1:54 UTC (permalink / raw) To: Alexandre Belloni Cc: Ralf Baechle, linux-mips, linux-kernel, devicetree, linux-pm On Tue, Nov 28, 2017 at 04:26:36PM +0100, Alexandre Belloni wrote: > Add binding documentation for the Microsemi Ocelot reset block. > > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > --- > Cc: Rob Herring <robh+dt@kernel.org> > Cc: devicetree@vger.kernel.org > To: Sebastian Reichel <sre@kernel.org> > Cc: linux-pm@vger.kernel.org > > .../bindings/power/reset/ocelot-reset.txt | 24 ++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt > > diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt > new file mode 100644 > index 000000000000..2d3f2c21fadd > --- /dev/null > +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt > @@ -0,0 +1,24 @@ > +Microsemi Ocelot reset driver Bindings are not drivers. > + > +The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the > +SoC MIPS core. > + > +Required Properties: > + - compatible: "mscc,ocelot-chip-reset" > + - mscc,cpucontrol: phandle to the CPU system control syscon block > + > +Example: > + cpu_ctrl: syscon@70000000 { > + compatible = "syscon"; syscon alone is not valid. > + reg = <0x70000000 0x2c>; > + }; > + > + syscon@71070000 { > + compatible = "simple-mfd", "syscon"; SoC specific compatible? > + reg = <0x71070000 0x1c>; > + > + reset { > + compatible = "mscc,ocelot-chip-reset"; > + mscc,cpucontrol = <&cpu_ctrl>; This looks strange. A syscon pointing to another syscon? Doesn't look like you even need this node, but hard to know if you don't document the parent node completely (i.e. what are all the functions in this syscon). > + }; > + }; > -- > 2.15.0 > ^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 07/13] power: reset: Add a driver for the Microsemi Ocelot reset 2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni ` (5 preceding siblings ...) 2017-11-28 15:26 ` [PATCH 06/13] dt-bindings: power: reset: Document ocelot-reset binding Alexandre Belloni @ 2017-11-28 15:26 ` Alexandre Belloni 2017-11-28 15:26 ` [PATCH 08/13] dt-bindings: mips: Add bindings for Microsemi SoCs Alexandre Belloni ` (5 subsequent siblings) 12 siblings, 0 replies; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 15:26 UTC (permalink / raw) To: Ralf Baechle; +Cc: linux-mips, linux-kernel, Alexandre Belloni, linux-pm The Microsemi Ocelot SoC has a register allowing to reset the MIPS core. Unfortunately, the syscon-reboot driver can't be used directly (but almost) as the reset control may be disabled using another register. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- To: Sebastian Reichel <sre@kernel.org> Cc: linux-pm@vger.kernel.org drivers/power/reset/Kconfig | 7 +++ drivers/power/reset/Makefile | 1 + drivers/power/reset/ocelot-reset.c | 87 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) create mode 100644 drivers/power/reset/ocelot-reset.c diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index ca0de1a78e85..2372f8e1040d 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -113,6 +113,13 @@ config POWER_RESET_MSM help Power off and restart support for Qualcomm boards. +config POWER_RESET_OCELOT_RESET + bool "Microsemi Ocelot reset driver" + depends on MSCC_OCELOT || COMPILE_TEST + select MFD_SYSCON + help + This driver supports restart for Microsemi Ocelot SoC. + config POWER_RESET_PIIX4_POWEROFF tristate "Intel PIIX4 power-off driver" depends on PCI diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile index aeb65edb17b7..df9d92291c67 100644 --- a/drivers/power/reset/Makefile +++ b/drivers/power/reset/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_POWER_RESET_GPIO_RESTART) += gpio-restart.o obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o obj-$(CONFIG_POWER_RESET_IMX) += imx-snvs-poweroff.o obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o +obj-$(CONFIG_POWER_RESET_OCELOT_RESET) += ocelot-reset.o obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c new file mode 100644 index 000000000000..d27e3d51f6a4 --- /dev/null +++ b/drivers/power/reset/ocelot-reset.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Microsemi MIPS SoC reset driver + * + * License: Dual MIT/GPL + * Copyright (c) 2017 Microsemi Corporation + */ +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/notifier.h> +#include <linux/mfd/syscon.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/reboot.h> +#include <linux/regmap.h> + +struct ocelot_reset_context { + struct regmap *chip_regs; + struct regmap *cpu_ctrl; + struct notifier_block restart_handler; +}; + +#define ICPU_CFG_CPU_SYSTEM_CTRL_RESET 0x20 +#define CORE_RST_PROTECT BIT(2) + +#define CHIP_REGS_SOFT_RST 0x8 +#define SOFT_CHIP_RST BIT(0) + +static int ocelot_restart_handle(struct notifier_block *this, + unsigned long mode, void *cmd) +{ + struct ocelot_reset_context *ctx = container_of(this, struct + ocelot_reset_context, + restart_handler); + + /* Make sure the core is not protected from reset */ + regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_RESET, + CORE_RST_PROTECT, 0); + + regmap_write(ctx->chip_regs, CHIP_REGS_SOFT_RST, SOFT_CHIP_RST); + + pr_emerg("Unable to restart system\n"); + return NOTIFY_DONE; +} + +static int ocelot_reset_probe(struct platform_device *pdev) +{ + struct ocelot_reset_context *ctx; + struct device *dev = &pdev->dev; + int err; + + ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->chip_regs = syscon_node_to_regmap(of_get_parent(dev->of_node)); + if (IS_ERR(ctx->chip_regs)) + return PTR_ERR(ctx->chip_regs); + + ctx->cpu_ctrl = syscon_regmap_lookup_by_phandle(dev->of_node, + "mscc,cpucontrol"); + if (IS_ERR(ctx->cpu_ctrl)) + return PTR_ERR(ctx->cpu_ctrl); + + ctx->restart_handler.notifier_call = ocelot_restart_handle; + ctx->restart_handler.priority = 192; + err = register_restart_handler(&ctx->restart_handler); + if (err) + dev_err(dev, "can't register restart notifier (err=%d)\n", err); + + return err; +} + +static const struct of_device_id ocelot_reset_of_match[] = { + { .compatible = "mscc,ocelot-chip-reset" }, + {} +}; + +static struct platform_driver ocelot_reset_driver = { + .probe = ocelot_reset_probe, + .driver = { + .name = "ocelot-chip-reset", + .of_match_table = ocelot_reset_of_match, + }, +}; +builtin_platform_driver(ocelot_reset_driver); -- 2.15.0 ^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 08/13] dt-bindings: mips: Add bindings for Microsemi SoCs 2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni ` (6 preceding siblings ...) 2017-11-28 15:26 ` [PATCH 07/13] power: reset: Add a driver for the Microsemi Ocelot reset Alexandre Belloni @ 2017-11-28 15:26 ` Alexandre Belloni 2017-11-28 19:14 ` Florian Fainelli 2017-11-28 15:26 ` [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs Alexandre Belloni ` (4 subsequent siblings) 12 siblings, 1 reply; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 15:26 UTC (permalink / raw) To: Ralf Baechle Cc: linux-mips, linux-kernel, Alexandre Belloni, Rob Herring, devicetree Add bindings for Microsemi SoCs. Currently only Ocelot is supported. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Documentation/devicetree/bindings/mips/mscc.txt | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt new file mode 100644 index 000000000000..2c52e76b7142 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/mscc.txt @@ -0,0 +1,6 @@ +* Microsemi MIPS CPUs + +Required properties: +- compatible: "brcm,ocelot" + +- mips-hpt-frequency: CPU counter frequency. -- 2.15.0 ^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH 08/13] dt-bindings: mips: Add bindings for Microsemi SoCs 2017-11-28 15:26 ` [PATCH 08/13] dt-bindings: mips: Add bindings for Microsemi SoCs Alexandre Belloni @ 2017-11-28 19:14 ` Florian Fainelli 0 siblings, 0 replies; 31+ messages in thread From: Florian Fainelli @ 2017-11-28 19:14 UTC (permalink / raw) To: Alexandre Belloni, Ralf Baechle Cc: linux-mips, linux-kernel, Rob Herring, devicetree On 11/28/2017 07:26 AM, Alexandre Belloni wrote: > Add bindings for Microsemi SoCs. Currently only Ocelot is supported. > > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > --- > Cc: Rob Herring <robh+dt@kernel.org> > Cc: devicetree@vger.kernel.org > > Documentation/devicetree/bindings/mips/mscc.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt > > diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt > new file mode 100644 > index 000000000000..2c52e76b7142 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mips/mscc.txt > @@ -0,0 +1,6 @@ > +* Microsemi MIPS CPUs > + > +Required properties: > +- compatible: "brcm,ocelot" You probably intended to use mscc,ocelot here, right? -- Florian ^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs 2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni ` (7 preceding siblings ...) 2017-11-28 15:26 ` [PATCH 08/13] dt-bindings: mips: Add bindings for Microsemi SoCs Alexandre Belloni @ 2017-11-28 15:26 ` Alexandre Belloni 2017-11-28 16:01 ` James Hogan 2017-11-28 15:26 ` [PATCH 10/13] MIPS: mscc: add ocelot dtsi Alexandre Belloni ` (3 subsequent siblings) 12 siblings, 1 reply; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 15:26 UTC (permalink / raw) To: Ralf Baechle; +Cc: linux-mips, linux-kernel, Alexandre Belloni Introduce support for the MIPS based Microsemi Ocelot SoCs. As the plan is to have all SoCs supported only using device tree, the mach directory is simply called mscc. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 24 ++++++++++ arch/mips/mscc/Makefile | 11 +++++ arch/mips/mscc/Platform | 12 +++++ arch/mips/mscc/setup.c | 106 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 154 insertions(+) create mode 100644 arch/mips/mscc/Makefile create mode 100644 arch/mips/mscc/Platform create mode 100644 arch/mips/mscc/setup.c diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index ac7ad54f984f..b3b2f8dc91db 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -18,6 +18,7 @@ platforms += lantiq platforms += lasat platforms += loongson32 platforms += loongson64 +platforms += mscc platforms += mti-malta platforms += netlogic platforms += paravirt diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 350a990fc719..a9db028a0338 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -527,6 +527,30 @@ config MIPS_MALTA This enables support for the MIPS Technologies Malta evaluation board. +config MSCC_OCELOT + bool "Microsemi Ocelot architecture" + select BOOT_RAW + select CEVT_R4K + select CSRC_R4K + select IRQ_MIPS_CPU + select DMA_NONCOHERENT + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_HAS_EARLY_PRINTK + select USE_GENERIC_EARLY_PRINTK_8250 + select MSCC_OCELOT_IRQ + select PINCTRL + select GPIOLIB + select COMMON_CLK + select USE_OF + select BUILTIN_DTB + select LIBFDT + help + This enables support for the Microsemi Ocelot architecture. + It builds a generic DT-based kernel image. + config MACH_PIC32 bool "Microchip PIC32 Family" help diff --git a/arch/mips/mscc/Makefile b/arch/mips/mscc/Makefile new file mode 100644 index 000000000000..c96b13546730 --- /dev/null +++ b/arch/mips/mscc/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: (GPL-2.0 OR MIT) +# +# Microsemi MIPS SoC support +# +# License: Dual MIT/GPL +# Copyright (c) 2017 Microsemi Corporation + +# +# Makefile for the Microsemi MIPS SoCs +# +obj-y := setup.o diff --git a/arch/mips/mscc/Platform b/arch/mips/mscc/Platform new file mode 100644 index 000000000000..9ae874c8f136 --- /dev/null +++ b/arch/mips/mscc/Platform @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: (GPL-2.0 OR MIT) +# +# Microsemi MIPS SoC support +# +# License: Dual MIT/GPL +# Copyright (c) 2017 Microsemi Corporation + +# +# Microsemi Ocelot board(s) +# +platform-$(CONFIG_MSCC_OCELOT) += mscc/ +load-$(CONFIG_MSCC_OCELOT) += 0x80100000 diff --git a/arch/mips/mscc/setup.c b/arch/mips/mscc/setup.c new file mode 100644 index 000000000000..77803edd7bfd --- /dev/null +++ b/arch/mips/mscc/setup.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Microsemi MIPS SoC support + * + * License: Dual MIT/GPL + * Copyright (c) 2017 Microsemi Corporation + */ +#include <linux/delay.h> +#include <linux/export.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/irqchip.h> +#include <linux/libfdt.h> +#include <linux/of_fdt.h> +#include <linux/of_platform.h> +#include <linux/reboot.h> + +#include <asm/time.h> +#include <asm/idle.h> +#include <asm/prom.h> +#include <asm/reboot.h> + +static void __init ocelot_earlyprintk_init(void) +{ + void __iomem *uart_base; + + uart_base = ioremap_nocache(0x70100000, 0x0f); + setup_8250_early_printk_port((unsigned long)uart_base, 2, 50000); +} + +void __init prom_init(void) +{ + /* Sanity check for defunct bootloader */ + if (fw_arg0 < 10 && (fw_arg1 & 0xFFF00000) == 0x80000000) { + unsigned int prom_argc = fw_arg0; + const char **prom_argv = (const char **)fw_arg1; + + if (prom_argc > 1 && strlen(prom_argv[1]) > 0) + /* ignore all built-in args if any f/w args given */ + strcpy(arcs_cmdline, prom_argv[1]); + } +} + +void __init prom_free_prom_memory(void) +{ +} + +unsigned int get_c0_compare_int(void) +{ + return CP0_LEGACY_COMPARE_IRQ; +} + +void __init plat_time_init(void) +{ + struct device_node *np; + u32 freq; + + np = of_find_node_by_name(NULL, "cpus"); + if (!np) + panic("missing 'cpus' DT node"); + if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0) + panic("missing 'mips-hpt-frequency' property"); + of_node_put(np); + + mips_hpt_frequency = freq; +} + +void __init arch_init_irq(void) +{ + irqchip_init(); +} + +const char *get_system_type(void) +{ + return "Microsemi Ocelot"; +} + +static void __init ocelot_late_init(void) +{ + ocelot_earlyprintk_init(); +} + +extern void (*late_time_init)(void); + +void __init plat_mem_setup(void) +{ + /* This has to be done so late because ioremap needs to work */ + late_time_init = ocelot_late_init; + + __dt_setup_arch(__dtb_start); +} + +void __init device_tree_init(void) +{ + if (!initial_boot_params) + return; + + unflatten_and_copy_device_tree(); +} + +static int __init populate_machine(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + return 0; +} +arch_initcall(populate_machine); -- 2.15.0 ^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs 2017-11-28 15:26 ` [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs Alexandre Belloni @ 2017-11-28 16:01 ` James Hogan 2017-11-28 16:53 ` Alexandre Belloni 0 siblings, 1 reply; 31+ messages in thread From: James Hogan @ 2017-11-28 16:01 UTC (permalink / raw) To: Alexandre Belloni; +Cc: Ralf Baechle, linux-mips, linux-kernel [-- Attachment #1: Type: text/plain, Size: 6224 bytes --] Hi Alexandre, On Tue, Nov 28, 2017 at 04:26:39PM +0100, Alexandre Belloni wrote: > Introduce support for the MIPS based Microsemi Ocelot SoCs. > As the plan is to have all SoCs supported only using device tree, the > mach directory is simply called mscc. Nice. Have you considered adding this to the existing multiplatform "generic" platform? See for example commit b35565bb16a5 ("MIPS: generic: Add support for MIPSfpga") for the latest platform to be converted. Cheers James > > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > --- > arch/mips/Kbuild.platforms | 1 + > arch/mips/Kconfig | 24 ++++++++++ > arch/mips/mscc/Makefile | 11 +++++ > arch/mips/mscc/Platform | 12 +++++ > arch/mips/mscc/setup.c | 106 +++++++++++++++++++++++++++++++++++++++++++++ > 5 files changed, 154 insertions(+) > create mode 100644 arch/mips/mscc/Makefile > create mode 100644 arch/mips/mscc/Platform > create mode 100644 arch/mips/mscc/setup.c > > diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms > index ac7ad54f984f..b3b2f8dc91db 100644 > --- a/arch/mips/Kbuild.platforms > +++ b/arch/mips/Kbuild.platforms > @@ -18,6 +18,7 @@ platforms += lantiq > platforms += lasat > platforms += loongson32 > platforms += loongson64 > +platforms += mscc > platforms += mti-malta > platforms += netlogic > platforms += paravirt > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 350a990fc719..a9db028a0338 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -527,6 +527,30 @@ config MIPS_MALTA > This enables support for the MIPS Technologies Malta evaluation > board. > > +config MSCC_OCELOT > + bool "Microsemi Ocelot architecture" > + select BOOT_RAW > + select CEVT_R4K > + select CSRC_R4K > + select IRQ_MIPS_CPU > + select DMA_NONCOHERENT > + select SYS_HAS_CPU_MIPS32_R2 > + select SYS_SUPPORTS_32BIT_KERNEL > + select SYS_SUPPORTS_BIG_ENDIAN > + select SYS_SUPPORTS_LITTLE_ENDIAN > + select SYS_HAS_EARLY_PRINTK > + select USE_GENERIC_EARLY_PRINTK_8250 > + select MSCC_OCELOT_IRQ > + select PINCTRL > + select GPIOLIB > + select COMMON_CLK > + select USE_OF > + select BUILTIN_DTB > + select LIBFDT > + help > + This enables support for the Microsemi Ocelot architecture. > + It builds a generic DT-based kernel image. > + > config MACH_PIC32 > bool "Microchip PIC32 Family" > help > diff --git a/arch/mips/mscc/Makefile b/arch/mips/mscc/Makefile > new file mode 100644 > index 000000000000..c96b13546730 > --- /dev/null > +++ b/arch/mips/mscc/Makefile > @@ -0,0 +1,11 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR MIT) > +# > +# Microsemi MIPS SoC support > +# > +# License: Dual MIT/GPL > +# Copyright (c) 2017 Microsemi Corporation > + > +# > +# Makefile for the Microsemi MIPS SoCs > +# > +obj-y := setup.o > diff --git a/arch/mips/mscc/Platform b/arch/mips/mscc/Platform > new file mode 100644 > index 000000000000..9ae874c8f136 > --- /dev/null > +++ b/arch/mips/mscc/Platform > @@ -0,0 +1,12 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR MIT) > +# > +# Microsemi MIPS SoC support > +# > +# License: Dual MIT/GPL > +# Copyright (c) 2017 Microsemi Corporation > + > +# > +# Microsemi Ocelot board(s) > +# > +platform-$(CONFIG_MSCC_OCELOT) += mscc/ > +load-$(CONFIG_MSCC_OCELOT) += 0x80100000 > diff --git a/arch/mips/mscc/setup.c b/arch/mips/mscc/setup.c > new file mode 100644 > index 000000000000..77803edd7bfd > --- /dev/null > +++ b/arch/mips/mscc/setup.c > @@ -0,0 +1,106 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Microsemi MIPS SoC support > + * > + * License: Dual MIT/GPL > + * Copyright (c) 2017 Microsemi Corporation > + */ > +#include <linux/delay.h> > +#include <linux/export.h> > +#include <linux/init.h> > +#include <linux/irq.h> > +#include <linux/irqchip.h> > +#include <linux/libfdt.h> > +#include <linux/of_fdt.h> > +#include <linux/of_platform.h> > +#include <linux/reboot.h> > + > +#include <asm/time.h> > +#include <asm/idle.h> > +#include <asm/prom.h> > +#include <asm/reboot.h> > + > +static void __init ocelot_earlyprintk_init(void) > +{ > + void __iomem *uart_base; > + > + uart_base = ioremap_nocache(0x70100000, 0x0f); > + setup_8250_early_printk_port((unsigned long)uart_base, 2, 50000); > +} > + > +void __init prom_init(void) > +{ > + /* Sanity check for defunct bootloader */ > + if (fw_arg0 < 10 && (fw_arg1 & 0xFFF00000) == 0x80000000) { > + unsigned int prom_argc = fw_arg0; > + const char **prom_argv = (const char **)fw_arg1; > + > + if (prom_argc > 1 && strlen(prom_argv[1]) > 0) > + /* ignore all built-in args if any f/w args given */ > + strcpy(arcs_cmdline, prom_argv[1]); > + } > +} > + > +void __init prom_free_prom_memory(void) > +{ > +} > + > +unsigned int get_c0_compare_int(void) > +{ > + return CP0_LEGACY_COMPARE_IRQ; > +} > + > +void __init plat_time_init(void) > +{ > + struct device_node *np; > + u32 freq; > + > + np = of_find_node_by_name(NULL, "cpus"); > + if (!np) > + panic("missing 'cpus' DT node"); > + if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0) > + panic("missing 'mips-hpt-frequency' property"); > + of_node_put(np); > + > + mips_hpt_frequency = freq; > +} > + > +void __init arch_init_irq(void) > +{ > + irqchip_init(); > +} > + > +const char *get_system_type(void) > +{ > + return "Microsemi Ocelot"; > +} > + > +static void __init ocelot_late_init(void) > +{ > + ocelot_earlyprintk_init(); > +} > + > +extern void (*late_time_init)(void); > + > +void __init plat_mem_setup(void) > +{ > + /* This has to be done so late because ioremap needs to work */ > + late_time_init = ocelot_late_init; > + > + __dt_setup_arch(__dtb_start); > +} > + > +void __init device_tree_init(void) > +{ > + if (!initial_boot_params) > + return; > + > + unflatten_and_copy_device_tree(); > +} > + > +static int __init populate_machine(void) > +{ > + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); > + return 0; > +} > +arch_initcall(populate_machine); > -- > 2.15.0 > > [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs 2017-11-28 16:01 ` James Hogan @ 2017-11-28 16:53 ` Alexandre Belloni 2017-11-28 17:31 ` James Hogan 0 siblings, 1 reply; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 16:53 UTC (permalink / raw) To: James Hogan; +Cc: Ralf Baechle, linux-mips, linux-kernel On 28/11/2017 at 16:01:38 +0000, James Hogan wrote: > Hi Alexandre, > > On Tue, Nov 28, 2017 at 04:26:39PM +0100, Alexandre Belloni wrote: > > Introduce support for the MIPS based Microsemi Ocelot SoCs. > > As the plan is to have all SoCs supported only using device tree, the > > mach directory is simply called mscc. > > Nice. Have you considered adding this to the existing multiplatform > "generic" platform? See for example commit b35565bb16a5 ("MIPS: generic: > Add support for MIPSfpga") for the latest platform to be converted. > I didn't because we are currently booting using an old redboot with its own boot protocol and at boot, the register read by the sead3 code is completely random (it actually matched once). Do you consider that mandatory to get the platform upstream? the plan is to switch to u-boot but we will definitively need to keep supporting redboot. > Cheers > James > > > > > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > > --- > > arch/mips/Kbuild.platforms | 1 + > > arch/mips/Kconfig | 24 ++++++++++ > > arch/mips/mscc/Makefile | 11 +++++ > > arch/mips/mscc/Platform | 12 +++++ > > arch/mips/mscc/setup.c | 106 +++++++++++++++++++++++++++++++++++++++++++++ > > 5 files changed, 154 insertions(+) > > create mode 100644 arch/mips/mscc/Makefile > > create mode 100644 arch/mips/mscc/Platform > > create mode 100644 arch/mips/mscc/setup.c > > > > diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms > > index ac7ad54f984f..b3b2f8dc91db 100644 > > --- a/arch/mips/Kbuild.platforms > > +++ b/arch/mips/Kbuild.platforms > > @@ -18,6 +18,7 @@ platforms += lantiq > > platforms += lasat > > platforms += loongson32 > > platforms += loongson64 > > +platforms += mscc > > platforms += mti-malta > > platforms += netlogic > > platforms += paravirt > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > > index 350a990fc719..a9db028a0338 100644 > > --- a/arch/mips/Kconfig > > +++ b/arch/mips/Kconfig > > @@ -527,6 +527,30 @@ config MIPS_MALTA > > This enables support for the MIPS Technologies Malta evaluation > > board. > > > > +config MSCC_OCELOT > > + bool "Microsemi Ocelot architecture" > > + select BOOT_RAW > > + select CEVT_R4K > > + select CSRC_R4K > > + select IRQ_MIPS_CPU > > + select DMA_NONCOHERENT > > + select SYS_HAS_CPU_MIPS32_R2 > > + select SYS_SUPPORTS_32BIT_KERNEL > > + select SYS_SUPPORTS_BIG_ENDIAN > > + select SYS_SUPPORTS_LITTLE_ENDIAN > > + select SYS_HAS_EARLY_PRINTK > > + select USE_GENERIC_EARLY_PRINTK_8250 > > + select MSCC_OCELOT_IRQ > > + select PINCTRL > > + select GPIOLIB > > + select COMMON_CLK > > + select USE_OF > > + select BUILTIN_DTB > > + select LIBFDT > > + help > > + This enables support for the Microsemi Ocelot architecture. > > + It builds a generic DT-based kernel image. > > + > > config MACH_PIC32 > > bool "Microchip PIC32 Family" > > help > > diff --git a/arch/mips/mscc/Makefile b/arch/mips/mscc/Makefile > > new file mode 100644 > > index 000000000000..c96b13546730 > > --- /dev/null > > +++ b/arch/mips/mscc/Makefile > > @@ -0,0 +1,11 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +# > > +# Microsemi MIPS SoC support > > +# > > +# License: Dual MIT/GPL > > +# Copyright (c) 2017 Microsemi Corporation > > + > > +# > > +# Makefile for the Microsemi MIPS SoCs > > +# > > +obj-y := setup.o > > diff --git a/arch/mips/mscc/Platform b/arch/mips/mscc/Platform > > new file mode 100644 > > index 000000000000..9ae874c8f136 > > --- /dev/null > > +++ b/arch/mips/mscc/Platform > > @@ -0,0 +1,12 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +# > > +# Microsemi MIPS SoC support > > +# > > +# License: Dual MIT/GPL > > +# Copyright (c) 2017 Microsemi Corporation > > + > > +# > > +# Microsemi Ocelot board(s) > > +# > > +platform-$(CONFIG_MSCC_OCELOT) += mscc/ > > +load-$(CONFIG_MSCC_OCELOT) += 0x80100000 > > diff --git a/arch/mips/mscc/setup.c b/arch/mips/mscc/setup.c > > new file mode 100644 > > index 000000000000..77803edd7bfd > > --- /dev/null > > +++ b/arch/mips/mscc/setup.c > > @@ -0,0 +1,106 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* > > + * Microsemi MIPS SoC support > > + * > > + * License: Dual MIT/GPL > > + * Copyright (c) 2017 Microsemi Corporation > > + */ > > +#include <linux/delay.h> > > +#include <linux/export.h> > > +#include <linux/init.h> > > +#include <linux/irq.h> > > +#include <linux/irqchip.h> > > +#include <linux/libfdt.h> > > +#include <linux/of_fdt.h> > > +#include <linux/of_platform.h> > > +#include <linux/reboot.h> > > + > > +#include <asm/time.h> > > +#include <asm/idle.h> > > +#include <asm/prom.h> > > +#include <asm/reboot.h> > > + > > +static void __init ocelot_earlyprintk_init(void) > > +{ > > + void __iomem *uart_base; > > + > > + uart_base = ioremap_nocache(0x70100000, 0x0f); > > + setup_8250_early_printk_port((unsigned long)uart_base, 2, 50000); > > +} > > + > > +void __init prom_init(void) > > +{ > > + /* Sanity check for defunct bootloader */ > > + if (fw_arg0 < 10 && (fw_arg1 & 0xFFF00000) == 0x80000000) { > > + unsigned int prom_argc = fw_arg0; > > + const char **prom_argv = (const char **)fw_arg1; > > + > > + if (prom_argc > 1 && strlen(prom_argv[1]) > 0) > > + /* ignore all built-in args if any f/w args given */ > > + strcpy(arcs_cmdline, prom_argv[1]); > > + } > > +} > > + > > +void __init prom_free_prom_memory(void) > > +{ > > +} > > + > > +unsigned int get_c0_compare_int(void) > > +{ > > + return CP0_LEGACY_COMPARE_IRQ; > > +} > > + > > +void __init plat_time_init(void) > > +{ > > + struct device_node *np; > > + u32 freq; > > + > > + np = of_find_node_by_name(NULL, "cpus"); > > + if (!np) > > + panic("missing 'cpus' DT node"); > > + if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0) > > + panic("missing 'mips-hpt-frequency' property"); > > + of_node_put(np); > > + > > + mips_hpt_frequency = freq; > > +} > > + > > +void __init arch_init_irq(void) > > +{ > > + irqchip_init(); > > +} > > + > > +const char *get_system_type(void) > > +{ > > + return "Microsemi Ocelot"; > > +} > > + > > +static void __init ocelot_late_init(void) > > +{ > > + ocelot_earlyprintk_init(); > > +} > > + > > +extern void (*late_time_init)(void); > > + > > +void __init plat_mem_setup(void) > > +{ > > + /* This has to be done so late because ioremap needs to work */ > > + late_time_init = ocelot_late_init; > > + > > + __dt_setup_arch(__dtb_start); > > +} > > + > > +void __init device_tree_init(void) > > +{ > > + if (!initial_boot_params) > > + return; > > + > > + unflatten_and_copy_device_tree(); > > +} > > + > > +static int __init populate_machine(void) > > +{ > > + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); > > + return 0; > > +} > > +arch_initcall(populate_machine); > > -- > > 2.15.0 > > > > -- Alexandre Belloni, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs 2017-11-28 16:53 ` Alexandre Belloni @ 2017-11-28 17:31 ` James Hogan 2017-11-28 19:50 ` Paul Burton 0 siblings, 1 reply; 31+ messages in thread From: James Hogan @ 2017-11-28 17:31 UTC (permalink / raw) To: Alexandre Belloni; +Cc: Ralf Baechle, linux-mips, linux-kernel, Paul Burton [-- Attachment #1: Type: text/plain, Size: 1165 bytes --] On Tue, Nov 28, 2017 at 05:53:59PM +0100, Alexandre Belloni wrote: > On 28/11/2017 at 16:01:38 +0000, James Hogan wrote: > > On Tue, Nov 28, 2017 at 04:26:39PM +0100, Alexandre Belloni wrote: > > > Introduce support for the MIPS based Microsemi Ocelot SoCs. > > > As the plan is to have all SoCs supported only using device tree, the > > > mach directory is simply called mscc. > > > > Nice. Have you considered adding this to the existing multiplatform > > "generic" platform? See for example commit b35565bb16a5 ("MIPS: generic: > > Add support for MIPSfpga") for the latest platform to be converted. > > > > I didn't because we are currently booting using an old redboot with its > own boot protocol and at boot, the register read by the sead3 code is > completely random (it actually matched once). > > Do you consider that mandatory to get the platform upstream? No, however if it is practical to do so I think it might be the best way forward (even if generic+YAMON support is mutually exclusive of generic+redboot, though hopefully there is some way to avoid that). Paul on Cc, he may have thoughts on this one. Cheers James [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs 2017-11-28 17:31 ` James Hogan @ 2017-11-28 19:50 ` Paul Burton 2017-11-29 16:38 ` Alexandre Belloni 0 siblings, 1 reply; 31+ messages in thread From: Paul Burton @ 2017-11-28 19:50 UTC (permalink / raw) To: James Hogan, Alexandre Belloni; +Cc: Ralf Baechle, linux-mips, linux-kernel Hi James, Alexandre, On Tue, Nov 28, 2017 at 05:31:51PM +0000, James Hogan wrote: > On Tue, Nov 28, 2017 at 05:53:59PM +0100, Alexandre Belloni wrote: > > On 28/11/2017 at 16:01:38 +0000, James Hogan wrote: > > > On Tue, Nov 28, 2017 at 04:26:39PM +0100, Alexandre Belloni wrote: > > > > Introduce support for the MIPS based Microsemi Ocelot SoCs. > > > > As the plan is to have all SoCs supported only using device tree, the > > > > mach directory is simply called mscc. > > > > > > Nice. Have you considered adding this to the existing multiplatform > > > "generic" platform? See for example commit b35565bb16a5 ("MIPS: generic: > > > Add support for MIPSfpga") for the latest platform to be converted. > > > > > > > I didn't because we are currently booting using an old redboot with its > > own boot protocol and at boot, the register read by the sead3 code is > > completely random (it actually matched once). > > > > Do you consider that mandatory to get the platform upstream? > > No, however if it is practical to do so I think it might be the best way > forward (even if generic+YAMON support is mutually exclusive of > generic+redboot, though hopefully there is some way to avoid that). > > Paul on Cc, he may have thoughts on this one. We could certainly look at tightening the checks in the SEAD-3 code to avoid the false positive. Could you share any details of the boot protocol you're using with redboot? One option might be for the SEAD-3 code to check that the arguments the bootloader provided look "YAMON-like", so long as the 2 protocols differ sufficiently. Thanks, Paul ^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs 2017-11-28 19:50 ` Paul Burton @ 2017-11-29 16:38 ` Alexandre Belloni 2018-01-17 23:58 ` James Hogan 0 siblings, 1 reply; 31+ messages in thread From: Alexandre Belloni @ 2017-11-29 16:38 UTC (permalink / raw) To: Paul Burton; +Cc: James Hogan, Ralf Baechle, linux-mips, linux-kernel Hi Paul, On 28/11/2017 at 11:50:02 -0800, Paul Burton wrote: > On Tue, Nov 28, 2017 at 05:31:51PM +0000, James Hogan wrote: > > On Tue, Nov 28, 2017 at 05:53:59PM +0100, Alexandre Belloni wrote: > > > On 28/11/2017 at 16:01:38 +0000, James Hogan wrote: > > > > On Tue, Nov 28, 2017 at 04:26:39PM +0100, Alexandre Belloni wrote: > > > > > Introduce support for the MIPS based Microsemi Ocelot SoCs. > > > > > As the plan is to have all SoCs supported only using device tree, the > > > > > mach directory is simply called mscc. > > > > > > > > Nice. Have you considered adding this to the existing multiplatform > > > > "generic" platform? See for example commit b35565bb16a5 ("MIPS: generic: > > > > Add support for MIPSfpga") for the latest platform to be converted. > > > > > > > > > > I didn't because we are currently booting using an old redboot with its > > > own boot protocol and at boot, the register read by the sead3 code is > > > completely random (it actually matched once). > > > > > > Do you consider that mandatory to get the platform upstream? > > > > No, however if it is practical to do so I think it might be the best way > > forward (even if generic+YAMON support is mutually exclusive of > > generic+redboot, though hopefully there is some way to avoid that). > > > > Paul on Cc, he may have thoughts on this one. > > We could certainly look at tightening the checks in the SEAD-3 code to > avoid the false positive. > > Could you share any details of the boot protocol you're using with > redboot? One option might be for the SEAD-3 code to check that the > arguments the bootloader provided look "YAMON-like", so long as the 2 > protocols differ sufficiently. > I didn't look closely at the redboot code yet but it ends up with something like: - argc == fw_arg0 - argv == fw_arg1 - not sure yet what is in argv[0] - kernel commande line in argv[1] - fw_arg2 is a pointer to a structure like: struct parmblock { t_env_var memsize; }; with: typedef struct { char *name; char *val; } t_env_var; this is the size of the RAM but I'm not using it because it is in the device tree. Does that help? -- Alexandre Belloni, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs 2017-11-29 16:38 ` Alexandre Belloni @ 2018-01-17 23:58 ` James Hogan 2018-03-02 15:22 ` Alexandre Belloni 0 siblings, 1 reply; 31+ messages in thread From: James Hogan @ 2018-01-17 23:58 UTC (permalink / raw) To: Alexandre Belloni; +Cc: Paul Burton, Ralf Baechle, linux-mips, linux-kernel [-- Attachment #1: Type: text/plain, Size: 5043 bytes --] On Wed, Nov 29, 2017 at 05:38:19PM +0100, Alexandre Belloni wrote: > Hi Paul, > > On 28/11/2017 at 11:50:02 -0800, Paul Burton wrote: > > On Tue, Nov 28, 2017 at 05:31:51PM +0000, James Hogan wrote: > > > On Tue, Nov 28, 2017 at 05:53:59PM +0100, Alexandre Belloni wrote: > > > > On 28/11/2017 at 16:01:38 +0000, James Hogan wrote: > > > > > On Tue, Nov 28, 2017 at 04:26:39PM +0100, Alexandre Belloni wrote: > > > > > > Introduce support for the MIPS based Microsemi Ocelot SoCs. > > > > > > As the plan is to have all SoCs supported only using device tree, the > > > > > > mach directory is simply called mscc. > > > > > > > > > > Nice. Have you considered adding this to the existing multiplatform > > > > > "generic" platform? See for example commit b35565bb16a5 ("MIPS: generic: > > > > > Add support for MIPSfpga") for the latest platform to be converted. > > > > > > > > > > > > > I didn't because we are currently booting using an old redboot with its > > > > own boot protocol and at boot, the register read by the sead3 code is > > > > completely random (it actually matched once). > > > > > > > > Do you consider that mandatory to get the platform upstream? > > > > > > No, however if it is practical to do so I think it might be the best way > > > forward (even if generic+YAMON support is mutually exclusive of > > > generic+redboot, though hopefully there is some way to avoid that). > > > > > > Paul on Cc, he may have thoughts on this one. > > > > We could certainly look at tightening the checks in the SEAD-3 code to > > avoid the false positive. > > > > Could you share any details of the boot protocol you're using with > > redboot? One option might be for the SEAD-3 code to check that the > > arguments the bootloader provided look "YAMON-like", so long as the 2 > > protocols differ sufficiently. > > > > I didn't look closely at the redboot code yet but it ends up with > something like: > - argc == fw_arg0 > - argv == fw_arg1 > - not sure yet what is in argv[0] > - kernel commande line in argv[1] > - fw_arg2 is a pointer to a structure like: > struct parmblock { > t_env_var memsize; > }; > with: > typedef struct > { > char *name; > char *val; > } t_env_var; > this is the size of the RAM but I'm not using it because it is in the > device tree. > > Does that help? That basically matches what YAMON provides. I can't see a nice way to support both in the same kernel. Processor ID is no good since Malta (not yet mainline added to "generic") uses the same address for the ID, and can support a much bigger range of cores. Poking at random I/O always feels a bit risky. Some safety checked environment checking (Paul says modetty0 should always be in there for YAMON) might work. Does Ocelot have a read-only ID register with a specific value? We'd have to add prioritisation of the legacy board detection to rely on that. If all else fails, we could still make them mutually exclusive, something roughly like below would work but its a bit clumsy as all the ocelot config options would still get enabled when sead3 is enabled, even though some of the drivers may not be useful. The detection & co-existence can always be improved later. What do you think? We can't #require CONFIG_LEGACY_BOARD_SEAD3=n unfortunately since it only checks the base config, not the already merged board configs. Cheers James diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 0f20f84de53b..bfdefc013358 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -537,6 +537,10 @@ generic_defconfig: # now that the boards have been converted to use the generic kernel they are # wrappers around the generic rules above. # +.PHONY: ocelot_defconfig +ocelot_defconfig: + $(Q)$(MAKE) -f $(srctree)/Makefile 32r2el_defconfig BOARDS=ocelot + .PHONY: sead3_defconfig sead3_defconfig: $(Q)$(MAKE) -f $(srctree)/Makefile 32r2el_defconfig BOARDS=sead-3 diff --git a/arch/mips/configs/generic/board-ocelot.config b/arch/mips/configs/generic/board-ocelot.config new file mode 100644 index 000000000000..b22a4570d05c --- /dev/null +++ b/arch/mips/configs/generic/board-ocelot.config @@ -0,0 +1,3 @@ +# require CONFIG_32BIT=y + +CONFIG_LEGACY_BOARD_OCELOT=y diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig index 52e0286a1612..fac8b936c468 100644 --- a/arch/mips/generic/Kconfig +++ b/arch/mips/generic/Kconfig @@ -27,6 +27,14 @@ config LEGACY_BOARD_SEAD3 Enable this to include support for booting on MIPS SEAD-3 FPGA-based development boards, which boot using a legacy boot protocol. +comment "MSCC Ocelot doesn't work with SEAD3 enabled" + depends on LEGACY_BOARD_SEAD3 + +config LEGACY_BOARD_OCELOT + bool "Support MSCC Ocelot boards" + depends on LEGACY_BOARD_SEAD3=n + select LEGACY_BOARDS + comment "FIT/UHI Boards" config FIT_IMAGE_FDT_BOSTON [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs 2018-01-17 23:58 ` James Hogan @ 2018-03-02 15:22 ` Alexandre Belloni 0 siblings, 0 replies; 31+ messages in thread From: Alexandre Belloni @ 2018-03-02 15:22 UTC (permalink / raw) To: James Hogan; +Cc: Paul Burton, Ralf Baechle, linux-mips, linux-kernel Hi, On 17/01/2018 at 23:58:47 +0000, James Hogan wrote: > Poking at random I/O always feels a bit risky. > > Some safety checked environment checking (Paul says modetty0 should > always be in there for YAMON) might work. > > Does Ocelot have a read-only ID register with a specific value? We'd > have to add prioritisation of the legacy board detection to rely on > that. > There is an ID register at 0x71070000. > If all else fails, we could still make them mutually exclusive, > something roughly like below would work but its a bit clumsy as all the > ocelot config options would still get enabled when sead3 is enabled, > even though some of the drivers may not be useful. The detection & > co-existence can always be improved later. What do you think? > I now have something working based on what you suggested. I'm cleaning that up and I'll resubmit soon. -- Alexandre Belloni, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com ^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 10/13] MIPS: mscc: add ocelot dtsi 2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni ` (8 preceding siblings ...) 2017-11-28 15:26 ` [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs Alexandre Belloni @ 2017-11-28 15:26 ` Alexandre Belloni 2017-11-28 18:40 ` Florian Fainelli 2017-11-28 15:26 ` [PATCH 11/13] MIPS: mscc: add ocelot PCB123 device tree Alexandre Belloni ` (2 subsequent siblings) 12 siblings, 1 reply; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 15:26 UTC (permalink / raw) To: Ralf Baechle; +Cc: linux-mips, linux-kernel, Alexandre Belloni Add a device tree include file for the Microsemi Ocelot SoC. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- arch/mips/boot/dts/Makefile | 1 + arch/mips/boot/dts/mscc/Makefile | 4 ++ arch/mips/boot/dts/mscc/ocelot.dtsi | 118 ++++++++++++++++++++++++++++++++++++ 3 files changed, 123 insertions(+) create mode 100644 arch/mips/boot/dts/mscc/Makefile create mode 100644 arch/mips/boot/dts/mscc/ocelot.dtsi diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index e2c6f131c8eb..1e79cab8e269 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -4,6 +4,7 @@ subdir-y += cavium-octeon subdir-y += img subdir-y += ingenic subdir-y += lantiq +subdir-y += mscc subdir-y += mti subdir-y += netlogic subdir-y += ni diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile new file mode 100644 index 000000000000..f0a155a74e02 --- /dev/null +++ b/arch/mips/boot/dts/mscc/Makefile @@ -0,0 +1,4 @@ +obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) + +# Force kbuild to make empty built-in.o if necessary +obj- += dummy.o diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi new file mode 100644 index 000000000000..ddbb3449fa92 --- /dev/null +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2017 Microsemi Corporation + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mscc,ocelot"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + mips-hpt-frequency = <250000000>; + + cpu@0 { + compatible = "mscc,ocelot"; + device_type = "cpu"; + reg = <0>; + }; + }; + + aliases { + serial0 = &uart0; + }; + + cpuintc: interrupt-controller@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-parent = <&intc>; + + cpu_ctrl: syscon@70000000 { + compatible = "syscon"; + reg = <0x70000000 0x2c>; + }; + + intc: interrupt-controller@70000070 { + compatible = "mscc,ocelot-icpu-intr"; + reg = <0x70000070 0x70>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + uart0: serial@70100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x70100000 0x20>; + interrupts = <6>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + uart2: serial@70100800 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x70100800 0x20>; + interrupts = <7>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + chip_regs: syscon@71070000 { + compatible = "simple-mfd", "syscon"; + reg = <0x71070000 0x1c>; + + reset { + compatible = "mscc,ocelot-chip-reset"; + mscc,cpucontrol = <&cpu_ctrl>; + }; + }; + + gpio: pinctrl@71070034 { + compatible = "mscc,ocelot-pinctrl"; + reg = <0x71070034 0x28>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + + uart_pins: uart-pins { + pins = "GPIO_6", "GPIO_7"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_12", "GPIO_13"; + function = "uart2"; + }; + }; + }; +}; -- 2.15.0 ^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH 10/13] MIPS: mscc: add ocelot dtsi 2017-11-28 15:26 ` [PATCH 10/13] MIPS: mscc: add ocelot dtsi Alexandre Belloni @ 2017-11-28 18:40 ` Florian Fainelli 0 siblings, 0 replies; 31+ messages in thread From: Florian Fainelli @ 2017-11-28 18:40 UTC (permalink / raw) To: Alexandre Belloni, Ralf Baechle; +Cc: linux-mips, linux-kernel On 11/28/2017 07:26 AM, Alexandre Belloni wrote: > Add a device tree include file for the Microsemi Ocelot SoC. > > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > --- > + ahb { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; You could provide the base address and size of the bus range, such that your nodes all become relative to that base address, e.g: ranges = <0 0x70000000 0x10000>; What a strange physical address to place registers on a MIPS system though... > + > + interrupt-parent = <&intc>; > + > + cpu_ctrl: syscon@70000000 { > + compatible = "syscon"; > + reg = <0x70000000 0x2c>; > + }; Then this becomes: syscon@0 { compatible = "syscon"; reg = <0x0 0x2c>; }; etc. > + > + intc: interrupt-controller@70000070 { > + compatible = "mscc,ocelot-icpu-intr"; > + reg = <0x70000070 0x70>; > + #interrupt-cells = <1>; > + interrupt-controller; > + interrupt-parent = <&cpuintc>; > + interrupts = <2>; > + }; > + > + uart0: serial@70100000 { > + pinctrl-0 = <&uart_pins>; > + pinctrl-names = "default"; > + compatible = "ns16550a"; > + reg = <0x70100000 0x20>; > + interrupts = <6>; > + clocks = <&ahb_clk>; > + reg-io-width = <4>; > + reg-shift = <2>; > + > + status = "disabled"; > + }; > + > + uart2: serial@70100800 { > + pinctrl-0 = <&uart2_pins>; > + pinctrl-names = "default"; > + compatible = "ns16550a"; > + reg = <0x70100800 0x20>; > + interrupts = <7>; > + clocks = <&ahb_clk>; > + reg-io-width = <4>; > + reg-shift = <2>; > + > + status = "disabled"; > + }; > + > + chip_regs: syscon@71070000 { > + compatible = "simple-mfd", "syscon"; > + reg = <0x71070000 0x1c>; > + > + reset { > + compatible = "mscc,ocelot-chip-reset"; > + mscc,cpucontrol = <&cpu_ctrl>; > + }; > + }; > + > + gpio: pinctrl@71070034 { > + compatible = "mscc,ocelot-pinctrl"; > + reg = <0x71070034 0x28>; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&gpio 0 0 22>; > + > + uart_pins: uart-pins { > + pins = "GPIO_6", "GPIO_7"; > + function = "uart"; > + }; > + > + uart2_pins: uart2-pins { > + pins = "GPIO_12", "GPIO_13"; > + function = "uart2"; > + }; > + }; > + }; > +}; > -- Florian ^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 11/13] MIPS: mscc: add ocelot PCB123 device tree 2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni ` (9 preceding siblings ...) 2017-11-28 15:26 ` [PATCH 10/13] MIPS: mscc: add ocelot dtsi Alexandre Belloni @ 2017-11-28 15:26 ` Alexandre Belloni 2017-11-28 15:26 ` [PATCH 12/13] MIPS: defconfigs: add a defconfig for Microsemi SoCs Alexandre Belloni 2017-11-28 15:26 ` [PATCH 13/13] MAINTAINERS: Add entry for Microsemi MIPS SoCs Alexandre Belloni 12 siblings, 0 replies; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 15:26 UTC (permalink / raw) To: Ralf Baechle; +Cc: linux-mips, linux-kernel, Alexandre Belloni Add a device tree for the Microsemi Ocelot PCB123 evaluation board. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- arch/mips/boot/dts/mscc/Makefile | 2 ++ arch/mips/boot/dts/mscc/ocelot_pcb123.dts | 30 ++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 arch/mips/boot/dts/mscc/ocelot_pcb123.dts diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile index f0a155a74e02..09a1c4b97de2 100644 --- a/arch/mips/boot/dts/mscc/Makefile +++ b/arch/mips/boot/dts/mscc/Makefile @@ -1,3 +1,5 @@ +dtb-$(CONFIG_MSCC_OCELOT) += ocelot_pcb123.dtb + obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) # Force kbuild to make empty built-in.o if necessary diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts new file mode 100644 index 000000000000..16a67ad2901d --- /dev/null +++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2017 Microsemi Corporation + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; + +#include "ocelot.dtsi" + +/ { + compatible = "mscc,ocelot-pcb123", "mscc,ocelot"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0e000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; -- 2.15.0 ^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 12/13] MIPS: defconfigs: add a defconfig for Microsemi SoCs 2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni ` (10 preceding siblings ...) 2017-11-28 15:26 ` [PATCH 11/13] MIPS: mscc: add ocelot PCB123 device tree Alexandre Belloni @ 2017-11-28 15:26 ` Alexandre Belloni 2017-11-28 15:26 ` [PATCH 13/13] MAINTAINERS: Add entry for Microsemi MIPS SoCs Alexandre Belloni 12 siblings, 0 replies; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 15:26 UTC (permalink / raw) To: Ralf Baechle; +Cc: linux-mips, linux-kernel, Alexandre Belloni Add a defconfg that reaches userspace for Microsemi Ocelot. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- arch/mips/configs/mscc_defconfig | 84 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 arch/mips/configs/mscc_defconfig diff --git a/arch/mips/configs/mscc_defconfig b/arch/mips/configs/mscc_defconfig new file mode 100644 index 000000000000..58cf09b1ae82 --- /dev/null +++ b/arch/mips/configs/mscc_defconfig @@ -0,0 +1,84 @@ +CONFIG_MSCC_OCELOT=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_MIPS_ELF_APPENDED_DTB=y +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_SWAP is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_SHMEM is not set +CONFIG_EMBEDDED=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_PROTO_DCCP is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CT_PROTO_UDPLITE is not set +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_FILTER=y +CONFIG_VLAN_8021Q=y +CONFIG_NET_SWITCHDEV=y +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_NETDEVICES=y +CONFIG_TUN=y +CONFIG_MICROSEMI_PHY=y +# CONFIG_WLAN is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +CONFIG_N_GSM=y +CONFIG_DEVKMEM=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_DESIGNWARE=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_OCELOT_RESET=y +CONFIG_SENSORS_TMP401=y +# CONFIG_USB_SUPPORT is not set +CONFIG_UIO=y +CONFIG_UIO_PDRV_GENIRQ=y +CONFIG_OVERLAY_FS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XZ=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0 +# CONFIG_EARLY_PRINTK is not set +# CONFIG_CRYPTO_HW is not set -- 2.15.0 ^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 13/13] MAINTAINERS: Add entry for Microsemi MIPS SoCs 2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni ` (11 preceding siblings ...) 2017-11-28 15:26 ` [PATCH 12/13] MIPS: defconfigs: add a defconfig for Microsemi SoCs Alexandre Belloni @ 2017-11-28 15:26 ` Alexandre Belloni 2017-11-28 15:34 ` Joe Perches 12 siblings, 1 reply; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 15:26 UTC (permalink / raw) To: Ralf Baechle; +Cc: linux-mips, linux-kernel, Alexandre Belloni Add myself as a maintainer for the Microsemi MIPS SoCs. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index aa71ab52fd76..b9a532d4fcd7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9062,6 +9062,13 @@ S: Maintained F: drivers/usb/misc/usb251xb.c F: Documentation/devicetree/bindings/usb/usb251xb.txt +MICROSEMI MIPS SOCS +M: Alexandre Belloni <alexandre.belloni@free-electrons.com> +L: linux-mips@linux-mips.org +S: Maintained +F: arch/mips/mscc/* +F: arch/mips/boot/dts/mscc/* + MICROSEMI SMART ARRAY SMARTPQI DRIVER (smartpqi) M: Don Brace <don.brace@microsemi.com> L: esc.storagedev@microsemi.com -- 2.15.0 ^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH 13/13] MAINTAINERS: Add entry for Microsemi MIPS SoCs 2017-11-28 15:26 ` [PATCH 13/13] MAINTAINERS: Add entry for Microsemi MIPS SoCs Alexandre Belloni @ 2017-11-28 15:34 ` Joe Perches 2017-11-28 15:44 ` Alexandre Belloni 0 siblings, 1 reply; 31+ messages in thread From: Joe Perches @ 2017-11-28 15:34 UTC (permalink / raw) To: Alexandre Belloni, Ralf Baechle; +Cc: linux-mips, linux-kernel On Tue, 2017-11-28 at 16:26 +0100, Alexandre Belloni wrote: > Add myself as a maintainer for the Microsemi MIPS SoCs. [] > diff --git a/MAINTAINERS b/MAINTAINERS [] > @@ -9062,6 +9062,13 @@ S: Maintained > F: drivers/usb/misc/usb251xb.c > F: Documentation/devicetree/bindings/usb/usb251xb.txt > > +MICROSEMI MIPS SOCS > +M: Alexandre Belloni <alexandre.belloni@free-electrons.com> > +L: linux-mips@linux-mips.org > +S: Maintained > +F: arch/mips/mscc/* > +F: arch/mips/boot/dts/mscc/* Do any of these directories also contain subdirectories? This use of * means only the top level directory files are matched by this pattern. Using just a trailing / instead makes any file in any subdirectory also match. Perhaps: F: arch/mips/mscc/ F: arch/mips/boot/dts/mscc/ ^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 13/13] MAINTAINERS: Add entry for Microsemi MIPS SoCs 2017-11-28 15:34 ` Joe Perches @ 2017-11-28 15:44 ` Alexandre Belloni 0 siblings, 0 replies; 31+ messages in thread From: Alexandre Belloni @ 2017-11-28 15:44 UTC (permalink / raw) To: Joe Perches; +Cc: Ralf Baechle, linux-mips, linux-kernel On 28/11/2017 at 07:34:50 -0800, Joe Perches wrote: > On Tue, 2017-11-28 at 16:26 +0100, Alexandre Belloni wrote: > > Add myself as a maintainer for the Microsemi MIPS SoCs. > [] > > diff --git a/MAINTAINERS b/MAINTAINERS > [] > > @@ -9062,6 +9062,13 @@ S: Maintained > > F: drivers/usb/misc/usb251xb.c > > F: Documentation/devicetree/bindings/usb/usb251xb.txt > > > > +MICROSEMI MIPS SOCS > > +M: Alexandre Belloni <alexandre.belloni@free-electrons.com> > > +L: linux-mips@linux-mips.org > > +S: Maintained > > +F: arch/mips/mscc/* > > +F: arch/mips/boot/dts/mscc/* > > Do any of these directories also contain subdirectories? > > This use of * means only the top level directory files > are matched by this pattern. > > Using just a trailing / instead makes any file in any > subdirectory also match. > > Perhaps: > > F: arch/mips/mscc/ > F: arch/mips/boot/dts/mscc/ Yes but I'll change it in v2 because I need to resend as I messed up the cc list on some patches. Thanks. -- Alexandre Belloni, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2018-03-02 15:22 UTC | newest] Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni 2017-11-28 15:26 ` [PATCH 01/13] dt-bindings: Add vendor prefix for Microsemi Corporation Alexandre Belloni 2017-11-28 16:10 ` James Hogan 2017-11-28 16:22 ` Alexandre Belloni 2017-12-01 1:14 ` Rob Herring 2017-11-28 15:26 ` [PATCH 02/13] dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller Alexandre Belloni 2017-12-01 1:15 ` Rob Herring 2017-11-28 15:26 ` [PATCH 03/13] irqchip: Add a driver for the Microsemi Ocelot controller Alexandre Belloni 2017-11-28 15:26 ` [PATCH 04/13] dt-bindings: pinctrl: Add bindings for Microsemi Ocelot Alexandre Belloni 2017-12-01 1:16 ` Rob Herring 2017-11-28 15:26 ` [PATCH 05/13] pinctrl: Add Microsemi Ocelot SoC driver Alexandre Belloni 2017-11-28 15:26 ` [PATCH 06/13] dt-bindings: power: reset: Document ocelot-reset binding Alexandre Belloni 2017-12-01 1:54 ` Rob Herring 2017-11-28 15:26 ` [PATCH 07/13] power: reset: Add a driver for the Microsemi Ocelot reset Alexandre Belloni 2017-11-28 15:26 ` [PATCH 08/13] dt-bindings: mips: Add bindings for Microsemi SoCs Alexandre Belloni 2017-11-28 19:14 ` Florian Fainelli 2017-11-28 15:26 ` [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs Alexandre Belloni 2017-11-28 16:01 ` James Hogan 2017-11-28 16:53 ` Alexandre Belloni 2017-11-28 17:31 ` James Hogan 2017-11-28 19:50 ` Paul Burton 2017-11-29 16:38 ` Alexandre Belloni 2018-01-17 23:58 ` James Hogan 2018-03-02 15:22 ` Alexandre Belloni 2017-11-28 15:26 ` [PATCH 10/13] MIPS: mscc: add ocelot dtsi Alexandre Belloni 2017-11-28 18:40 ` Florian Fainelli 2017-11-28 15:26 ` [PATCH 11/13] MIPS: mscc: add ocelot PCB123 device tree Alexandre Belloni 2017-11-28 15:26 ` [PATCH 12/13] MIPS: defconfigs: add a defconfig for Microsemi SoCs Alexandre Belloni 2017-11-28 15:26 ` [PATCH 13/13] MAINTAINERS: Add entry for Microsemi MIPS SoCs Alexandre Belloni 2017-11-28 15:34 ` Joe Perches 2017-11-28 15:44 ` Alexandre Belloni
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