* [PATCH v2 01/22] clk: at91: audio-pll: fix audio pmc type
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-17 17:49 ` Stephen Boyd
2018-10-16 14:21 ` [PATCH v2 02/22] clk: at91: generated: SSCs don't have a gclk Alexandre Belloni
` (21 subsequent siblings)
22 siblings, 1 reply; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
The allocation for the audio pmc is using the size of struct clk_audio_pad
instead of struct clk_audio_pmc. This works fine because the former is
larger than the latter but it is safer to be correct.
Fixes: ("0865805d82d4 clk: at91: add audio pll clock drivers")
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
drivers/clk/at91/clk-audio-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c
index da7bafcfbe70..b3eaf654fac9 100644
--- a/drivers/clk/at91/clk-audio-pll.c
+++ b/drivers/clk/at91/clk-audio-pll.c
@@ -509,7 +509,7 @@ static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
{
- struct clk_audio_pad *apmc_ck;
+ struct clk_audio_pmc *apmc_ck;
struct clk_init_data init = {};
apmc_ck = kzalloc(sizeof(*apmc_ck), GFP_KERNEL);
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* Re: [PATCH v2 01/22] clk: at91: audio-pll: fix audio pmc type
2018-10-16 14:21 ` [PATCH v2 01/22] clk: at91: audio-pll: fix audio pmc type Alexandre Belloni
@ 2018-10-17 17:49 ` Stephen Boyd
0 siblings, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2018-10-17 17:49 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Quoting Alexandre Belloni (2018-10-16 07:21:39)
> The allocation for the audio pmc is using the size of struct clk_audio_pad
> instead of struct clk_audio_pmc. This works fine because the former is
> larger than the latter but it is safer to be correct.
>
> Fixes: ("0865805d82d4 clk: at91: add audio pll clock drivers")
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v2 02/22] clk: at91: generated: SSCs don't have a gclk
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
2018-10-16 14:21 ` [PATCH v2 01/22] clk: at91: audio-pll: fix audio pmc type Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-17 17:49 ` Stephen Boyd
2018-10-16 14:21 ` [PATCH v2 03/22] clk: at91: h32mx: separate registration from DT parsing Alexandre Belloni
` (20 subsequent siblings)
22 siblings, 1 reply; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
As the SSCs don't have gclk, don't check for their ID to allow them to set
the audio pll rate.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
drivers/clk/at91/clk-generated.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
index 33481368740e..e709a12269c0 100644
--- a/drivers/clk/at91/clk-generated.c
+++ b/drivers/clk/at91/clk-generated.c
@@ -26,8 +26,6 @@
#define GENERATED_SOURCE_MAX 6
#define GENERATED_MAX_DIV 255
-#define GCK_ID_SSC0 43
-#define GCK_ID_SSC1 44
#define GCK_ID_I2S0 54
#define GCK_ID_I2S1 55
#define GCK_ID_CLASSD 59
@@ -368,8 +366,7 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
if (of_device_is_compatible(np,
"atmel,sama5d2-clk-generated")) {
- if (gck->id == GCK_ID_SSC0 || gck->id == GCK_ID_SSC1 ||
- gck->id == GCK_ID_I2S0 || gck->id == GCK_ID_I2S1 ||
+ if (gck->id == GCK_ID_I2S0 || gck->id == GCK_ID_I2S1 ||
gck->id == GCK_ID_CLASSD)
gck->audio_pll_allowed = true;
else
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 03/22] clk: at91: h32mx: separate registration from DT parsing
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
2018-10-16 14:21 ` [PATCH v2 01/22] clk: at91: audio-pll: fix audio pmc type Alexandre Belloni
2018-10-16 14:21 ` [PATCH v2 02/22] clk: at91: generated: SSCs don't have a gclk Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-17 17:49 ` Stephen Boyd
2018-10-16 14:21 ` [PATCH v2 04/22] clk: at91: audio-pll: " Alexandre Belloni
` (19 subsequent siblings)
22 siblings, 1 reply; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Separate registration out of of_sama5d4_clk_h32mx_setup to allow other code
to use it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
drivers/clk/at91/clk-h32mx.c | 40 ++++++++++++++++++++++++------------
1 file changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c
index e0daa4a31f88..a3274648b6c0 100644
--- a/drivers/clk/at91/clk-h32mx.c
+++ b/drivers/clk/at91/clk-h32mx.c
@@ -86,25 +86,19 @@ static const struct clk_ops h32mx_ops = {
.set_rate = clk_sama5d4_h32mx_set_rate,
};
-static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
+struct clk_hw * __init
+at91_clk_register_h32mx(struct regmap *regmap, const char *name,
+ const char *parent_name)
{
struct clk_sama5d4_h32mx *h32mxclk;
struct clk_init_data init;
- const char *parent_name;
- struct regmap *regmap;
int ret;
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
h32mxclk = kzalloc(sizeof(*h32mxclk), GFP_KERNEL);
if (!h32mxclk)
- return;
-
- parent_name = of_clk_get_parent_name(np, 0);
+ return ERR_PTR(-ENOMEM);
- init.name = np->name;
+ init.name = name;
init.ops = &h32mx_ops;
init.parent_names = parent_name ? &parent_name : NULL;
init.num_parents = parent_name ? 1 : 0;
@@ -116,10 +110,30 @@ static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
ret = clk_hw_register(NULL, &h32mxclk->hw);
if (ret) {
kfree(h32mxclk);
- return;
+ return ERR_PTR(ret);
}
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, &h32mxclk->hw);
+ return &h32mxclk->hw;
+}
+
+static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ const char *name = np->name;
+ const char *parent_name;
+ struct regmap *regmap;
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ hw = at91_clk_register_h32mx(regmap, name, parent_name);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
}
CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx",
of_sama5d4_clk_h32mx_setup);
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 04/22] clk: at91: audio-pll: separate registration from DT parsing
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (2 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 03/22] clk: at91: h32mx: separate registration from DT parsing Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-17 17:49 ` Stephen Boyd
2018-10-16 14:21 ` [PATCH v2 05/22] clk: at91: generated: set audio_pll_allowed in at91_clk_register_generated() Alexandre Belloni
` (18 subsequent siblings)
22 siblings, 1 reply; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Separate registration out of of_sama5d2_clk_audio_pll*_setup to allow other
code to use it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
drivers/clk/at91/clk-audio-pll.c | 147 +++++++++++++++++++++++--------
1 file changed, 109 insertions(+), 38 deletions(-)
diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c
index b3eaf654fac9..f326023a50a3 100644
--- a/drivers/clk/at91/clk-audio-pll.c
+++ b/drivers/clk/at91/clk-audio-pll.c
@@ -444,85 +444,156 @@ static const struct clk_ops audio_pll_pmc_ops = {
.set_rate = clk_audio_pll_pmc_set_rate,
};
-static int of_sama5d2_clk_audio_pll_setup(struct device_node *np,
- struct clk_init_data *init,
- struct clk_hw *hw,
- struct regmap **clk_audio_regmap)
+struct clk_hw * __init
+at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,
+ const char *parent_name)
{
- struct regmap *regmap;
- const char *parent_names[1];
+ struct clk_audio_frac *frac_ck;
+ struct clk_init_data init = {};
int ret;
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return PTR_ERR(regmap);
+ frac_ck = kzalloc(sizeof(*frac_ck), GFP_KERNEL);
+ if (!frac_ck)
+ return ERR_PTR(-ENOMEM);
- init->name = np->name;
- of_clk_parent_fill(np, parent_names, 1);
- init->parent_names = parent_names;
- init->num_parents = 1;
+ init.name = name;
+ init.ops = &audio_pll_frac_ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ init.flags = CLK_SET_RATE_GATE;
- hw->init = init;
- *clk_audio_regmap = regmap;
+ frac_ck->hw.init = &init;
+ frac_ck->regmap = regmap;
- ret = clk_hw_register(NULL, hw);
- if (ret)
- return ret;
+ ret = clk_hw_register(NULL, &frac_ck->hw);
+ if (ret) {
+ kfree(frac_ck);
+ return ERR_PTR(ret);
+ }
- return of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+ return &frac_ck->hw;
}
static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)
{
- struct clk_audio_frac *frac_ck;
- struct clk_init_data init = {};
+ struct clk_hw *hw;
+ const char *name = np->name;
+ const char *parent_name;
+ struct regmap *regmap;
- frac_ck = kzalloc(sizeof(*frac_ck), GFP_KERNEL);
- if (!frac_ck)
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
return;
- init.ops = &audio_pll_frac_ops;
- init.flags = CLK_SET_RATE_GATE;
+ parent_name = of_clk_get_parent_name(np, 0);
- if (of_sama5d2_clk_audio_pll_setup(np, &init, &frac_ck->hw,
- &frac_ck->regmap))
- kfree(frac_ck);
+ hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
}
-static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
+struct clk_hw * __init
+at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,
+ const char *parent_name)
{
struct clk_audio_pad *apad_ck;
- struct clk_init_data init = {};
+ struct clk_init_data init;
+ int ret;
apad_ck = kzalloc(sizeof(*apad_ck), GFP_KERNEL);
if (!apad_ck)
- return;
+ return ERR_PTR(-ENOMEM);
+ init.name = name;
init.ops = &audio_pll_pad_ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
CLK_SET_RATE_PARENT;
- if (of_sama5d2_clk_audio_pll_setup(np, &init, &apad_ck->hw,
- &apad_ck->regmap))
+ apad_ck->hw.init = &init;
+ apad_ck->regmap = regmap;
+
+ ret = clk_hw_register(NULL, &apad_ck->hw);
+ if (ret) {
kfree(apad_ck);
+ return ERR_PTR(ret);
+ }
+
+ return &apad_ck->hw;
}
-static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
+static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ const char *name = np->name;
+ const char *parent_name;
+ struct regmap *regmap;
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+
+struct clk_hw * __init
+at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
+ const char *parent_name)
{
struct clk_audio_pmc *apmc_ck;
- struct clk_init_data init = {};
+ struct clk_init_data init;
+ int ret;
apmc_ck = kzalloc(sizeof(*apmc_ck), GFP_KERNEL);
if (!apmc_ck)
- return;
+ return ERR_PTR(-ENOMEM);
+ init.name = name;
init.ops = &audio_pll_pmc_ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
CLK_SET_RATE_PARENT;
- if (of_sama5d2_clk_audio_pll_setup(np, &init, &apmc_ck->hw,
- &apmc_ck->regmap))
+ apmc_ck->hw.init = &init;
+ apmc_ck->regmap = regmap;
+
+ ret = clk_hw_register(NULL, &apmc_ck->hw);
+ if (ret) {
kfree(apmc_ck);
+ return ERR_PTR(ret);
+ }
+
+ return &apmc_ck->hw;
+}
+
+static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ const char *name = np->name;
+ const char *parent_name;
+ struct regmap *regmap;
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
}
CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup,
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* Re: [PATCH v2 04/22] clk: at91: audio-pll: separate registration from DT parsing
2018-10-16 14:21 ` [PATCH v2 04/22] clk: at91: audio-pll: " Alexandre Belloni
@ 2018-10-17 17:49 ` Stephen Boyd
0 siblings, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2018-10-17 17:49 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Quoting Alexandre Belloni (2018-10-16 07:21:42)
> Separate registration out of of_sama5d2_clk_audio_pll*_setup to allow other
> code to use it.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v2 05/22] clk: at91: generated: set audio_pll_allowed in at91_clk_register_generated()
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (3 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 04/22] clk: at91: audio-pll: " Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-17 17:49 ` Stephen Boyd
2018-10-16 14:21 ` [PATCH v2 06/22] clk: at91: allow clock registration from C code Alexandre Belloni
` (17 subsequent siblings)
22 siblings, 1 reply; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Set gck->audio_pll_allowed in at91_clk_register_generated. This makes it
easier to do it from code that is not parsing device tree.
Also, this fixes an issue where the resulting clk_hw can be dereferenced
before being tested for error.
Fixes: 1a1a36d72e3d ("clk: at91: clk-generated: make gclk determine audio_pll rate")
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
drivers/clk/at91/clk-generated.c | 27 ++++++++++-----------------
1 file changed, 10 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
index e709a12269c0..6dfee6e588c4 100644
--- a/drivers/clk/at91/clk-generated.c
+++ b/drivers/clk/at91/clk-generated.c
@@ -280,7 +280,7 @@ static void clk_generated_startup(struct clk_generated *gck)
static struct clk_hw * __init
at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
const char *name, const char **parent_names,
- u8 num_parents, u8 id,
+ u8 num_parents, u8 id, bool pll_audio,
const struct clk_range *range)
{
struct clk_generated *gck;
@@ -304,6 +304,7 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
gck->regmap = regmap;
gck->lock = lock;
gck->range = *range;
+ gck->audio_pll_allowed = pll_audio;
clk_generated_startup(gck);
hw = &gck->hw;
@@ -329,7 +330,6 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
struct device_node *gcknp;
struct clk_range range = CLK_RANGE(0, 0);
struct regmap *regmap;
- struct clk_generated *gck;
num_parents = of_clk_get_parent_count(np);
if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
@@ -346,6 +346,8 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
return;
for_each_child_of_node(np, gcknp) {
+ bool pll_audio = false;
+
if (of_property_read_u32(gcknp, "reg", &id))
continue;
@@ -358,23 +360,14 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
&range);
+ if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&
+ (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||
+ id == GCK_ID_CLASSD))
+ pll_audio = true;
+
hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, name,
parent_names, num_parents,
- id, &range);
-
- gck = to_clk_generated(hw);
-
- if (of_device_is_compatible(np,
- "atmel,sama5d2-clk-generated")) {
- if (gck->id == GCK_ID_I2S0 || gck->id == GCK_ID_I2S1 ||
- gck->id == GCK_ID_CLASSD)
- gck->audio_pll_allowed = true;
- else
- gck->audio_pll_allowed = false;
- } else {
- gck->audio_pll_allowed = false;
- }
-
+ id, pll_audio, &range);
if (IS_ERR(hw))
continue;
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* Re: [PATCH v2 05/22] clk: at91: generated: set audio_pll_allowed in at91_clk_register_generated()
2018-10-16 14:21 ` [PATCH v2 05/22] clk: at91: generated: set audio_pll_allowed in at91_clk_register_generated() Alexandre Belloni
@ 2018-10-17 17:49 ` Stephen Boyd
0 siblings, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2018-10-17 17:49 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Quoting Alexandre Belloni (2018-10-16 07:21:43)
> Set gck->audio_pll_allowed in at91_clk_register_generated. This makes it
> easier to do it from code that is not parsing device tree.
>
> Also, this fixes an issue where the resulting clk_hw can be dereferenced
> before being tested for error.
>
> Fixes: 1a1a36d72e3d ("clk: at91: clk-generated: make gclk determine audio_pll rate")
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v2 06/22] clk: at91: allow clock registration from C code
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (4 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 05/22] clk: at91: generated: set audio_pll_allowed in at91_clk_register_generated() Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-17 17:49 ` Stephen Boyd
2018-10-16 14:21 ` [PATCH v2 07/22] clk: at91: add pmc_data struct and helpers Alexandre Belloni
` (16 subsequent siblings)
22 siblings, 1 reply; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Remove static keyword to allow functions to be used from other units. Also
move some struct and function declarations to pmc.h
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
drivers/clk/at91/clk-generated.c | 2 +-
drivers/clk/at91/clk-i2s-mux.c | 2 +-
drivers/clk/at91/clk-main.c | 8 +-
drivers/clk/at91/clk-master.c | 17 +---
drivers/clk/at91/clk-peripheral.c | 4 +-
drivers/clk/at91/clk-pll.c | 24 +----
drivers/clk/at91/clk-plldiv.c | 2 +-
drivers/clk/at91/clk-programmable.c | 14 +--
drivers/clk/at91/clk-slow.c | 2 +-
drivers/clk/at91/clk-smd.c | 2 +-
drivers/clk/at91/clk-system.c | 2 +-
drivers/clk/at91/clk-usb.c | 6 +-
drivers/clk/at91/clk-utmi.c | 2 +-
drivers/clk/at91/pmc.h | 142 ++++++++++++++++++++++++++++
14 files changed, 170 insertions(+), 59 deletions(-)
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
index 6dfee6e588c4..0fe4d7f04225 100644
--- a/drivers/clk/at91/clk-generated.c
+++ b/drivers/clk/at91/clk-generated.c
@@ -277,7 +277,7 @@ static void clk_generated_startup(struct clk_generated *gck)
>> AT91_PMC_PCR_GCKDIV_OFFSET;
}
-static struct clk_hw * __init
+struct clk_hw * __init
at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
const char *name, const char **parent_names,
u8 num_parents, u8 id, bool pll_audio,
diff --git a/drivers/clk/at91/clk-i2s-mux.c b/drivers/clk/at91/clk-i2s-mux.c
index f0c3c3079f04..ed9e96938589 100644
--- a/drivers/clk/at91/clk-i2s-mux.c
+++ b/drivers/clk/at91/clk-i2s-mux.c
@@ -48,7 +48,7 @@ static const struct clk_ops clk_i2s_mux_ops = {
.determine_rate = __clk_mux_determine_rate,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,
const char * const *parent_names,
unsigned int num_parents, u8 bus_id)
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
index c813c27f2e58..82184009137d 100644
--- a/drivers/clk/at91/clk-main.c
+++ b/drivers/clk/at91/clk-main.c
@@ -128,7 +128,7 @@ static const struct clk_ops main_osc_ops = {
.is_prepared = clk_main_osc_is_prepared,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91_clk_register_main_osc(struct regmap *regmap,
const char *name,
const char *parent_name,
@@ -275,7 +275,7 @@ static const struct clk_ops main_rc_osc_ops = {
.recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91_clk_register_main_rc_osc(struct regmap *regmap,
const char *name,
u32 frequency, u32 accuracy)
@@ -403,7 +403,7 @@ static const struct clk_ops rm9200_main_ops = {
.recalc_rate = clk_rm9200_main_recalc_rate,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91_clk_register_rm9200_main(struct regmap *regmap,
const char *name,
const char *parent_name)
@@ -541,7 +541,7 @@ static const struct clk_ops sam9x5_main_ops = {
.get_parent = clk_sam9x5_main_get_parent,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91_clk_register_sam9x5_main(struct regmap *regmap,
const char *name,
const char **parent_names,
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index e9cba9fc26d7..088044bb6ea2 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -24,17 +24,6 @@
#define MASTER_DIV_SHIFT 8
#define MASTER_DIV_MASK 0x3
-struct clk_master_characteristics {
- struct clk_range output;
- u32 divisors[4];
- u8 have_div3_pres;
-};
-
-struct clk_master_layout {
- u32 mask;
- u8 pres_shift;
-};
-
#define to_clk_master(hw) container_of(hw, struct clk_master, hw)
struct clk_master {
@@ -120,7 +109,7 @@ static const struct clk_ops master_ops = {
.get_parent = clk_master_get_parent,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91_clk_register_master(struct regmap *regmap,
const char *name, int num_parents,
const char **parent_names,
@@ -161,12 +150,12 @@ at91_clk_register_master(struct regmap *regmap,
}
-static const struct clk_master_layout at91rm9200_master_layout = {
+const struct clk_master_layout at91rm9200_master_layout = {
.mask = 0x31F,
.pres_shift = 2,
};
-static const struct clk_master_layout at91sam9x5_master_layout = {
+const struct clk_master_layout at91sam9x5_master_layout = {
.mask = 0x373,
.pres_shift = 4,
};
diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c
index 770118369230..cb41d06a2481 100644
--- a/drivers/clk/at91/clk-peripheral.c
+++ b/drivers/clk/at91/clk-peripheral.c
@@ -104,7 +104,7 @@ static const struct clk_ops peripheral_ops = {
.is_enabled = clk_peripheral_is_enabled,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91_clk_register_peripheral(struct regmap *regmap, const char *name,
const char *parent_name, u32 id)
{
@@ -331,7 +331,7 @@ static const struct clk_ops sam9x5_peripheral_ops = {
.set_rate = clk_sam9x5_peripheral_set_rate,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,
const char *name, const char *parent_name,
u32 id, const struct clk_range *range)
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
index 72b6091eb7b9..31fff0b9d5c2 100644
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -34,20 +34,6 @@
#define PLL_OUT_SHIFT 14
#define PLL_MAX_ID 1
-struct clk_pll_characteristics {
- struct clk_range input;
- int num_output;
- struct clk_range *output;
- u16 *icpll;
- u8 *out;
-};
-
-struct clk_pll_layout {
- u32 pllr_mask;
- u16 mul_mask;
- u8 mul_shift;
-};
-
#define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
struct clk_pll {
@@ -285,7 +271,7 @@ static const struct clk_ops pll_ops = {
.set_rate = clk_pll_set_rate,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91_clk_register_pll(struct regmap *regmap, const char *name,
const char *parent_name, u8 id,
const struct clk_pll_layout *layout,
@@ -331,25 +317,25 @@ at91_clk_register_pll(struct regmap *regmap, const char *name,
}
-static const struct clk_pll_layout at91rm9200_pll_layout = {
+const struct clk_pll_layout at91rm9200_pll_layout = {
.pllr_mask = 0x7FFFFFF,
.mul_shift = 16,
.mul_mask = 0x7FF,
};
-static const struct clk_pll_layout at91sam9g45_pll_layout = {
+const struct clk_pll_layout at91sam9g45_pll_layout = {
.pllr_mask = 0xFFFFFF,
.mul_shift = 16,
.mul_mask = 0xFF,
};
-static const struct clk_pll_layout at91sam9g20_pllb_layout = {
+const struct clk_pll_layout at91sam9g20_pllb_layout = {
.pllr_mask = 0x3FFFFF,
.mul_shift = 16,
.mul_mask = 0x3F,
};
-static const struct clk_pll_layout sama5d3_pll_layout = {
+const struct clk_pll_layout sama5d3_pll_layout = {
.pllr_mask = 0x1FFFFFF,
.mul_shift = 18,
.mul_mask = 0x7F,
diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c
index b4afaf22f3fd..de803a2b27d3 100644
--- a/drivers/clk/at91/clk-plldiv.c
+++ b/drivers/clk/at91/clk-plldiv.c
@@ -75,7 +75,7 @@ static const struct clk_ops plldiv_ops = {
.set_rate = clk_plldiv_set_rate,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91_clk_register_plldiv(struct regmap *regmap, const char *name,
const char *parent_name)
{
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
index 0e6aab1252fc..df302bfa8259 100644
--- a/drivers/clk/at91/clk-programmable.c
+++ b/drivers/clk/at91/clk-programmable.c
@@ -25,12 +25,6 @@
#define PROG_PRES(layout, pckr) ((pckr >> layout->pres_shift) & PROG_PRES_MASK)
#define PROG_MAX_RM9200_CSS 3
-struct clk_programmable_layout {
- u8 pres_shift;
- u8 css_mask;
- u8 have_slck_mck;
-};
-
struct clk_programmable {
struct clk_hw hw;
struct regmap *regmap;
@@ -170,7 +164,7 @@ static const struct clk_ops programmable_ops = {
.set_rate = clk_programmable_set_rate,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91_clk_register_programmable(struct regmap *regmap,
const char *name, const char **parent_names,
u8 num_parents, u8 id,
@@ -211,19 +205,19 @@ at91_clk_register_programmable(struct regmap *regmap,
return hw;
}
-static const struct clk_programmable_layout at91rm9200_programmable_layout = {
+const struct clk_programmable_layout at91rm9200_programmable_layout = {
.pres_shift = 2,
.css_mask = 0x3,
.have_slck_mck = 0,
};
-static const struct clk_programmable_layout at91sam9g45_programmable_layout = {
+const struct clk_programmable_layout at91sam9g45_programmable_layout = {
.pres_shift = 2,
.css_mask = 0x3,
.have_slck_mck = 1,
};
-static const struct clk_programmable_layout at91sam9x5_programmable_layout = {
+const struct clk_programmable_layout at91sam9x5_programmable_layout = {
.pres_shift = 4,
.css_mask = 0x7,
.have_slck_mck = 0,
diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c
index 560a8b9abf93..a890132db68f 100644
--- a/drivers/clk/at91/clk-slow.c
+++ b/drivers/clk/at91/clk-slow.c
@@ -40,7 +40,7 @@ static const struct clk_ops sam9260_slow_ops = {
.get_parent = clk_sam9260_slow_get_parent,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91_clk_register_sam9260_slow(struct regmap *regmap,
const char *name,
const char **parent_names,
diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c
index 965c662b90a5..bbf5dc91777f 100644
--- a/drivers/clk/at91/clk-smd.c
+++ b/drivers/clk/at91/clk-smd.c
@@ -111,7 +111,7 @@ static const struct clk_ops at91sam9x5_smd_ops = {
.set_rate = at91sam9x5_clk_smd_set_rate,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
const char **parent_names, u8 num_parents)
{
diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c
index 86a36809765d..1ac0144a38c0 100644
--- a/drivers/clk/at91/clk-system.c
+++ b/drivers/clk/at91/clk-system.c
@@ -88,7 +88,7 @@ static const struct clk_ops system_ops = {
.is_prepared = clk_system_is_prepared,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91_clk_register_system(struct regmap *regmap, const char *name,
const char *parent_name, u8 id)
{
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c
index 791770a563fc..a728320877dd 100644
--- a/drivers/clk/at91/clk-usb.c
+++ b/drivers/clk/at91/clk-usb.c
@@ -192,7 +192,7 @@ static const struct clk_ops at91sam9n12_usb_ops = {
.set_rate = at91sam9x5_clk_usb_set_rate,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
const char **parent_names, u8 num_parents)
{
@@ -225,7 +225,7 @@ at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
return hw;
}
-static struct clk_hw * __init
+struct clk_hw * __init
at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name,
const char *parent_name)
{
@@ -342,7 +342,7 @@ static const struct clk_ops at91rm9200_usb_ops = {
.set_rate = at91rm9200_clk_usb_set_rate,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,
const char *parent_name, const u32 *divisors)
{
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
index cd8d689138ff..6c69b6ac71e1 100644
--- a/drivers/clk/at91/clk-utmi.c
+++ b/drivers/clk/at91/clk-utmi.c
@@ -125,7 +125,7 @@ static const struct clk_ops utmi_ops = {
.recalc_rate = clk_utmi_recalc_rate,
};
-static struct clk_hw * __init
+struct clk_hw * __init
at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
const char *name, const char *parent_name)
{
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index d22b1fa9ecdc..3dc50267a458 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -26,9 +26,151 @@ struct clk_range {
#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
+struct clk_master_layout {
+ u32 mask;
+ u8 pres_shift;
+};
+
+extern const struct clk_master_layout at91rm9200_master_layout;
+extern const struct clk_master_layout at91sam9x5_master_layout;
+
+struct clk_master_characteristics {
+ struct clk_range output;
+ u32 divisors[4];
+ u8 have_div3_pres;
+};
+
+struct clk_pll_layout {
+ u32 pllr_mask;
+ u16 mul_mask;
+ u8 mul_shift;
+};
+
+extern const struct clk_pll_layout at91rm9200_pll_layout;
+extern const struct clk_pll_layout at91sam9g45_pll_layout;
+extern const struct clk_pll_layout at91sam9g20_pllb_layout;
+extern const struct clk_pll_layout sama5d3_pll_layout;
+
+struct clk_pll_characteristics {
+ struct clk_range input;
+ int num_output;
+ struct clk_range *output;
+ u16 *icpll;
+ u8 *out;
+};
+
+struct clk_programmable_layout {
+ u8 pres_shift;
+ u8 css_mask;
+ u8 have_slck_mck;
+};
+
+extern const struct clk_programmable_layout at91rm9200_programmable_layout;
+extern const struct clk_programmable_layout at91sam9g45_programmable_layout;
+extern const struct clk_programmable_layout at91sam9x5_programmable_layout;
+
int of_at91_get_clk_range(struct device_node *np, const char *propname,
struct clk_range *range);
+struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data);
+
+struct clk_hw * __init
+at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,
+ const char *parent_name);
+
+struct clk_hw * __init
+at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,
+ const char *parent_name);
+
+struct clk_hw * __init
+at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
+ const char *parent_name);
+
+struct clk_hw * __init
+at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
+ const char *name, const char **parent_names,
+ u8 num_parents, u8 id, bool pll_audio,
+ const struct clk_range *range);
+
+struct clk_hw * __init
+at91_clk_register_h32mx(struct regmap *regmap, const char *name,
+ const char *parent_name);
+
+struct clk_hw * __init
+at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,
+ const char * const *parent_names,
+ unsigned int num_parents, u8 bus_id);
+
+struct clk_hw * __init
+at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name,
+ u32 frequency, u32 accuracy);
+struct clk_hw * __init
+at91_clk_register_main_osc(struct regmap *regmap, const char *name,
+ const char *parent_name, bool bypass);
+struct clk_hw * __init
+at91_clk_register_rm9200_main(struct regmap *regmap,
+ const char *name,
+ const char *parent_name);
+struct clk_hw * __init
+at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name,
+ const char **parent_names, int num_parents);
+
+struct clk_hw * __init
+at91_clk_register_master(struct regmap *regmap, const char *name,
+ int num_parents, const char **parent_names,
+ const struct clk_master_layout *layout,
+ const struct clk_master_characteristics *characteristics);
+
+struct clk_hw * __init
+at91_clk_register_peripheral(struct regmap *regmap, const char *name,
+ const char *parent_name, u32 id);
+struct clk_hw * __init
+at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,
+ const char *name, const char *parent_name,
+ u32 id, const struct clk_range *range);
+
+struct clk_hw * __init
+at91_clk_register_pll(struct regmap *regmap, const char *name,
+ const char *parent_name, u8 id,
+ const struct clk_pll_layout *layout,
+ const struct clk_pll_characteristics *characteristics);
+struct clk_hw * __init
+at91_clk_register_plldiv(struct regmap *regmap, const char *name,
+ const char *parent_name);
+
+struct clk_hw * __init
+at91_clk_register_programmable(struct regmap *regmap, const char *name,
+ const char **parent_names, u8 num_parents, u8 id,
+ const struct clk_programmable_layout *layout);
+
+struct clk_hw * __init
+at91_clk_register_sam9260_slow(struct regmap *regmap,
+ const char *name,
+ const char **parent_names,
+ int num_parents);
+
+struct clk_hw * __init
+at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
+ const char **parent_names, u8 num_parents);
+
+struct clk_hw * __init
+at91_clk_register_system(struct regmap *regmap, const char *name,
+ const char *parent_name, u8 id);
+
+struct clk_hw * __init
+at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
+ const char **parent_names, u8 num_parents);
+struct clk_hw * __init
+at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name,
+ const char *parent_name);
+struct clk_hw * __init
+at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,
+ const char *parent_name, const u32 *divisors);
+
+struct clk_hw * __init
+at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
+ const char *name, const char *parent_name);
+
#ifdef CONFIG_PM
void pmc_register_id(u8 id);
void pmc_register_pck(u8 pck);
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 07/22] clk: at91: add pmc_data struct and helpers
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (5 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 06/22] clk: at91: allow clock registration from C code Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-17 17:49 ` Stephen Boyd
2018-10-16 14:21 ` [PATCH v2 08/22] dt-bindings: clk: at91: Document new PMC binding Alexandre Belloni
` (15 subsequent siblings)
22 siblings, 1 reply; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Add a new strut to handle references to all the PMC clocks and implement
allocation/free helpers.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
drivers/clk/at91/pmc.c | 44 ++++++++++++++++++++++++++++++++++++++++++
drivers/clk/at91/pmc.h | 17 ++++++++++++++++
2 files changed, 61 insertions(+)
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index 1fa27f4ea538..0f8b3add1b04 100644
--- a/drivers/clk/at91/pmc.c
+++ b/drivers/clk/at91/pmc.c
@@ -47,6 +47,50 @@ int of_at91_get_clk_range(struct device_node *np, const char *propname,
}
EXPORT_SYMBOL_GPL(of_at91_get_clk_range);
+void pmc_data_free(struct pmc_data *pmc_data)
+{
+ kfree(pmc_data->chws);
+ kfree(pmc_data->shws);
+ kfree(pmc_data->phws);
+ kfree(pmc_data->ghws);
+}
+
+struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
+ unsigned int nperiph, unsigned int ngck)
+{
+ struct pmc_data *pmc_data = kzalloc(sizeof(*pmc_data), GFP_KERNEL);
+
+ if (!pmc_data)
+ return NULL;
+
+ pmc_data->ncore = ncore;
+ pmc_data->chws = kcalloc(ncore, sizeof(struct clk_hw *), GFP_KERNEL);
+ if (!pmc_data->chws)
+ goto err;
+
+ pmc_data->nsystem = nsystem;
+ pmc_data->shws = kcalloc(nsystem, sizeof(struct clk_hw *), GFP_KERNEL);
+ if (!pmc_data->shws)
+ goto err;
+
+ pmc_data->nperiph = nperiph;
+ pmc_data->phws = kcalloc(nperiph, sizeof(struct clk_hw *), GFP_KERNEL);
+ if (!pmc_data->phws)
+ goto err;
+
+ pmc_data->ngck = ngck;
+ pmc_data->ghws = kcalloc(ngck, sizeof(struct clk_hw *), GFP_KERNEL);
+ if (!pmc_data->ghws)
+ goto err;
+
+ return pmc_data;
+
+err:
+ pmc_data_free(pmc_data);
+
+ return NULL;
+}
+
#ifdef CONFIG_PM
static struct regmap *pmcreg;
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 3dc50267a458..672a79bda88c 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -19,6 +19,17 @@
extern spinlock_t pmc_pcr_lock;
+struct pmc_data {
+ unsigned int ncore;
+ struct clk_hw **chws;
+ unsigned int nsystem;
+ struct clk_hw **shws;
+ unsigned int nperiph;
+ struct clk_hw **phws;
+ unsigned int ngck;
+ struct clk_hw **ghws;
+};
+
struct clk_range {
unsigned long min;
unsigned long max;
@@ -69,6 +80,12 @@ extern const struct clk_programmable_layout at91rm9200_programmable_layout;
extern const struct clk_programmable_layout at91sam9g45_programmable_layout;
extern const struct clk_programmable_layout at91sam9x5_programmable_layout;
+#define ndck(a, s) (a[s - 1].id + 1)
+#define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1)
+struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
+ unsigned int nperiph, unsigned int ngck);
+void pmc_data_free(struct pmc_data *pmc_data);
+
int of_at91_get_clk_range(struct device_node *np, const char *propname,
struct clk_range *range);
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 08/22] dt-bindings: clk: at91: Document new PMC binding
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (6 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 07/22] clk: at91: add pmc_data struct and helpers Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-17 17:49 ` Stephen Boyd
2018-10-16 14:21 ` [PATCH v2 09/22] clk: at91: add new DT lookup function Alexandre Belloni
` (14 subsequent siblings)
22 siblings, 1 reply; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Document the new PMC binding with only one PMC node for all the PMC clocks
instead of one node per clock as this proved to be problematic.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
.../devicetree/bindings/clock/at91-clock.txt | 516 +-----------------
1 file changed, 21 insertions(+), 495 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
index 8f8f95056f3d..e9f70fcdfe80 100644
--- a/Documentation/devicetree/bindings/clock/at91-clock.txt
+++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
@@ -4,6 +4,8 @@ This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+Slow Clock controller:
+
Required properties:
- compatible : shall be one of the following:
"atmel,at91sam9x5-sckc" or
@@ -16,84 +18,6 @@ Required properties:
"atmel,at91sam9x5-clk-slow-rc-osc":
at91 internal slow RC oscillator
-
- "atmel,<chip>-pmc":
- at91 PMC (Power Management Controller)
- All at91 specific clocks (clocks defined below) must be child
- node of the PMC node.
- <chip> can be: at91rm9200, at91sam9260, at91sam9261,
- at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9x5,
- sama5d2, sama5d3 or sama5d4.
-
- "atmel,at91sam9x5-clk-slow" (under sckc node)
- or
- "atmel,at91sam9260-clk-slow" (under pmc node):
- at91 slow clk
-
- "atmel,at91rm9200-clk-main-osc"
- "atmel,at91sam9x5-clk-main-rc-osc"
- at91 main clk sources
-
- "atmel,at91sam9x5-clk-main"
- "atmel,at91rm9200-clk-main":
- at91 main clock
-
- "atmel,at91rm9200-clk-master" or
- "atmel,at91sam9x5-clk-master":
- at91 master clock
-
- "atmel,at91sam9x5-clk-peripheral" or
- "atmel,at91rm9200-clk-peripheral":
- at91 peripheral clocks
-
- "atmel,at91rm9200-clk-pll" or
- "atmel,at91sam9g45-clk-pll" or
- "atmel,at91sam9g20-clk-pllb" or
- "atmel,sama5d3-clk-pll":
- at91 pll clocks
-
- "atmel,at91sam9x5-clk-plldiv":
- at91 plla divisor
-
- "atmel,at91rm9200-clk-programmable" or
- "atmel,at91sam9g45-clk-programmable" or
- "atmel,at91sam9x5-clk-programmable":
- at91 programmable clocks
-
- "atmel,at91sam9x5-clk-smd":
- at91 SMD (Soft Modem) clock
-
- "atmel,at91rm9200-clk-system":
- at91 system clocks
-
- "atmel,at91rm9200-clk-usb" or
- "atmel,at91sam9x5-clk-usb" or
- "atmel,at91sam9n12-clk-usb":
- at91 usb clock
-
- "atmel,at91sam9x5-clk-utmi":
- at91 utmi clock
-
- "atmel,sama5d4-clk-h32mx":
- at91 h32mx clock
-
- "atmel,sama5d2-clk-generated":
- at91 generated clock
-
- "atmel,sama5d2-clk-audio-pll-frac":
- at91 audio fractional pll
-
- "atmel,sama5d2-clk-audio-pll-pad":
- at91 audio pll CLK_AUDIO output pin
-
- "atmel,sama5d2-clk-audio-pll-pmc"
- at91 audio pll output on AUDIOPLLCLK that feeds the PMC
- and can be used by peripheral clock or generic clock
-
- "atmel,sama5d2-clk-i2s-mux" (under pmc node):
- at91 I2S clock source selection
-
-Required properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id).
- #address-cells : shall be 1 (reg is used to encode clk id).
@@ -109,428 +33,30 @@ For example:
/* put at91 slow clocks here */
};
+Power Management Controller (PMC):
-Required properties for internal slow RC oscillator:
-- #clock-cells : from common clock binding; shall be set to 0.
-- clock-frequency : define the internal RC oscillator frequency.
-
-Optional properties:
-- clock-accuracy : define the internal RC oscillator accuracy.
-
-For example:
- slow_rc_osc: slow_rc_osc {
- compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
- clock-frequency = <32768>;
- clock-accuracy = <50000000>;
- };
-
-Required properties for slow oscillator:
-- #clock-cells : from common clock binding; shall be set to 0.
-- clocks : shall encode the main osc source clk sources (see atmel datasheet).
+Required properties:
+- compatible : shall be "atmel,<chip>-pmc", "syscon":
+ <chip> can be: at91rm9200, at91sam9260, at91sam9261,
+ at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9g15,
+ at91sam9g25, at91sam9g35, at91sam9x25, at91sam9x35, at91sam9x5,
+ sama5d2, sama5d3 or sama5d4.
+- #clock-cells : from common clock binding; shall be set to 2. The first entry
+ is the type of the clock (core, system, peripheral or generated) and the
+ second entry its index as provided by the datasheet
+- clocks : Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries: "slow_clk", "main_xtal"
Optional properties:
- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
provided on XIN.
For example:
- slow_osc: slow_osc {
- compatible = "atmel,at91rm9200-clk-slow-osc";
- #clock-cells = <0>;
- clocks = <&slow_xtal>;
- };
-
-Required properties for slow clock:
-- #clock-cells : from common clock binding; shall be set to 0.
-- clocks : shall encode the slow clk sources (see atmel datasheet).
-
-For example:
- clk32k: slck {
- compatible = "atmel,at91sam9x5-clk-slow";
- #clock-cells = <0>;
- clocks = <&slow_rc_osc &slow_osc>;
- };
-
-Required properties for PMC node:
-- reg : defines the IO memory reserved for the PMC.
-- #size-cells : shall be 0 (reg is used to encode clk id).
-- #address-cells : shall be 1 (reg is used to encode clk id).
-- interrupts : shall be set to PMC interrupt line.
-- interrupt-controller : tell that the PMC is an interrupt controller.
-- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
- and reflect the bit position in the PMC_ER/DR/SR registers.
- You can use the dt macros defined in dt-bindings/clock/at91.h.
- 0 (AT91_PMC_MOSCS) -> main oscillator ready
- 1 (AT91_PMC_LOCKA) -> PLL A ready
- 2 (AT91_PMC_LOCKB) -> PLL B ready
- 3 (AT91_PMC_MCKRDY) -> master clock ready
- 6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready
- 8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready
- 16 (AT91_PMC_MOSCSELS) -> main oscillator selected
- 17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized
- 18 (AT91_PMC_CFDEV) -> clock failure detected
-
-For example:
- pmc: pmc@fffffc00 {
- compatible = "atmel,sama5d3-pmc";
- interrupts = <1 4 7>;
- interrupt-controller;
- #interrupt-cells = <2>;
- #size-cells = <0>;
- #address-cells = <1>;
-
- /* put at91 clocks here */
- };
-
-Required properties for main clock internal RC oscillator:
-- interrupts : shall be set to "<0>".
-- clock-frequency : define the internal RC oscillator frequency.
-
-Optional properties:
-- clock-accuracy : define the internal RC oscillator accuracy.
-
-For example:
- main_rc_osc: main_rc_osc {
- compatible = "atmel,at91sam9x5-clk-main-rc-osc";
- interrupt-parent = <&pmc>;
- interrupts = <0>;
- clock-frequency = <12000000>;
- clock-accuracy = <50000000>;
- };
-
-Required properties for main clock oscillator:
-- interrupts : shall be set to "<0>".
-- #clock-cells : from common clock binding; shall be set to 0.
-- clocks : shall encode the main osc source clk sources (see atmel datasheet).
-
-Optional properties:
-- atmel,osc-bypass : boolean property. Specified if a clock signal is provided
- on XIN.
-
- clock signal is directly provided on XIN pin.
-
-For example:
- main_osc: main_osc {
- compatible = "atmel,at91rm9200-clk-main-osc";
- interrupt-parent = <&pmc>;
- interrupts = <0>;
- #clock-cells = <0>;
- clocks = <&main_xtal>;
- };
-
-Required properties for main clock:
-- interrupts : shall be set to "<0>".
-- #clock-cells : from common clock binding; shall be set to 0.
-- clocks : shall encode the main clk sources (see atmel datasheet).
-
-For example:
- main: mainck {
- compatible = "atmel,at91sam9x5-clk-main";
- interrupt-parent = <&pmc>;
- interrupts = <0>;
- #clock-cells = <0>;
- clocks = <&main_rc_osc &main_osc>;
- };
-
-Required properties for master clock:
-- interrupts : shall be set to "<3>".
-- #clock-cells : from common clock binding; shall be set to 0.
-- clocks : shall be the master clock sources (see atmel datasheet) phandles.
- e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
-- atmel,clk-output-range : minimum and maximum clock frequency (two u32
- fields).
- e.g. output = <0 133000000>; <=> 0 to 133MHz.
-- atmel,clk-divisors : master clock divisors table (four u32 fields).
- 0 <=> reserved value.
- e.g. divisors = <1 2 4 6>;
-- atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the
- PRES field as CLOCK_DIV3 (e.g sam9x5).
-
-For example:
- mck: mck {
- compatible = "atmel,at91rm9200-clk-master";
- interrupt-parent = <&pmc>;
- interrupts = <3>;
- #clock-cells = <0>;
- atmel,clk-output-range = <0 133000000>;
- atmel,clk-divisors = <1 2 4 0>;
- };
-
-Required properties for peripheral clocks:
-- #size-cells : shall be 0 (reg is used to encode clk id).
-- #address-cells : shall be 1 (reg is used to encode clk id).
-- clocks : shall be the master clock phandle.
- e.g. clocks = <&mck>;
-- name: device tree node describing a specific peripheral clock.
- * #clock-cells : from common clock binding; shall be set to 0.
- * reg: peripheral id. See Atmel's datasheets to get a full
- list of peripheral ids.
- * atmel,clk-output-range : minimum and maximum clock frequency
- (two u32 fields). Only valid on at91sam9x5-clk-peripheral
- compatible IPs.
-
-For example:
- periph: periphck {
- compatible = "atmel,at91sam9x5-clk-peripheral";
- #size-cells = <0>;
- #address-cells = <1>;
- clocks = <&mck>;
-
- ssc0_clk {
- #clock-cells = <0>;
- reg = <2>;
- atmel,clk-output-range = <0 133000000>;
- };
-
- usart0_clk {
- #clock-cells = <0>;
- reg = <3>;
- atmel,clk-output-range = <0 66000000>;
- };
- };
-
-
-Required properties for pll clocks:
-- interrupts : shall be set to "<1>".
-- #clock-cells : from common clock binding; shall be set to 0.
-- clocks : shall be the main clock phandle.
-- reg : pll id.
- 0 -> PLL A
- 1 -> PLL B
-- atmel,clk-input-range : minimum and maximum source clock frequency (two u32
- fields).
- e.g. input = <1 32000000>; <=> 1 to 32MHz.
-- #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
- range description. Sould be set to 2, 3
- or 4.
- * 1st and 2nd cells represent the frequency range (min-max).
- * 3rd cell is optional and represents the OUT field value for the given
- range.
- * 4th cell is optional and represents the ICPLL field (PLLICPR
- register)
-- atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
- depending on #atmel,pll-output-range-cells
- property value.
-
-For example:
- plla: pllack {
- compatible = "atmel,at91sam9g45-clk-pll";
- interrupt-parent = <&pmc>;
- interrupts = <1>;
- #clock-cells = <0>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <2000000 32000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <74500000 800000000 0 0
- 69500000 750000000 1 0
- 64500000 700000000 2 0
- 59500000 650000000 3 0
- 54500000 600000000 0 1
- 49500000 550000000 1 1
- 44500000 500000000 2 1
- 40000000 450000000 3 1>;
- };
-
-Required properties for plldiv clocks (plldiv = pll / 2):
-- #clock-cells : from common clock binding; shall be set to 0.
-- clocks : shall be the plla clock phandle.
-
-The pll divisor is equal to 2 and cannot be changed.
-
-For example:
- plladiv: plladivck {
- compatible = "atmel,at91sam9x5-clk-plldiv";
- #clock-cells = <0>;
- clocks = <&plla>;
- };
-
-Required properties for programmable clocks:
-- #size-cells : shall be 0 (reg is used to encode clk id).
-- #address-cells : shall be 1 (reg is used to encode clk id).
-- clocks : shall be the programmable clock source phandles.
- e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
-- name: device tree node describing a specific prog clock.
- * #clock-cells : from common clock binding; shall be set to 0.
- * reg : programmable clock id (register offset from PCKx
- register).
- * interrupts : shall be set to "<(8 + id)>".
-
-For example:
- prog: progck {
- compatible = "atmel,at91sam9g45-clk-programmable";
- #size-cells = <0>;
- #address-cells = <1>;
- interrupt-parent = <&pmc>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
-
- prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <8>;
- };
-
- prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <9>;
- };
- };
-
-
-Required properties for smd clock:
-- #clock-cells : from common clock binding; shall be set to 0.
-- clocks : shall be the smd clock source phandles.
- e.g. clocks = <&plladiv>, <&utmi>;
-
-For example:
- smd: smdck {
- compatible = "atmel,at91sam9x5-clk-smd";
- #clock-cells = <0>;
- clocks = <&plladiv>, <&utmi>;
- };
-
-Required properties for system clocks:
-- #size-cells : shall be 0 (reg is used to encode clk id).
-- #address-cells : shall be 1 (reg is used to encode clk id).
-- name: device tree node describing a specific system clock.
- * #clock-cells : from common clock binding; shall be set to 0.
- * reg: system clock id (bit position in SCER/SCDR/SCSR registers).
- See Atmel's datasheet to get a full list of system clock ids.
-
-For example:
- system: systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ddrck {
- #clock-cells = <0>;
- reg = <2>;
- clocks = <&mck>;
- };
-
- uhpck {
- #clock-cells = <0>;
- reg = <6>;
- clocks = <&usb>;
- };
-
- udpck {
- #clock-cells = <0>;
- reg = <7>;
- clocks = <&usb>;
- };
- };
-
-
-Required properties for usb clock:
-- #clock-cells : from common clock binding; shall be set to 0.
-- clocks : shall be the smd clock source phandles.
- e.g. clocks = <&pllb>;
-- atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"):
- usb clock divisor table.
- e.g. divisors = <1 2 4 0>;
-
-For example:
- usb: usbck {
- compatible = "atmel,at91sam9x5-clk-usb";
- #clock-cells = <0>;
- clocks = <&plladiv>, <&utmi>;
- };
-
- usb: usbck {
- compatible = "atmel,at91rm9200-clk-usb";
- #clock-cells = <0>;
- clocks = <&pllb>;
- atmel,clk-divisors = <1 2 4 0>;
- };
-
-
-Required properties for utmi clock:
-- interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
-- #clock-cells : from common clock binding; shall be set to 0.
-- clocks : shall be the main clock source phandle.
-
-For example:
- utmi: utmick {
- compatible = "atmel,at91sam9x5-clk-utmi";
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>;
- #clock-cells = <0>;
- clocks = <&main>;
- };
-
-Required properties for 32 bits bus Matrix clock (h32mx clock):
-- #clock-cells : from common clock binding; shall be set to 0.
-- clocks : shall be the master clock source phandle.
-
-For example:
- h32ck: h32mxck {
- #clock-cells = <0>;
- compatible = "atmel,sama5d4-clk-h32mx";
- clocks = <&mck>;
- };
-
-Required properties for generated clocks:
-- #size-cells : shall be 0 (reg is used to encode clk id).
-- #address-cells : shall be 1 (reg is used to encode clk id).
-- clocks : shall be the generated clock source phandles.
- e.g. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
-- name: device tree node describing a specific generated clock.
- * #clock-cells : from common clock binding; shall be set to 0.
- * reg: peripheral id. See Atmel's datasheets to get a full
- list of peripheral ids.
- * atmel,clk-output-range : minimum and maximum clock frequency
- (two u32 fields).
-
-For example:
- gck {
- compatible = "atmel,sama5d2-clk-generated";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
-
- tcb0_gclk: tcb0_gclk {
- #clock-cells = <0>;
- reg = <35>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- pwm_gclk: pwm_gclk {
- #clock-cells = <0>;
- reg = <38>;
- atmel,clk-output-range = <0 83000000>;
- };
- };
-
-Required properties for I2S mux clocks:
-- #size-cells : shall be 0 (reg is used to encode I2S bus id).
-- #address-cells : shall be 1 (reg is used to encode I2S bus id).
-- name: device tree node describing a specific mux clock.
- * #clock-cells : from common clock binding; shall be set to 0.
- * clocks : shall be the mux clock parent phandles; shall be 2 phandles:
- peripheral and generated clock; the first phandle shall belong to the
- peripheral clock and the second one shall belong to the generated
- clock; "clock-indices" property can be user to specify
- the correct order.
- * reg: I2S bus id of the corresponding mux clock.
- e.g. reg = <0>; for i2s0, reg = <1>; for i2s1
-
-For example:
- i2s_clkmux {
- compatible = "atmel,sama5d2-clk-i2s-mux";
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2s0muxck: i2s0_muxclk {
- clocks = <&i2s0_clk>, <&i2s0_gclk>;
- #clock-cells = <0>;
- reg = <0>;
- };
-
- i2s1muxck: i2s1_muxclk {
- clocks = <&i2s1_clk>, <&i2s1_gclk>;
- #clock-cells = <0>;
- reg = <1>;
- };
+ pmc: pmc@f0018000 {
+ compatible = "atmel,sama5d4-pmc", "syscon";
+ reg = <0xf0018000 0x120>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ #clock-cells = <2>;
+ clocks = <&clk32k>, <&main_xtal>;
+ clock-names = "slow_clk", "main_xtal";
};
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 09/22] clk: at91: add new DT lookup function
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (7 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 08/22] dt-bindings: clk: at91: Document new PMC binding Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-17 17:50 ` Stephen Boyd
2018-10-16 14:21 ` [PATCH v2 10/22] clk: at91: add sama5d4 pmc driver Alexandre Belloni
` (13 subsequent siblings)
22 siblings, 1 reply; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Add a new DT lookup function to lookup for PMC clocks.
Note that the #ifndef AT91_PMC_MOSCS section will be removed once all the
platforms are converted.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Rob Herring <robh@kernel.org>
---
drivers/clk/at91/pmc.c | 34 ++++++++++++++++++++++++++++++++
include/dt-bindings/clock/at91.h | 15 ++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index 0f8b3add1b04..db24539d5740 100644
--- a/drivers/clk/at91/pmc.c
+++ b/drivers/clk/at91/pmc.c
@@ -19,6 +19,8 @@
#include <asm/proc-fns.h>
+#include <dt-bindings/clock/at91.h>
+
#include "pmc.h"
#define PMC_MAX_IDS 128
@@ -47,6 +49,38 @@ int of_at91_get_clk_range(struct device_node *np, const char *propname,
}
EXPORT_SYMBOL_GPL(of_at91_get_clk_range);
+struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data)
+{
+ unsigned int type = clkspec->args[0];
+ unsigned int idx = clkspec->args[1];
+ struct pmc_data *pmc_data = data;
+
+ switch (type) {
+ case PMC_TYPE_CORE:
+ if (idx < pmc_data->ncore)
+ return pmc_data->chws[idx];
+ break;
+ case PMC_TYPE_SYSTEM:
+ if (idx < pmc_data->nsystem)
+ return pmc_data->shws[idx];
+ break;
+ case PMC_TYPE_PERIPHERAL:
+ if (idx < pmc_data->nperiph)
+ return pmc_data->phws[idx];
+ break;
+ case PMC_TYPE_GCK:
+ if (idx < pmc_data->ngck)
+ return pmc_data->ghws[idx];
+ break;
+ default:
+ break;
+ }
+
+ pr_err("%s: invalid type (%u) or index (%u)\n", __func__, type, idx);
+
+ return ERR_PTR(-EINVAL);
+}
+
void pmc_data_free(struct pmc_data *pmc_data)
{
kfree(pmc_data->chws);
diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
index ab3ee241d10c..ed30da28d820 100644
--- a/include/dt-bindings/clock/at91.h
+++ b/include/dt-bindings/clock/at91.h
@@ -9,6 +9,20 @@
#ifndef _DT_BINDINGS_CLK_AT91_H
#define _DT_BINDINGS_CLK_AT91_H
+#define PMC_TYPE_CORE 0
+#define PMC_TYPE_SYSTEM 1
+#define PMC_TYPE_PERIPHERAL 2
+#define PMC_TYPE_GCK 3
+
+#define PMC_SLOW 0
+#define PMC_MCK 1
+#define PMC_UTMI 2
+#define PMC_MAIN 3
+#define PMC_MCK2 4
+#define PMC_I2S0_MUX 5
+#define PMC_I2S1_MUX 6
+
+#ifndef AT91_PMC_MOSCS
#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
#define AT91_PMC_LOCKA 1 /* PLLA Lock */
#define AT91_PMC_LOCKB 2 /* PLLB Lock */
@@ -19,5 +33,6 @@
#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */
#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
#define AT91_PMC_GCKRDY 24 /* Generated Clocks */
+#endif
#endif
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* Re: [PATCH v2 09/22] clk: at91: add new DT lookup function
2018-10-16 14:21 ` [PATCH v2 09/22] clk: at91: add new DT lookup function Alexandre Belloni
@ 2018-10-17 17:50 ` Stephen Boyd
0 siblings, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2018-10-17 17:50 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Quoting Alexandre Belloni (2018-10-16 07:21:47)
> Add a new DT lookup function to lookup for PMC clocks.
>
> Note that the #ifndef AT91_PMC_MOSCS section will be removed once all the
> platforms are converted.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v2 10/22] clk: at91: add sama5d4 pmc driver
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (8 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 09/22] clk: at91: add new DT lookup function Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-17 17:50 ` Stephen Boyd
2018-10-16 14:21 ` [PATCH v2 11/22] clk: at91: add sama5d2 PMC driver Alexandre Belloni
` (12 subsequent siblings)
22 siblings, 1 reply; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Add a driver for the PMC clocks of the sama5d4
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/sama5d4.c | 264 +++++++++++++++++++++++++++++++++++++
2 files changed, 265 insertions(+)
create mode 100644 drivers/clk/at91/sama5d4.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index facc169ebb68..7cdb762f3e2e 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o
obj-$(CONFIG_HAVE_AT91_GENERATED_CLK) += clk-generated.o
obj-$(CONFIG_HAVE_AT91_I2S_MUX_CLK) += clk-i2s-mux.o
+obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c
new file mode 100644
index 000000000000..64b9f438f73b
--- /dev/null
+++ b/drivers/clk/at91/sama5d4.c
@@ -0,0 +1,264 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/at91.h>
+
+#include "pmc.h"
+
+static const struct clk_master_characteristics mck_characteristics = {
+ .output = { .min = 125000000, .max = 200000000 },
+ .divisors = { 1, 2, 4, 3 },
+};
+
+static u8 plla_out[] = { 0 };
+
+static u16 plla_icpll[] = { 0 };
+
+static struct clk_range plla_outputs[] = {
+ { .min = 600000000, .max = 1200000000 },
+};
+
+static const struct clk_pll_characteristics plla_characteristics = {
+ .input = { .min = 12000000, .max = 12000000 },
+ .num_output = ARRAY_SIZE(plla_outputs),
+ .output = plla_outputs,
+ .icpll = plla_icpll,
+ .out = plla_out,
+};
+
+static const struct {
+ char *n;
+ char *p;
+ u8 id;
+} sama5d4_systemck[] = {
+ { .n = "ddrck", .p = "masterck", .id = 2 },
+ { .n = "lcdck", .p = "masterck", .id = 3 },
+ { .n = "smdck", .p = "smdclk", .id = 4 },
+ { .n = "uhpck", .p = "usbck", .id = 6 },
+ { .n = "udpck", .p = "usbck", .id = 7 },
+ { .n = "pck0", .p = "prog0", .id = 8 },
+ { .n = "pck1", .p = "prog1", .id = 9 },
+ { .n = "pck2", .p = "prog2", .id = 10 },
+};
+
+static const struct {
+ char *n;
+ u8 id;
+} sama5d4_periph32ck[] = {
+ { .n = "pioD_clk", .id = 5 },
+ { .n = "usart0_clk", .id = 6 },
+ { .n = "usart1_clk", .id = 7 },
+ { .n = "icm_clk", .id = 9 },
+ { .n = "aes_clk", .id = 12 },
+ { .n = "tdes_clk", .id = 14 },
+ { .n = "sha_clk", .id = 15 },
+ { .n = "matrix1_clk", .id = 17 },
+ { .n = "hsmc_clk", .id = 22 },
+ { .n = "pioA_clk", .id = 23 },
+ { .n = "pioB_clk", .id = 24 },
+ { .n = "pioC_clk", .id = 25 },
+ { .n = "pioE_clk", .id = 26 },
+ { .n = "uart0_clk", .id = 27 },
+ { .n = "uart1_clk", .id = 28 },
+ { .n = "usart2_clk", .id = 29 },
+ { .n = "usart3_clk", .id = 30 },
+ { .n = "usart4_clk", .id = 31 },
+ { .n = "twi0_clk", .id = 32 },
+ { .n = "twi1_clk", .id = 33 },
+ { .n = "twi2_clk", .id = 34 },
+ { .n = "mci0_clk", .id = 35 },
+ { .n = "mci1_clk", .id = 36 },
+ { .n = "spi0_clk", .id = 37 },
+ { .n = "spi1_clk", .id = 38 },
+ { .n = "spi2_clk", .id = 39 },
+ { .n = "tcb0_clk", .id = 40 },
+ { .n = "tcb1_clk", .id = 41 },
+ { .n = "tcb2_clk", .id = 42 },
+ { .n = "pwm_clk", .id = 43 },
+ { .n = "adc_clk", .id = 44 },
+ { .n = "dbgu_clk", .id = 45 },
+ { .n = "uhphs_clk", .id = 46 },
+ { .n = "udphs_clk", .id = 47 },
+ { .n = "ssc0_clk", .id = 48 },
+ { .n = "ssc1_clk", .id = 49 },
+ { .n = "trng_clk", .id = 53 },
+ { .n = "macb0_clk", .id = 54 },
+ { .n = "macb1_clk", .id = 55 },
+ { .n = "fuse_clk", .id = 57 },
+ { .n = "securam_clk", .id = 59 },
+ { .n = "smd_clk", .id = 61 },
+ { .n = "twi3_clk", .id = 62 },
+ { .n = "catb_clk", .id = 63 },
+};
+
+static const struct {
+ char *n;
+ u8 id;
+} sama5d4_periphck[] = {
+ { .n = "dma0_clk", .id = 8 },
+ { .n = "cpkcc_clk", .id = 10 },
+ { .n = "aesb_clk", .id = 13 },
+ { .n = "mpddr_clk", .id = 16 },
+ { .n = "matrix0_clk", .id = 18 },
+ { .n = "vdec_clk", .id = 19 },
+ { .n = "dma1_clk", .id = 50 },
+ { .n = "lcdc_clk", .id = 51 },
+ { .n = "isi_clk", .id = 52 },
+};
+
+static void __init sama5d4_pmc_setup(struct device_node *np)
+{
+ struct clk_range range = CLK_RANGE(0, 0);
+ const char *slck_name, *mainxtal_name;
+ struct pmc_data *sama5d4_pmc;
+ const char *parent_names[5];
+ struct regmap *regmap;
+ struct clk_hw *hw;
+ unsigned int i;
+ bool bypass;
+
+ i = of_property_match_string(np, "clock-names", "slow_clk");
+ if (i < 0)
+ return;
+
+ slck_name = of_clk_get_parent_name(np, i);
+
+ i = of_property_match_string(np, "clock-names", "main_xtal");
+ if (i < 0)
+ return;
+ mainxtal_name = of_clk_get_parent_name(np, i);
+
+ regmap = syscon_node_to_regmap(np);
+ if (IS_ERR(regmap))
+ return;
+
+ sama5d4_pmc = pmc_data_allocate(PMC_MCK2 +1,
+ nck(sama5d4_systemck),
+ nck(sama5d4_periph32ck), 0);
+ if (!sama5d4_pmc)
+ return;
+
+ hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
+ 100000000);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ bypass = of_property_read_bool(np, "atmel,osc-bypass");
+
+ hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
+ bypass);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ parent_names[0] = "main_rc_osc";
+ parent_names[1] = "main_osc";
+ hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
+ &sama5d3_pll_layout, &plla_characteristics);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d4_pmc->chws[PMC_UTMI] = hw;
+
+ parent_names[0] = slck_name;
+ parent_names[1] = "mainck";
+ parent_names[2] = "plladivck";
+ parent_names[3] = "utmick";
+ hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
+ &at91sam9x5_master_layout,
+ &mck_characteristics);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d4_pmc->chws[PMC_MCK] = hw;
+
+ hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck");
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d4_pmc->chws[PMC_MCK2] = hw;
+
+ parent_names[0] = "plladivck";
+ parent_names[1] = "utmick";
+ hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ parent_names[0] = "plladivck";
+ parent_names[1] = "utmick";
+ hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ parent_names[0] = slck_name;
+ parent_names[1] = "mainck";
+ parent_names[2] = "plladivck";
+ parent_names[3] = "utmick";
+ parent_names[4] = "mck";
+ for (i = 0; i < 3; i++) {
+ char name[6];
+
+ snprintf(name, sizeof(name), "prog%d", i);
+
+ hw = at91_clk_register_programmable(regmap, name,
+ parent_names, 5, i,
+ &at91sam9x5_programmable_layout);
+ if (IS_ERR(hw))
+ goto err_free;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sama5d4_systemck); i++) {
+ hw = at91_clk_register_system(regmap, sama5d4_systemck[i].n,
+ sama5d4_systemck[i].p,
+ sama5d4_systemck[i].id);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d4_pmc->shws[sama5d4_systemck[i].id] = hw;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sama5d4_periphck); i++) {
+ hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+ sama5d4_periphck[i].n,
+ "masterck",
+ sama5d4_periphck[i].id,
+ &range);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d4_pmc->phws[sama5d4_periphck[i].id] = hw;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sama5d4_periph32ck); i++) {
+ hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+ sama5d4_periph32ck[i].n,
+ "h32mxck",
+ sama5d4_periph32ck[i].id,
+ &range);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d4_pmc->phws[sama5d4_periph32ck[i].id] = hw;
+ }
+
+ of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d4_pmc);
+
+ return;
+
+err_free:
+ pmc_data_free(sama5d4_pmc);
+}
+CLK_OF_DECLARE_DRIVER(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup);
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 11/22] clk: at91: add sama5d2 PMC driver
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (9 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 10/22] clk: at91: add sama5d4 pmc driver Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-17 17:50 ` Stephen Boyd
2018-10-16 14:21 ` [PATCH v2 12/22] clk: at91: add at91sam9260 " Alexandre Belloni
` (11 subsequent siblings)
22 siblings, 1 reply; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Add a driver for the PMC clocks of the sama5d2
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/sama5d2.c | 336 +++++++++++++++++++++++++++++++++++++
2 files changed, 337 insertions(+)
create mode 100644 drivers/clk/at91/sama5d2.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 7cdb762f3e2e..1e7c70dda723 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o
obj-$(CONFIG_HAVE_AT91_GENERATED_CLK) += clk-generated.o
obj-$(CONFIG_HAVE_AT91_I2S_MUX_CLK) += clk-i2s-mux.o
obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
+obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o
diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
new file mode 100644
index 000000000000..07f1f1d613ff
--- /dev/null
+++ b/drivers/clk/at91/sama5d2.c
@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/at91.h>
+
+#include "pmc.h"
+
+static const struct clk_master_characteristics mck_characteristics = {
+ .output = { .min = 124000000, .max = 166000000 },
+ .divisors = { 1, 2, 4, 3 },
+};
+
+static u8 plla_out[] = { 0 };
+
+static u16 plla_icpll[] = { 0 };
+
+static struct clk_range plla_outputs[] = {
+ { .min = 600000000, .max = 1200000000 },
+};
+
+static const struct clk_pll_characteristics plla_characteristics = {
+ .input = { .min = 12000000, .max = 12000000 },
+ .num_output = ARRAY_SIZE(plla_outputs),
+ .output = plla_outputs,
+ .icpll = plla_icpll,
+ .out = plla_out,
+};
+
+static const struct {
+ char *n;
+ char *p;
+ u8 id;
+} sama5d2_systemck[] = {
+ { .n = "ddrck", .p = "masterck", .id = 2 },
+ { .n = "lcdck", .p = "masterck", .id = 3 },
+ { .n = "uhpck", .p = "usbck", .id = 6 },
+ { .n = "udpck", .p = "usbck", .id = 7 },
+ { .n = "pck0", .p = "prog0", .id = 8 },
+ { .n = "pck1", .p = "prog1", .id = 9 },
+ { .n = "pck2", .p = "prog2", .id = 10 },
+ { .n = "iscck", .p = "masterck", .id = 18 },
+};
+
+static const struct {
+ char *n;
+ u8 id;
+ struct clk_range r;
+} sama5d2_periph32ck[] = {
+ { .n = "macb0_clk", .id = 5, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "tdes_clk", .id = 11, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "matrix1_clk", .id = 14, },
+ { .n = "hsmc_clk", .id = 17, },
+ { .n = "pioA_clk", .id = 18, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "flx0_clk", .id = 19, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "flx1_clk", .id = 20, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "flx2_clk", .id = 21, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "flx3_clk", .id = 22, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "flx4_clk", .id = 23, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "uart0_clk", .id = 24, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "uart1_clk", .id = 25, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "uart2_clk", .id = 26, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "uart3_clk", .id = 27, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "uart4_clk", .id = 28, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "twi0_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "twi1_clk", .id = 30, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "spi0_clk", .id = 33, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "spi1_clk", .id = 34, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "tcb0_clk", .id = 35, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "tcb1_clk", .id = 36, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "pwm_clk", .id = 38, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "adc_clk", .id = 40, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "uhphs_clk", .id = 41, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "udphs_clk", .id = 42, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "ssc0_clk", .id = 43, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "ssc1_clk", .id = 44, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "trng_clk", .id = 47, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "pdmic_clk", .id = 48, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "securam_clk", .id = 51, },
+ { .n = "i2s0_clk", .id = 54, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "i2s1_clk", .id = 55, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "can0_clk", .id = 56, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "can1_clk", .id = 57, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "classd_clk", .id = 59, .r = { .min = 0, .max = 83000000 }, },
+};
+
+static const struct {
+ char *n;
+ u8 id;
+} sama5d2_periphck[] = {
+ { .n = "dma0_clk", .id = 6, },
+ { .n = "dma1_clk", .id = 7, },
+ { .n = "aes_clk", .id = 9, },
+ { .n = "aesb_clk", .id = 10, },
+ { .n = "sha_clk", .id = 12, },
+ { .n = "mpddr_clk", .id = 13, },
+ { .n = "matrix0_clk", .id = 15, },
+ { .n = "sdmmc0_hclk", .id = 31, },
+ { .n = "sdmmc1_hclk", .id = 32, },
+ { .n = "lcdc_clk", .id = 45, },
+ { .n = "isc_clk", .id = 46, },
+ { .n = "qspi0_clk", .id = 52, },
+ { .n = "qspi1_clk", .id = 53, },
+};
+
+static const struct {
+ char *n;
+ u8 id;
+ struct clk_range r;
+ bool pll;
+} sama5d2_gck[] = {
+ { .n = "sdmmc0_gclk", .id = 31, },
+ { .n = "sdmmc1_gclk", .id = 32, },
+ { .n = "tcb0_gclk", .id = 35, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "tcb1_gclk", .id = 36, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "pwm_gclk", .id = 38, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "isc_gclk", .id = 46, },
+ { .n = "pdmic_gclk", .id = 48, },
+ { .n = "i2s0_gclk", .id = 54, .pll = true },
+ { .n = "i2s1_gclk", .id = 55, .pll = true },
+ { .n = "can0_gclk", .id = 56, .r = { .min = 0, .max = 80000000 }, },
+ { .n = "can1_gclk", .id = 57, .r = { .min = 0, .max = 80000000 }, },
+ { .n = "classd_gclk", .id = 59, .r = { .min = 0, .max = 100000000 },
+ .pll = true },
+};
+
+static void __init sama5d2_pmc_setup(struct device_node *np)
+{
+ struct clk_range range = CLK_RANGE(0, 0);
+ const char *slck_name, *mainxtal_name;
+ struct pmc_data *sama5d2_pmc;
+ const char *parent_names[6];
+ struct regmap *regmap, *regmap_sfr;
+ struct clk_hw *hw;
+ unsigned int i;
+ bool bypass;
+
+ i = of_property_match_string(np, "clock-names", "slow_clk");
+ if (i < 0)
+ return;
+
+ slck_name = of_clk_get_parent_name(np, i);
+
+ i = of_property_match_string(np, "clock-names", "main_xtal");
+ if (i < 0)
+ return;
+ mainxtal_name = of_clk_get_parent_name(np, i);
+
+ regmap = syscon_node_to_regmap(np);
+ if (IS_ERR(regmap))
+ return;
+
+ sama5d2_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1,
+ nck(sama5d2_systemck),
+ nck(sama5d2_periph32ck),
+ nck(sama5d2_gck));
+ if (!sama5d2_pmc)
+ return;
+
+ hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
+ 100000000);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ bypass = of_property_read_bool(np, "atmel,osc-bypass");
+
+ hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
+ bypass);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ parent_names[0] = "main_rc_osc";
+ parent_names[1] = "main_osc";
+ hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d2_pmc->chws[PMC_MAIN] = hw;
+
+ hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
+ &sama5d3_pll_layout, &plla_characteristics);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck",
+ "mainck");
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck",
+ "audiopll_fracck");
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck",
+ "audiopll_fracck");
+ if (IS_ERR(hw))
+ goto err_free;
+
+ regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
+ if (IS_ERR(regmap_sfr))
+ regmap_sfr = NULL;
+
+ hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck");
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d2_pmc->chws[PMC_UTMI] = hw;
+
+ parent_names[0] = slck_name;
+ parent_names[1] = "mainck";
+ parent_names[2] = "plladivck";
+ parent_names[3] = "utmick";
+ hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
+ &at91sam9x5_master_layout,
+ &mck_characteristics);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d2_pmc->chws[PMC_MCK] = hw;
+
+ hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck");
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d2_pmc->chws[PMC_MCK2] = hw;
+
+ parent_names[0] = "plladivck";
+ parent_names[1] = "utmick";
+ hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ parent_names[0] = slck_name;
+ parent_names[1] = "mainck";
+ parent_names[2] = "plladivck";
+ parent_names[3] = "utmick";
+ parent_names[4] = "mck";
+ for (i = 0; i < 3; i++) {
+ char name[6];
+
+ snprintf(name, sizeof(name), "prog%d", i);
+
+ hw = at91_clk_register_programmable(regmap, name,
+ parent_names, 5, i,
+ &at91sam9x5_programmable_layout);
+ if (IS_ERR(hw))
+ goto err_free;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sama5d2_systemck); i++) {
+ hw = at91_clk_register_system(regmap, sama5d2_systemck[i].n,
+ sama5d2_systemck[i].p,
+ sama5d2_systemck[i].id);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d2_pmc->shws[sama5d2_systemck[i].id] = hw;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) {
+ hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+ sama5d2_periphck[i].n,
+ "masterck",
+ sama5d2_periphck[i].id,
+ &range);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d2_pmc->phws[sama5d2_periphck[i].id] = hw;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) {
+ hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+ sama5d2_periph32ck[i].n,
+ "h32mxck",
+ sama5d2_periph32ck[i].id,
+ &sama5d2_periph32ck[i].r);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d2_pmc->phws[sama5d2_periph32ck[i].id] = hw;
+ }
+
+ parent_names[0] = slck_name;
+ parent_names[1] = "mainck";
+ parent_names[2] = "plladivck";
+ parent_names[3] = "utmick";
+ parent_names[4] = "mck";
+ parent_names[5] = "audiopll_pmcck";
+ for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
+ hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
+ sama5d2_gck[i].n,
+ parent_names, 6,
+ sama5d2_gck[i].id,
+ sama5d2_gck[i].pll,
+ &sama5d2_gck[i].r);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d2_pmc->ghws[sama5d2_gck[i].id] = hw;
+ }
+
+ if (regmap_sfr) {
+ parent_names[0] = "i2s0_clk";
+ parent_names[1] = "i2s0_gclk";
+ hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk",
+ parent_names, 2, 0);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d2_pmc->chws[PMC_I2S0_MUX] = hw;
+
+ parent_names[0] = "i2s1_clk";
+ parent_names[1] = "i2s1_gclk";
+ hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk",
+ parent_names, 2, 1);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d2_pmc->chws[PMC_I2S1_MUX] = hw;
+ }
+
+ of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d2_pmc);
+
+ return;
+
+err_free:
+ pmc_data_free(sama5d2_pmc);
+}
+CLK_OF_DECLARE_DRIVER(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 12/22] clk: at91: add at91sam9260 PMC driver
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (10 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 11/22] clk: at91: add sama5d2 PMC driver Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-17 17:50 ` Stephen Boyd
2018-10-16 14:21 ` [PATCH v2 13/22] clk: at91: add at91sam9x5 PMCs driver Alexandre Belloni
` (10 subsequent siblings)
22 siblings, 1 reply; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Add a driver for the PMC clocks of the at91sam9260, at91sam9261,
at91am9263 and at91sam9g20 SoCs.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/at91sam9260.c | 494 +++++++++++++++++++++++++++++++++
2 files changed, 495 insertions(+)
create mode 100644 drivers/clk/at91/at91sam9260.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 1e7c70dda723..08399003c752 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -14,5 +14,6 @@ obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o
obj-$(CONFIG_HAVE_AT91_GENERATED_CLK) += clk-generated.o
obj-$(CONFIG_HAVE_AT91_I2S_MUX_CLK) += clk-i2s-mux.o
+obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o
obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o
diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c
new file mode 100644
index 000000000000..49aeee6c31a6
--- /dev/null
+++ b/drivers/clk/at91/at91sam9260.c
@@ -0,0 +1,494 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/at91.h>
+
+#include "pmc.h"
+
+struct sck {
+ char *n;
+ char *p;
+ u8 id;
+};
+
+struct pck {
+ char *n;
+ u8 id;
+};
+
+struct at91sam926x_data {
+ const struct clk_pll_layout *plla_layout;
+ const struct clk_pll_characteristics *plla_characteristics;
+ const struct clk_pll_layout *pllb_layout;
+ const struct clk_pll_characteristics *pllb_characteristics;
+ const struct clk_master_characteristics *mck_characteristics;
+ const struct sck *sck;
+ const struct pck *pck;
+ u8 num_sck;
+ u8 num_pck;
+ u8 num_progck;
+ bool has_slck;
+};
+
+static const struct clk_master_characteristics sam9260_mck_characteristics = {
+ .output = { .min = 0, .max = 105000000 },
+ .divisors = { 1, 2, 4, 0 },
+};
+
+static u8 sam9260_plla_out[] = { 0, 2 };
+
+static u16 sam9260_plla_icpll[] = { 1, 1 };
+
+static struct clk_range sam9260_plla_outputs[] = {
+ { .min = 80000000, .max = 160000000 },
+ { .min = 150000000, .max = 240000000 },
+};
+
+static const struct clk_pll_characteristics sam9260_plla_characteristics = {
+ .input = { .min = 1000000, .max = 32000000 },
+ .num_output = ARRAY_SIZE(sam9260_plla_outputs),
+ .output = sam9260_plla_outputs,
+ .icpll = sam9260_plla_icpll,
+ .out = sam9260_plla_out,
+};
+
+static u8 sam9260_pllb_out[] = { 1 };
+
+static u16 sam9260_pllb_icpll[] = { 1 };
+
+static struct clk_range sam9260_pllb_outputs[] = {
+ { .min = 70000000, .max = 130000000 },
+};
+
+static const struct clk_pll_characteristics sam9260_pllb_characteristics = {
+ .input = { .min = 1000000, .max = 5000000 },
+ .num_output = ARRAY_SIZE(sam9260_pllb_outputs),
+ .output = sam9260_pllb_outputs,
+ .icpll = sam9260_pllb_icpll,
+ .out = sam9260_pllb_out,
+};
+
+static const struct sck at91sam9260_systemck[] = {
+ { .n = "uhpck", .p = "usbck", .id = 6 },
+ { .n = "udpck", .p = "usbck", .id = 7 },
+ { .n = "pck0", .p = "prog0", .id = 8 },
+ { .n = "pck1", .p = "prog1", .id = 9 },
+};
+
+static const struct pck at91sam9260_periphck[] = {
+ { .n = "pioA_clk", .id = 2 },
+ { .n = "pioB_clk", .id = 3 },
+ { .n = "pioC_clk", .id = 4 },
+ { .n = "adc_clk", .id = 5 },
+ { .n = "usart0_clk", .id = 6 },
+ { .n = "usart1_clk", .id = 7 },
+ { .n = "usart2_clk", .id = 8 },
+ { .n = "mci0_clk", .id = 9 },
+ { .n = "udc_clk", .id = 10 },
+ { .n = "twi0_clk", .id = 11 },
+ { .n = "spi0_clk", .id = 12 },
+ { .n = "spi1_clk", .id = 13 },
+ { .n = "ssc0_clk", .id = 14 },
+ { .n = "tc0_clk", .id = 17 },
+ { .n = "tc1_clk", .id = 18 },
+ { .n = "tc2_clk", .id = 19 },
+ { .n = "ohci_clk", .id = 20 },
+ { .n = "macb0_clk", .id = 21 },
+ { .n = "isi_clk", .id = 22 },
+ { .n = "usart3_clk", .id = 23 },
+ { .n = "uart0_clk", .id = 24 },
+ { .n = "uart1_clk", .id = 25 },
+ { .n = "tc3_clk", .id = 26 },
+ { .n = "tc4_clk", .id = 27 },
+ { .n = "tc5_clk", .id = 28 },
+};
+
+static struct at91sam926x_data at91sam9260_data = {
+ .plla_layout = &at91rm9200_pll_layout,
+ .plla_characteristics = &sam9260_plla_characteristics,
+ .pllb_layout = &at91rm9200_pll_layout,
+ .pllb_characteristics = &sam9260_pllb_characteristics,
+ .mck_characteristics = &sam9260_mck_characteristics,
+ .sck = at91sam9260_systemck,
+ .num_sck = ARRAY_SIZE(at91sam9260_systemck),
+ .pck = at91sam9260_periphck,
+ .num_pck = ARRAY_SIZE(at91sam9260_periphck),
+ .num_progck = 2,
+ .has_slck = true,
+};
+
+static const struct clk_master_characteristics sam9g20_mck_characteristics = {
+ .output = { .min = 0, .max = 133000000 },
+ .divisors = { 1, 2, 4, 6 },
+};
+
+static u8 sam9g20_plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
+
+static u16 sam9g20_plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
+
+static struct clk_range sam9g20_plla_outputs[] = {
+ { .min = 745000000, .max = 800000000 },
+ { .min = 695000000, .max = 750000000 },
+ { .min = 645000000, .max = 700000000 },
+ { .min = 595000000, .max = 650000000 },
+ { .min = 545000000, .max = 600000000 },
+ { .min = 495000000, .max = 550000000 },
+ { .min = 445000000, .max = 500000000 },
+ { .min = 400000000, .max = 450000000 },
+};
+
+static const struct clk_pll_characteristics sam9g20_plla_characteristics = {
+ .input = { .min = 2000000, .max = 32000000 },
+ .num_output = ARRAY_SIZE(sam9g20_plla_outputs),
+ .output = sam9g20_plla_outputs,
+ .icpll = sam9g20_plla_icpll,
+ .out = sam9g20_plla_out,
+};
+
+static u8 sam9g20_pllb_out[] = { 0 };
+
+static u16 sam9g20_pllb_icpll[] = { 0 };
+
+static struct clk_range sam9g20_pllb_outputs[] = {
+ { .min = 30000000, .max = 100000000 },
+};
+
+static const struct clk_pll_characteristics sam9g20_pllb_characteristics = {
+ .input = { .min = 2000000, .max = 32000000 },
+ .num_output = ARRAY_SIZE(sam9g20_pllb_outputs),
+ .output = sam9g20_pllb_outputs,
+ .icpll = sam9g20_pllb_icpll,
+ .out = sam9g20_pllb_out,
+};
+
+static struct at91sam926x_data at91sam9g20_data = {
+ .plla_layout = &at91sam9g45_pll_layout,
+ .plla_characteristics = &sam9g20_plla_characteristics,
+ .pllb_layout = &at91sam9g20_pllb_layout,
+ .pllb_characteristics = &sam9g20_pllb_characteristics,
+ .mck_characteristics = &sam9g20_mck_characteristics,
+ .sck = at91sam9260_systemck,
+ .num_sck = ARRAY_SIZE(at91sam9260_systemck),
+ .pck = at91sam9260_periphck,
+ .num_pck = ARRAY_SIZE(at91sam9260_periphck),
+ .num_progck = 2,
+ .has_slck = true,
+};
+
+static const struct clk_master_characteristics sam9261_mck_characteristics = {
+ .output = { .min = 0, .max = 94000000 },
+ .divisors = { 1, 2, 4, 0 },
+};
+
+static struct clk_range sam9261_plla_outputs[] = {
+ { .min = 80000000, .max = 200000000 },
+ { .min = 190000000, .max = 240000000 },
+};
+
+static const struct clk_pll_characteristics sam9261_plla_characteristics = {
+ .input = { .min = 1000000, .max = 32000000 },
+ .num_output = ARRAY_SIZE(sam9261_plla_outputs),
+ .output = sam9261_plla_outputs,
+ .icpll = sam9260_plla_icpll,
+ .out = sam9260_plla_out,
+};
+
+static u8 sam9261_pllb_out[] = { 1 };
+
+static u16 sam9261_pllb_icpll[] = { 1 };
+
+static struct clk_range sam9261_pllb_outputs[] = {
+ { .min = 70000000, .max = 130000000 },
+};
+
+static const struct clk_pll_characteristics sam9261_pllb_characteristics = {
+ .input = { .min = 1000000, .max = 5000000 },
+ .num_output = ARRAY_SIZE(sam9261_pllb_outputs),
+ .output = sam9261_pllb_outputs,
+ .icpll = sam9261_pllb_icpll,
+ .out = sam9261_pllb_out,
+};
+
+static const struct sck at91sam9261_systemck[] = {
+ { .n = "uhpck", .p = "usbck", .id = 6 },
+ { .n = "udpck", .p = "usbck", .id = 7 },
+ { .n = "pck0", .p = "prog0", .id = 8 },
+ { .n = "pck1", .p = "prog1", .id = 9 },
+ { .n = "pck2", .p = "prog2", .id = 10 },
+ { .n = "pck3", .p = "prog3", .id = 11 },
+ { .n = "hclk0", .p = "masterck", .id = 16 },
+ { .n = "hclk1", .p = "masterck", .id = 17 },
+};
+
+static const struct pck at91sam9261_periphck[] = {
+ { .n = "pioA_clk", .id = 2, },
+ { .n = "pioB_clk", .id = 3, },
+ { .n = "pioC_clk", .id = 4, },
+ { .n = "usart0_clk", .id = 6, },
+ { .n = "usart1_clk", .id = 7, },
+ { .n = "usart2_clk", .id = 8, },
+ { .n = "mci0_clk", .id = 9, },
+ { .n = "udc_clk", .id = 10, },
+ { .n = "twi0_clk", .id = 11, },
+ { .n = "spi0_clk", .id = 12, },
+ { .n = "spi1_clk", .id = 13, },
+ { .n = "ssc0_clk", .id = 14, },
+ { .n = "ssc1_clk", .id = 15, },
+ { .n = "ssc2_clk", .id = 16, },
+ { .n = "tc0_clk", .id = 17, },
+ { .n = "tc1_clk", .id = 18, },
+ { .n = "tc2_clk", .id = 19, },
+ { .n = "ohci_clk", .id = 20, },
+ { .n = "lcd_clk", .id = 21, },
+};
+
+static struct at91sam926x_data at91sam9261_data = {
+ .plla_layout = &at91rm9200_pll_layout,
+ .plla_characteristics = &sam9261_plla_characteristics,
+ .pllb_layout = &at91rm9200_pll_layout,
+ .pllb_characteristics = &sam9261_pllb_characteristics,
+ .mck_characteristics = &sam9261_mck_characteristics,
+ .sck = at91sam9261_systemck,
+ .num_sck = ARRAY_SIZE(at91sam9261_systemck),
+ .pck = at91sam9261_periphck,
+ .num_pck = ARRAY_SIZE(at91sam9261_periphck),
+ .num_progck = 4,
+};
+
+static const struct clk_master_characteristics sam9263_mck_characteristics = {
+ .output = { .min = 0, .max = 120000000 },
+ .divisors = { 1, 2, 4, 0 },
+};
+
+static struct clk_range sam9263_pll_outputs[] = {
+ { .min = 80000000, .max = 200000000 },
+ { .min = 190000000, .max = 240000000 },
+};
+
+static const struct clk_pll_characteristics sam9263_pll_characteristics = {
+ .input = { .min = 1000000, .max = 32000000 },
+ .num_output = ARRAY_SIZE(sam9263_pll_outputs),
+ .output = sam9263_pll_outputs,
+ .icpll = sam9260_plla_icpll,
+ .out = sam9260_plla_out,
+};
+
+static const struct sck at91sam9263_systemck[] = {
+ { .n = "uhpck", .p = "usbck", .id = 6 },
+ { .n = "udpck", .p = "usbck", .id = 7 },
+ { .n = "pck0", .p = "prog0", .id = 8 },
+ { .n = "pck1", .p = "prog1", .id = 9 },
+ { .n = "pck2", .p = "prog2", .id = 10 },
+ { .n = "pck3", .p = "prog3", .id = 11 },
+};
+
+static const struct pck at91sam9263_periphck[] = {
+ { .n = "pioA_clk", .id = 2, },
+ { .n = "pioB_clk", .id = 3, },
+ { .n = "pioCDE_clk", .id = 4, },
+ { .n = "usart0_clk", .id = 7, },
+ { .n = "usart1_clk", .id = 8, },
+ { .n = "usart2_clk", .id = 9, },
+ { .n = "mci0_clk", .id = 10, },
+ { .n = "mci1_clk", .id = 11, },
+ { .n = "can_clk", .id = 12, },
+ { .n = "twi0_clk", .id = 13, },
+ { .n = "spi0_clk", .id = 14, },
+ { .n = "spi1_clk", .id = 15, },
+ { .n = "ssc0_clk", .id = 16, },
+ { .n = "ssc1_clk", .id = 17, },
+ { .n = "ac97_clk", .id = 18, },
+ { .n = "tcb_clk", .id = 19, },
+ { .n = "pwm_clk", .id = 20, },
+ { .n = "macb0_clk", .id = 21, },
+ { .n = "g2de_clk", .id = 23, },
+ { .n = "udc_clk", .id = 24, },
+ { .n = "isi_clk", .id = 25, },
+ { .n = "lcd_clk", .id = 26, },
+ { .n = "dma_clk", .id = 27, },
+ { .n = "ohci_clk", .id = 29, },
+};
+
+static struct at91sam926x_data at91sam9263_data = {
+ .plla_layout = &at91rm9200_pll_layout,
+ .plla_characteristics = &sam9263_pll_characteristics,
+ .pllb_layout = &at91rm9200_pll_layout,
+ .pllb_characteristics = &sam9263_pll_characteristics,
+ .mck_characteristics = &sam9263_mck_characteristics,
+ .sck = at91sam9263_systemck,
+ .num_sck = ARRAY_SIZE(at91sam9263_systemck),
+ .pck = at91sam9263_periphck,
+ .num_pck = ARRAY_SIZE(at91sam9263_periphck),
+ .num_progck = 4,
+};
+
+static void __init at91sam926x_pmc_setup(struct device_node *np,
+ struct at91sam926x_data *data)
+{
+ const char *slowxtal_name, *mainxtal_name;
+ struct pmc_data *at91sam9260_pmc;
+ u32 usb_div[] = { 1, 2, 4, 0 };
+ const char *parent_names[6];
+ const char *slck_name;
+ struct regmap *regmap;
+ struct clk_hw *hw;
+ unsigned int i;
+ bool bypass;
+
+ i = of_property_match_string(np, "clock-names", "slow_xtal");
+ if (i < 0)
+ return;
+
+ slowxtal_name = of_clk_get_parent_name(np, i);
+
+ i = of_property_match_string(np, "clock-names", "main_xtal");
+ if (i < 0)
+ return;
+ mainxtal_name = of_clk_get_parent_name(np, i);
+
+ regmap = syscon_node_to_regmap(np);
+ if (IS_ERR(regmap))
+ return;
+
+ at91sam9260_pmc = pmc_data_allocate(PMC_MAIN + 1,
+ ndck(data->sck, data->num_sck),
+ ndck(data->pck, data->num_pck), 0);
+ if (!at91sam9260_pmc)
+ return;
+
+ bypass = of_property_read_bool(np, "atmel,osc-bypass");
+
+ hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
+ bypass);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9260_pmc->chws[PMC_MAIN] = hw;
+
+ if (data->has_slck) {
+ hw = clk_hw_register_fixed_rate_with_accuracy(NULL,
+ "slow_rc_osc",
+ NULL, 0, 32768,
+ 50000000);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ parent_names[0] = "slow_rc_osc";
+ parent_names[1] = "slow_xtal";
+ hw = at91_clk_register_sam9260_slow(regmap, "slck",
+ parent_names, 2);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9260_pmc->chws[PMC_SLOW] = hw;
+ slck_name = "slck";
+ } else {
+ slck_name = slowxtal_name;
+ }
+
+ hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
+ data->plla_layout,
+ data->plla_characteristics);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
+ data->pllb_layout,
+ data->pllb_characteristics);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ parent_names[0] = slck_name;
+ parent_names[1] = "mainck";
+ parent_names[2] = "pllack";
+ parent_names[3] = "pllbck";
+ hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
+ &at91rm9200_master_layout,
+ data->mck_characteristics);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9260_pmc->chws[PMC_MCK] = hw;
+
+ hw = at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ parent_names[0] = slck_name;
+ parent_names[1] = "mainck";
+ parent_names[2] = "pllack";
+ parent_names[3] = "pllbck";
+ for (i = 0; i < data->num_progck; i++) {
+ char name[6];
+
+ snprintf(name, sizeof(name), "prog%d", i);
+
+ hw = at91_clk_register_programmable(regmap, name,
+ parent_names, 4, i,
+ &at91rm9200_programmable_layout);
+ if (IS_ERR(hw))
+ goto err_free;
+ }
+
+ for (i = 0; i < data->num_sck; i++) {
+ hw = at91_clk_register_system(regmap, data->sck[i].n,
+ data->sck[i].p,
+ data->sck[i].id);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9260_pmc->shws[data->sck[i].id] = hw;
+ }
+
+ for (i = 0; i < data->num_pck; i++) {
+ hw = at91_clk_register_peripheral(regmap,
+ data->pck[i].n,
+ "masterck",
+ data->pck[i].id);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9260_pmc->phws[data->pck[i].id] = hw;
+ }
+
+ of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9260_pmc);
+
+ return;
+
+err_free:
+ pmc_data_free(at91sam9260_pmc);
+}
+
+static void __init at91sam9260_pmc_setup(struct device_node *np)
+{
+ at91sam926x_pmc_setup(np, &at91sam9260_data);
+}
+CLK_OF_DECLARE_DRIVER(at91sam9260_pmc, "atmel,at91sam9260-pmc",
+ at91sam9260_pmc_setup);
+
+static void __init at91sam9261_pmc_setup(struct device_node *np)
+{
+ at91sam926x_pmc_setup(np, &at91sam9261_data);
+}
+CLK_OF_DECLARE_DRIVER(at91sam9261_pmc, "atmel,at91sam9261-pmc",
+ at91sam9261_pmc_setup);
+
+static void __init at91sam9263_pmc_setup(struct device_node *np)
+{
+ at91sam926x_pmc_setup(np, &at91sam9263_data);
+}
+CLK_OF_DECLARE_DRIVER(at91sam9263_pmc, "atmel,at91sam9263-pmc",
+ at91sam9263_pmc_setup);
+
+static void __init at91sam9g20_pmc_setup(struct device_node *np)
+{
+ at91sam926x_pmc_setup(np, &at91sam9g20_data);
+}
+CLK_OF_DECLARE_DRIVER(at91sam9g20_pmc, "atmel,at91sam9g20-pmc",
+ at91sam9g20_pmc_setup);
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* Re: [PATCH v2 12/22] clk: at91: add at91sam9260 PMC driver
2018-10-16 14:21 ` [PATCH v2 12/22] clk: at91: add at91sam9260 " Alexandre Belloni
@ 2018-10-17 17:50 ` Stephen Boyd
0 siblings, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2018-10-17 17:50 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Quoting Alexandre Belloni (2018-10-16 07:21:50)
> Add a driver for the PMC clocks of the at91sam9260, at91sam9261,
> at91am9263 and at91sam9g20 SoCs.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v2 13/22] clk: at91: add at91sam9x5 PMCs driver
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (11 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 12/22] clk: at91: add at91sam9260 " Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-17 17:50 ` Stephen Boyd
2018-10-16 14:21 ` [PATCH v2 14/22] clk: at91: add at91sam9rl PMC driver Alexandre Belloni
` (9 subsequent siblings)
22 siblings, 1 reply; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Add a driver for the PMC clocks of the at91sam9x5 SoCs
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/at91sam9x5.c | 309 ++++++++++++++++++++++++++++++++++
2 files changed, 310 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/at91/at91sam9x5.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 08399003c752..78dc71d653de 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -14,6 +14,6 @@ obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o
obj-$(CONFIG_HAVE_AT91_GENERATED_CLK) += clk-generated.o
obj-$(CONFIG_HAVE_AT91_I2S_MUX_CLK) += clk-i2s-mux.o
-obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o
+obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9x5.o
obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o
diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c
new file mode 100644
index 000000000000..3cdf227ce159
--- /dev/null
+++ b/drivers/clk/at91/at91sam9x5.c
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/at91.h>
+
+#include "pmc.h"
+
+static const struct clk_master_characteristics mck_characteristics = {
+ .output = { .min = 0, .max = 133333333 },
+ .divisors = { 1, 2, 4, 3 },
+ .have_div3_pres = 1,
+};
+
+static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
+
+static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
+
+static struct clk_range plla_outputs[] = {
+ { .min = 745000000, .max = 800000000 },
+ { .min = 695000000, .max = 750000000 },
+ { .min = 645000000, .max = 700000000 },
+ { .min = 595000000, .max = 650000000 },
+ { .min = 545000000, .max = 600000000 },
+ { .min = 495000000, .max = 555000000 },
+ { .min = 445000000, .max = 500000000 },
+ { .min = 400000000, .max = 450000000 },
+};
+
+static const struct clk_pll_characteristics plla_characteristics = {
+ .input = { .min = 2000000, .max = 32000000 },
+ .num_output = ARRAY_SIZE(plla_outputs),
+ .output = plla_outputs,
+ .icpll = plla_icpll,
+ .out = plla_out,
+};
+
+static const struct {
+ char *n;
+ char *p;
+ u8 id;
+} at91sam9x5_systemck[] = {
+ { .n = "ddrck", .p = "masterck", .id = 2 },
+ { .n = "smdck", .p = "smdclk", .id = 4 },
+ { .n = "uhpck", .p = "usbck", .id = 6 },
+ { .n = "udpck", .p = "usbck", .id = 7 },
+ { .n = "pck0", .p = "prog0", .id = 8 },
+ { .n = "pck1", .p = "prog1", .id = 9 },
+};
+
+struct pck {
+ char *n;
+ u8 id;
+};
+
+static const struct pck at91sam9x5_periphck[] = {
+ { .n = "pioAB_clk", .id = 2, },
+ { .n = "pioCD_clk", .id = 3, },
+ { .n = "smd_clk", .id = 4, },
+ { .n = "usart0_clk", .id = 5, },
+ { .n = "usart1_clk", .id = 6, },
+ { .n = "usart2_clk", .id = 7, },
+ { .n = "twi0_clk", .id = 9, },
+ { .n = "twi1_clk", .id = 10, },
+ { .n = "twi2_clk", .id = 11, },
+ { .n = "mci0_clk", .id = 12, },
+ { .n = "spi0_clk", .id = 13, },
+ { .n = "spi1_clk", .id = 14, },
+ { .n = "uart0_clk", .id = 15, },
+ { .n = "uart1_clk", .id = 16, },
+ { .n = "tcb0_clk", .id = 17, },
+ { .n = "pwm_clk", .id = 18, },
+ { .n = "adc_clk", .id = 19, },
+ { .n = "dma0_clk", .id = 20, },
+ { .n = "dma1_clk", .id = 21, },
+ { .n = "uhphs_clk", .id = 22, },
+ { .n = "udphs_clk", .id = 23, },
+ { .n = "mci1_clk", .id = 26, },
+ { .n = "ssc0_clk", .id = 28, },
+};
+
+static const struct pck at91sam9g15_periphck[] = {
+ { .n = "lcdc_clk", .id = 25, },
+ { /* sentinel */}
+};
+
+static const struct pck at91sam9g25_periphck[] = {
+ { .n = "usart3_clk", .id = 8, },
+ { .n = "macb0_clk", .id = 24, },
+ { .n = "isi_clk", .id = 25, },
+ { /* sentinel */}
+};
+
+static const struct pck at91sam9g35_periphck[] = {
+ { .n = "macb0_clk", .id = 24, },
+ { .n = "lcdc_clk", .id = 25, },
+ { /* sentinel */}
+};
+
+static const struct pck at91sam9x25_periphck[] = {
+ { .n = "usart3_clk", .id = 8, },
+ { .n = "macb0_clk", .id = 24, },
+ { .n = "macb1_clk", .id = 27, },
+ { .n = "can0_clk", .id = 29, },
+ { .n = "can1_clk", .id = 30, },
+ { /* sentinel */}
+};
+
+static const struct pck at91sam9x35_periphck[] = {
+ { .n = "macb0_clk", .id = 24, },
+ { .n = "lcdc_clk", .id = 25, },
+ { .n = "can0_clk", .id = 29, },
+ { .n = "can1_clk", .id = 30, },
+ { /* sentinel */}
+};
+
+static void __init at91sam9x5_pmc_setup(struct device_node *np,
+ const struct pck *extra_pcks,
+ bool has_lcdck)
+{
+ struct clk_range range = CLK_RANGE(0, 0);
+ const char *slck_name, *mainxtal_name;
+ struct pmc_data *at91sam9x5_pmc;
+ const char *parent_names[6];
+ struct regmap *regmap;
+ struct clk_hw *hw;
+ unsigned int i;
+ bool bypass;
+
+ i = of_property_match_string(np, "clock-names", "slow_clk");
+ if (i < 0)
+ return;
+
+ slck_name = of_clk_get_parent_name(np, i);
+
+ i = of_property_match_string(np, "clock-names", "main_xtal");
+ if (i < 0)
+ return;
+ mainxtal_name = of_clk_get_parent_name(np, i);
+
+ regmap = syscon_node_to_regmap(np);
+ if (IS_ERR(regmap))
+ return;
+
+ at91sam9x5_pmc = pmc_data_allocate(PMC_MAIN + 1,
+ nck(at91sam9x5_systemck),
+ nck(at91sam9x35_periphck), 0);
+ if (!at91sam9x5_pmc)
+ return;
+
+ hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
+ 50000000);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ bypass = of_property_read_bool(np, "atmel,osc-bypass");
+
+ hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
+ bypass);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ parent_names[0] = "main_rc_osc";
+ parent_names[1] = "main_osc";
+ hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9x5_pmc->chws[PMC_MAIN] = hw;
+
+ hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
+ &at91rm9200_pll_layout, &plla_characteristics);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9x5_pmc->chws[PMC_UTMI] = hw;
+
+ parent_names[0] = slck_name;
+ parent_names[1] = "mainck";
+ parent_names[2] = "plladivck";
+ parent_names[3] = "utmick";
+ hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
+ &at91sam9x5_master_layout,
+ &mck_characteristics);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9x5_pmc->chws[PMC_MCK] = hw;
+
+ parent_names[0] = "plladivck";
+ parent_names[1] = "utmick";
+ hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ parent_names[0] = slck_name;
+ parent_names[1] = "mainck";
+ parent_names[2] = "plladivck";
+ parent_names[3] = "utmick";
+ parent_names[4] = "mck";
+ for (i = 0; i < 2; i++) {
+ char name[6];
+
+ snprintf(name, sizeof(name), "prog%d", i);
+
+ hw = at91_clk_register_programmable(regmap, name,
+ parent_names, 5, i,
+ &at91sam9x5_programmable_layout);
+ if (IS_ERR(hw))
+ goto err_free;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) {
+ hw = at91_clk_register_system(regmap, at91sam9x5_systemck[i].n,
+ at91sam9x5_systemck[i].p,
+ at91sam9x5_systemck[i].id);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9x5_pmc->shws[at91sam9x5_systemck[i].id] = hw;
+ }
+
+ if (has_lcdck) {
+ hw = at91_clk_register_system(regmap, "lcdck", "masterck", 3);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9x5_pmc->shws[3] = hw;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(at91sam9x5_periphck); i++) {
+ hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+ at91sam9x5_periphck[i].n,
+ "masterck",
+ at91sam9x5_periphck[i].id,
+ &range);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9x5_pmc->phws[at91sam9x5_periphck[i].id] = hw;
+ }
+
+ for (i = 0; extra_pcks[i].id; i++) {
+ hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+ extra_pcks[i].n,
+ "masterck",
+ extra_pcks[i].id,
+ &range);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9x5_pmc->phws[extra_pcks[i].id] = hw;
+ }
+
+ of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9x5_pmc);
+
+ return;
+
+err_free:
+ pmc_data_free(at91sam9x5_pmc);
+}
+
+static void __init at91sam9g15_pmc_setup(struct device_node *np)
+{
+ at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true);
+}
+CLK_OF_DECLARE_DRIVER(at91sam9g15_pmc, "atmel,at91sam9g15-pmc",
+ at91sam9g15_pmc_setup);
+
+static void __init at91sam9g25_pmc_setup(struct device_node *np)
+{
+ at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false);
+}
+CLK_OF_DECLARE_DRIVER(at91sam9g25_pmc, "atmel,at91sam9g25-pmc",
+ at91sam9g25_pmc_setup);
+
+static void __init at91sam9g35_pmc_setup(struct device_node *np)
+{
+ at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true);
+}
+CLK_OF_DECLARE_DRIVER(at91sam9g35_pmc, "atmel,at91sam9g35-pmc",
+ at91sam9g35_pmc_setup);
+
+static void __init at91sam9x25_pmc_setup(struct device_node *np)
+{
+ at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false);
+}
+CLK_OF_DECLARE_DRIVER(at91sam9x25_pmc, "atmel,at91sam9x25-pmc",
+ at91sam9x25_pmc_setup);
+
+static void __init at91sam9x35_pmc_setup(struct device_node *np)
+{
+ at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true);
+}
+CLK_OF_DECLARE_DRIVER(at91sam9x35_pmc, "atmel,at91sam9x35-pmc",
+ at91sam9x35_pmc_setup);
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 14/22] clk: at91: add at91sam9rl PMC driver
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (12 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 13/22] clk: at91: add at91sam9x5 PMCs driver Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-17 17:50 ` Stephen Boyd
2018-10-16 14:21 ` [PATCH v2 15/22] clk: at91: move DT compatibility code to its own file Alexandre Belloni
` (8 subsequent siblings)
22 siblings, 1 reply; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Add a driver for the PMC clocks of the at91sam9rl SoC.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/at91sam9rl.c | 171 ++++++++++++++++++++++++++++++++++
2 files changed, 172 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/at91/at91sam9rl.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 78dc71d653de..0752def6271a 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -14,6 +14,6 @@ obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o
obj-$(CONFIG_HAVE_AT91_GENERATED_CLK) += clk-generated.o
obj-$(CONFIG_HAVE_AT91_I2S_MUX_CLK) += clk-i2s-mux.o
-obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9x5.o
+obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o
obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o
diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c
new file mode 100644
index 000000000000..5532fba5825b
--- /dev/null
+++ b/drivers/clk/at91/at91sam9rl.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/at91.h>
+
+#include "pmc.h"
+
+static const struct clk_master_characteristics sam9rl_mck_characteristics = {
+ .output = { .min = 0, .max = 94000000 },
+ .divisors = { 1, 2, 4, 0 },
+};
+
+static u8 sam9rl_plla_out[] = { 0, 2 };
+
+static struct clk_range sam9rl_plla_outputs[] = {
+ { .min = 80000000, .max = 200000000 },
+ { .min = 190000000, .max = 240000000 },
+};
+
+static const struct clk_pll_characteristics sam9rl_plla_characteristics = {
+ .input = { .min = 1000000, .max = 32000000 },
+ .num_output = ARRAY_SIZE(sam9rl_plla_outputs),
+ .output = sam9rl_plla_outputs,
+ .out = sam9rl_plla_out,
+};
+
+static const struct {
+ char *n;
+ char *p;
+ u8 id;
+} at91sam9rl_systemck[] = {
+ { .n = "pck0", .p = "prog0", .id = 8 },
+ { .n = "pck1", .p = "prog1", .id = 9 },
+};
+
+static const struct {
+ char *n;
+ u8 id;
+} at91sam9rl_periphck[] = {
+ { .n = "pioA_clk", .id = 2, },
+ { .n = "pioB_clk", .id = 3, },
+ { .n = "pioC_clk", .id = 4, },
+ { .n = "pioD_clk", .id = 5, },
+ { .n = "usart0_clk", .id = 6, },
+ { .n = "usart1_clk", .id = 7, },
+ { .n = "usart2_clk", .id = 8, },
+ { .n = "usart3_clk", .id = 9, },
+ { .n = "mci0_clk", .id = 10, },
+ { .n = "twi0_clk", .id = 11, },
+ { .n = "twi1_clk", .id = 12, },
+ { .n = "spi0_clk", .id = 13, },
+ { .n = "ssc0_clk", .id = 14, },
+ { .n = "ssc1_clk", .id = 15, },
+ { .n = "tc0_clk", .id = 16, },
+ { .n = "tc1_clk", .id = 17, },
+ { .n = "tc2_clk", .id = 18, },
+ { .n = "pwm_clk", .id = 19, },
+ { .n = "adc_clk", .id = 20, },
+ { .n = "dma0_clk", .id = 21, },
+ { .n = "udphs_clk", .id = 22, },
+ { .n = "lcd_clk", .id = 23, },
+};
+
+static void __init at91sam9rl_pmc_setup(struct device_node *np)
+{
+ const char *slck_name, *mainxtal_name;
+ struct pmc_data *at91sam9rl_pmc;
+ const char *parent_names[6];
+ struct regmap *regmap;
+ struct clk_hw *hw;
+ unsigned int i;
+
+ i = of_property_match_string(np, "clock-names", "slow_clk");
+ if (i < 0)
+ return;
+
+ slck_name = of_clk_get_parent_name(np, i);
+
+ i = of_property_match_string(np, "clock-names", "main_xtal");
+ if (i < 0)
+ return;
+ mainxtal_name = of_clk_get_parent_name(np, i);
+
+ regmap = syscon_node_to_regmap(np);
+ if (IS_ERR(regmap))
+ return;
+
+ at91sam9rl_pmc = pmc_data_allocate(PMC_MAIN + 1,
+ nck(at91sam9rl_systemck),
+ nck(at91sam9rl_periphck), 0);
+ if (!at91sam9rl_pmc)
+ return;
+
+ hw = at91_clk_register_rm9200_main(regmap, "mainck", mainxtal_name);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9rl_pmc->chws[PMC_MAIN] = hw;
+
+ hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
+ &at91rm9200_pll_layout,
+ &sam9rl_plla_characteristics);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9rl_pmc->chws[PMC_UTMI] = hw;
+
+ parent_names[0] = slck_name;
+ parent_names[1] = "mainck";
+ parent_names[2] = "pllack";
+ parent_names[3] = "utmick";
+ hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
+ &at91rm9200_master_layout,
+ &sam9rl_mck_characteristics);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9rl_pmc->chws[PMC_MCK] = hw;
+
+ parent_names[0] = slck_name;
+ parent_names[1] = "mainck";
+ parent_names[2] = "pllack";
+ parent_names[3] = "utmick";
+ parent_names[4] = "masterck";
+ for (i = 0; i < 2; i++) {
+ char name[6];
+
+ snprintf(name, sizeof(name), "prog%d", i);
+
+ hw = at91_clk_register_programmable(regmap, name,
+ parent_names, 5, i,
+ &at91rm9200_programmable_layout);
+ if (IS_ERR(hw))
+ goto err_free;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(at91sam9rl_systemck); i++) {
+ hw = at91_clk_register_system(regmap, at91sam9rl_systemck[i].n,
+ at91sam9rl_systemck[i].p,
+ at91sam9rl_systemck[i].id);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9rl_pmc->shws[at91sam9rl_systemck[i].id] = hw;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) {
+ hw = at91_clk_register_peripheral(regmap,
+ at91sam9rl_periphck[i].n,
+ "masterck",
+ at91sam9rl_periphck[i].id);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ at91sam9rl_pmc->phws[at91sam9rl_periphck[i].id] = hw;
+ }
+
+ of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9rl_pmc);
+
+ return;
+
+err_free:
+ pmc_data_free(at91sam9rl_pmc);
+}
+CLK_OF_DECLARE_DRIVER(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup);
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 15/22] clk: at91: move DT compatibility code to its own file
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (13 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 14/22] clk: at91: add at91sam9rl PMC driver Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-17 17:50 ` Stephen Boyd
2018-10-16 14:21 ` [PATCH v2 16/22] ARM: dts: at91: sama5d4: switch to new clock bindings Alexandre Belloni
` (7 subsequent siblings)
22 siblings, 1 reply; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Move all the DT backward compatibility code to its own file so it can be
deleted later.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-audio-pll.c | 70 --
drivers/clk/at91/clk-generated.c | 65 --
drivers/clk/at91/clk-h32mx.c | 22 -
drivers/clk/at91/clk-i2s-mux.c | 38 --
drivers/clk/at91/clk-main.c | 104 ---
drivers/clk/at91/clk-master.c | 82 ---
drivers/clk/at91/clk-peripheral.c | 77 ---
drivers/clk/at91/clk-pll.c | 163 -----
drivers/clk/at91/clk-plldiv.c | 25 -
drivers/clk/at91/clk-programmable.c | 67 --
drivers/clk/at91/clk-slow.c | 30 -
drivers/clk/at91/clk-smd.c | 32 -
drivers/clk/at91/clk-system.c | 37 --
drivers/clk/at91/clk-usb.c | 88 ---
drivers/clk/at91/clk-utmi.c | 43 --
drivers/clk/at91/dt-compat.c | 961 ++++++++++++++++++++++++++++
17 files changed, 962 insertions(+), 944 deletions(-)
create mode 100644 drivers/clk/at91/dt-compat.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 0752def6271a..c75df1cad60e 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -3,7 +3,7 @@
# Makefile for at91 specific clk
#
-obj-y += pmc.o sckc.o
+obj-y += pmc.o sckc.o dt-compat.o
obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o
obj-y += clk-system.o clk-peripheral.o clk-programmable.o
diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c
index f326023a50a3..96e3c6405351 100644
--- a/drivers/clk/at91/clk-audio-pll.c
+++ b/drivers/clk/at91/clk-audio-pll.c
@@ -474,26 +474,6 @@ at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,
return &frac_ck->hw;
}
-static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)
-{
- struct clk_hw *hw;
- const char *name = np->name;
- const char *parent_name;
- struct regmap *regmap;
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- parent_name = of_clk_get_parent_name(np, 0);
-
- hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
-}
-
struct clk_hw * __init
at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,
const char *parent_name)
@@ -525,26 +505,6 @@ at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,
return &apad_ck->hw;
}
-static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
-{
- struct clk_hw *hw;
- const char *name = np->name;
- const char *parent_name;
- struct regmap *regmap;
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- parent_name = of_clk_get_parent_name(np, 0);
-
- hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
-}
-
struct clk_hw * __init
at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
const char *parent_name)
@@ -575,33 +535,3 @@ at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
return &apmc_ck->hw;
}
-
-static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
-{
- struct clk_hw *hw;
- const char *name = np->name;
- const char *parent_name;
- struct regmap *regmap;
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- parent_name = of_clk_get_parent_name(np, 0);
-
- hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
-}
-
-CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup,
- "atmel,sama5d2-clk-audio-pll-frac",
- of_sama5d2_clk_audio_pll_frac_setup);
-CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup,
- "atmel,sama5d2-clk-audio-pll-pad",
- of_sama5d2_clk_audio_pll_pad_setup);
-CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup,
- "atmel,sama5d2-clk-audio-pll-pmc",
- of_sama5d2_clk_audio_pll_pmc_setup);
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
index 0fe4d7f04225..66e7f7baf958 100644
--- a/drivers/clk/at91/clk-generated.c
+++ b/drivers/clk/at91/clk-generated.c
@@ -20,15 +20,8 @@
#include "pmc.h"
-#define PERIPHERAL_MAX 64
-#define PERIPHERAL_ID_MIN 2
-
-#define GENERATED_SOURCE_MAX 6
#define GENERATED_MAX_DIV 255
-#define GCK_ID_I2S0 54
-#define GCK_ID_I2S1 55
-#define GCK_ID_CLASSD 59
#define GCK_INDEX_DT_AUDIO_PLL 5
struct clk_generated {
@@ -318,61 +311,3 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
return hw;
}
-
-static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
-{
- int num;
- u32 id;
- const char *name;
- struct clk_hw *hw;
- unsigned int num_parents;
- const char *parent_names[GENERATED_SOURCE_MAX];
- struct device_node *gcknp;
- struct clk_range range = CLK_RANGE(0, 0);
- struct regmap *regmap;
-
- num_parents = of_clk_get_parent_count(np);
- if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
- return;
-
- of_clk_parent_fill(np, parent_names, num_parents);
-
- num = of_get_child_count(np);
- if (!num || num > PERIPHERAL_MAX)
- return;
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- for_each_child_of_node(np, gcknp) {
- bool pll_audio = false;
-
- if (of_property_read_u32(gcknp, "reg", &id))
- continue;
-
- if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
- continue;
-
- if (of_property_read_string(np, "clock-output-names", &name))
- name = gcknp->name;
-
- of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
- &range);
-
- if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&
- (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||
- id == GCK_ID_CLASSD))
- pll_audio = true;
-
- hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, name,
- parent_names, num_parents,
- id, pll_audio, &range);
- if (IS_ERR(hw))
- continue;
-
- of_clk_add_hw_provider(gcknp, of_clk_hw_simple_get, hw);
- }
-}
-CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated",
- of_sama5d2_clk_generated_setup);
diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c
index a3274648b6c0..f0a2c6baab37 100644
--- a/drivers/clk/at91/clk-h32mx.c
+++ b/drivers/clk/at91/clk-h32mx.c
@@ -115,25 +115,3 @@ at91_clk_register_h32mx(struct regmap *regmap, const char *name,
return &h32mxclk->hw;
}
-
-static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
-{
- struct clk_hw *hw;
- const char *name = np->name;
- const char *parent_name;
- struct regmap *regmap;
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- parent_name = of_clk_get_parent_name(np, 0);
-
- hw = at91_clk_register_h32mx(regmap, name, parent_name);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
-}
-CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx",
- of_sama5d4_clk_h32mx_setup);
diff --git a/drivers/clk/at91/clk-i2s-mux.c b/drivers/clk/at91/clk-i2s-mux.c
index ed9e96938589..dfdffa5409e6 100644
--- a/drivers/clk/at91/clk-i2s-mux.c
+++ b/drivers/clk/at91/clk-i2s-mux.c
@@ -14,8 +14,6 @@
#include <soc/at91/atmel-sfr.h>
-#define I2S_BUS_NR 2
-
struct clk_i2s_mux {
struct clk_hw hw;
struct regmap *regmap;
@@ -78,39 +76,3 @@ at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,
return &i2s_ck->hw;
}
-
-static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np)
-{
- struct regmap *regmap_sfr;
- u8 bus_id;
- const char *parent_names[2];
- struct device_node *i2s_mux_np;
- struct clk_hw *hw;
- int ret;
-
- regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
- if (IS_ERR(regmap_sfr))
- return;
-
- for_each_child_of_node(np, i2s_mux_np) {
- if (of_property_read_u8(i2s_mux_np, "reg", &bus_id))
- continue;
-
- if (bus_id > I2S_BUS_NR)
- continue;
-
- ret = of_clk_parent_fill(i2s_mux_np, parent_names, 2);
- if (ret != 2)
- continue;
-
- hw = at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name,
- parent_names, 2, bus_id);
- if (IS_ERR(hw))
- continue;
-
- of_clk_add_hw_provider(i2s_mux_np, of_clk_hw_simple_get, hw);
- }
-}
-
-CLK_OF_DECLARE(sama5d2_clk_i2s_mux, "atmel,sama5d2-clk-i2s-mux",
- of_sama5d2_clk_i2s_mux_setup);
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
index 82184009137d..7ac0facdb28b 100644
--- a/drivers/clk/at91/clk-main.c
+++ b/drivers/clk/at91/clk-main.c
@@ -12,7 +12,6 @@
#include <linux/clkdev.h>
#include <linux/clk/at91_pmc.h>
#include <linux/delay.h>
-#include <linux/of.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
@@ -171,31 +170,6 @@ at91_clk_register_main_osc(struct regmap *regmap,
return hw;
}
-static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
-{
- struct clk_hw *hw;
- const char *name = np->name;
- const char *parent_name;
- struct regmap *regmap;
- bool bypass;
-
- of_property_read_string(np, "clock-output-names", &name);
- bypass = of_property_read_bool(np, "atmel,osc-bypass");
- parent_name = of_clk_get_parent_name(np, 0);
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- hw = at91_clk_register_main_osc(regmap, name, parent_name, bypass);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
-}
-CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc",
- of_at91rm9200_clk_main_osc_setup);
-
static bool clk_main_rc_osc_ready(struct regmap *regmap)
{
unsigned int status;
@@ -313,32 +287,6 @@ at91_clk_register_main_rc_osc(struct regmap *regmap,
return hw;
}
-static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np)
-{
- struct clk_hw *hw;
- u32 frequency = 0;
- u32 accuracy = 0;
- const char *name = np->name;
- struct regmap *regmap;
-
- of_property_read_string(np, "clock-output-names", &name);
- of_property_read_u32(np, "clock-frequency", &frequency);
- of_property_read_u32(np, "clock-accuracy", &accuracy);
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- hw = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
-}
-CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc",
- of_at91sam9x5_clk_main_rc_osc_setup);
-
-
static int clk_main_probe_frequency(struct regmap *regmap)
{
unsigned long prep_time, timeout;
@@ -442,29 +390,6 @@ at91_clk_register_rm9200_main(struct regmap *regmap,
return hw;
}
-static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
-{
- struct clk_hw *hw;
- const char *parent_name;
- const char *name = np->name;
- struct regmap *regmap;
-
- parent_name = of_clk_get_parent_name(np, 0);
- of_property_read_string(np, "clock-output-names", &name);
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- hw = at91_clk_register_rm9200_main(regmap, name, parent_name);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
-}
-CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
- of_at91rm9200_clk_main_setup);
-
static inline bool clk_sam9x5_main_ready(struct regmap *regmap)
{
unsigned int status;
@@ -583,32 +508,3 @@ at91_clk_register_sam9x5_main(struct regmap *regmap,
return hw;
}
-
-static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
-{
- struct clk_hw *hw;
- const char *parent_names[2];
- unsigned int num_parents;
- const char *name = np->name;
- struct regmap *regmap;
-
- num_parents = of_clk_get_parent_count(np);
- if (num_parents == 0 || num_parents > 2)
- return;
-
- of_clk_parent_fill(np, parent_names, num_parents);
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- of_property_read_string(np, "clock-output-names", &name);
-
- hw = at91_clk_register_sam9x5_main(regmap, name, parent_names,
- num_parents);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
-}
-CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main",
- of_at91sam9x5_clk_main_setup);
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index 088044bb6ea2..eb53b4a8fab6 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -17,8 +17,6 @@
#include "pmc.h"
-#define MASTER_SOURCE_MAX 4
-
#define MASTER_PRES_MASK 0x7
#define MASTER_PRES_MAX MASTER_PRES_MASK
#define MASTER_DIV_SHIFT 8
@@ -159,83 +157,3 @@ const struct clk_master_layout at91sam9x5_master_layout = {
.mask = 0x373,
.pres_shift = 4,
};
-
-
-static struct clk_master_characteristics * __init
-of_at91_clk_master_get_characteristics(struct device_node *np)
-{
- struct clk_master_characteristics *characteristics;
-
- characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
- if (!characteristics)
- return NULL;
-
- if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output))
- goto out_free_characteristics;
-
- of_property_read_u32_array(np, "atmel,clk-divisors",
- characteristics->divisors, 4);
-
- characteristics->have_div3_pres =
- of_property_read_bool(np, "atmel,master-clk-have-div3-pres");
-
- return characteristics;
-
-out_free_characteristics:
- kfree(characteristics);
- return NULL;
-}
-
-static void __init
-of_at91_clk_master_setup(struct device_node *np,
- const struct clk_master_layout *layout)
-{
- struct clk_hw *hw;
- unsigned int num_parents;
- const char *parent_names[MASTER_SOURCE_MAX];
- const char *name = np->name;
- struct clk_master_characteristics *characteristics;
- struct regmap *regmap;
-
- num_parents = of_clk_get_parent_count(np);
- if (num_parents == 0 || num_parents > MASTER_SOURCE_MAX)
- return;
-
- of_clk_parent_fill(np, parent_names, num_parents);
-
- of_property_read_string(np, "clock-output-names", &name);
-
- characteristics = of_at91_clk_master_get_characteristics(np);
- if (!characteristics)
- return;
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- hw = at91_clk_register_master(regmap, name, num_parents,
- parent_names, layout,
- characteristics);
- if (IS_ERR(hw))
- goto out_free_characteristics;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
- return;
-
-out_free_characteristics:
- kfree(characteristics);
-}
-
-static void __init of_at91rm9200_clk_master_setup(struct device_node *np)
-{
- of_at91_clk_master_setup(np, &at91rm9200_master_layout);
-}
-CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master",
- of_at91rm9200_clk_master_setup);
-
-static void __init of_at91sam9x5_clk_master_setup(struct device_node *np)
-{
- of_at91_clk_master_setup(np, &at91sam9x5_master_layout);
-}
-CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master",
- of_at91sam9x5_clk_master_setup);
diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c
index cb41d06a2481..65c1defa78e4 100644
--- a/drivers/clk/at91/clk-peripheral.c
+++ b/drivers/clk/at91/clk-peripheral.c
@@ -19,11 +19,6 @@
DEFINE_SPINLOCK(pmc_pcr_lock);
-#define PERIPHERAL_MAX 64
-
-#define PERIPHERAL_AT91RM9200 0
-#define PERIPHERAL_AT91SAM9X5 1
-
#define PERIPHERAL_ID_MIN 2
#define PERIPHERAL_ID_MAX 31
#define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
@@ -374,75 +369,3 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,
return hw;
}
-
-static void __init
-of_at91_clk_periph_setup(struct device_node *np, u8 type)
-{
- int num;
- u32 id;
- struct clk_hw *hw;
- const char *parent_name;
- const char *name;
- struct device_node *periphclknp;
- struct regmap *regmap;
-
- parent_name = of_clk_get_parent_name(np, 0);
- if (!parent_name)
- return;
-
- num = of_get_child_count(np);
- if (!num || num > PERIPHERAL_MAX)
- return;
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- for_each_child_of_node(np, periphclknp) {
- if (of_property_read_u32(periphclknp, "reg", &id))
- continue;
-
- if (id >= PERIPHERAL_MAX)
- continue;
-
- if (of_property_read_string(np, "clock-output-names", &name))
- name = periphclknp->name;
-
- if (type == PERIPHERAL_AT91RM9200) {
- hw = at91_clk_register_peripheral(regmap, name,
- parent_name, id);
- } else {
- struct clk_range range = CLK_RANGE(0, 0);
-
- of_at91_get_clk_range(periphclknp,
- "atmel,clk-output-range",
- &range);
-
- hw = at91_clk_register_sam9x5_peripheral(regmap,
- &pmc_pcr_lock,
- name,
- parent_name,
- id, &range);
- }
-
- if (IS_ERR(hw))
- continue;
-
- of_clk_add_hw_provider(periphclknp, of_clk_hw_simple_get, hw);
- }
-}
-
-static void __init of_at91rm9200_clk_periph_setup(struct device_node *np)
-{
- of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200);
-}
-CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral",
- of_at91rm9200_clk_periph_setup);
-
-static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np)
-{
- of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5);
-}
-CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral",
- of_at91sam9x5_clk_periph_setup);
-
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
index 31fff0b9d5c2..f19eed31595a 100644
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -340,166 +340,3 @@ const struct clk_pll_layout sama5d3_pll_layout = {
.mul_shift = 18,
.mul_mask = 0x7F,
};
-
-
-static struct clk_pll_characteristics * __init
-of_at91_clk_pll_get_characteristics(struct device_node *np)
-{
- int i;
- int offset;
- u32 tmp;
- int num_output;
- u32 num_cells;
- struct clk_range input;
- struct clk_range *output;
- u8 *out = NULL;
- u16 *icpll = NULL;
- struct clk_pll_characteristics *characteristics;
-
- if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
- return NULL;
-
- if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
- &num_cells))
- return NULL;
-
- if (num_cells < 2 || num_cells > 4)
- return NULL;
-
- if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
- return NULL;
- num_output = tmp / (sizeof(u32) * num_cells);
-
- characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
- if (!characteristics)
- return NULL;
-
- output = kcalloc(num_output, sizeof(*output), GFP_KERNEL);
- if (!output)
- goto out_free_characteristics;
-
- if (num_cells > 2) {
- out = kcalloc(num_output, sizeof(*out), GFP_KERNEL);
- if (!out)
- goto out_free_output;
- }
-
- if (num_cells > 3) {
- icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL);
- if (!icpll)
- goto out_free_output;
- }
-
- for (i = 0; i < num_output; i++) {
- offset = i * num_cells;
- if (of_property_read_u32_index(np,
- "atmel,pll-clk-output-ranges",
- offset, &tmp))
- goto out_free_output;
- output[i].min = tmp;
- if (of_property_read_u32_index(np,
- "atmel,pll-clk-output-ranges",
- offset + 1, &tmp))
- goto out_free_output;
- output[i].max = tmp;
-
- if (num_cells == 2)
- continue;
-
- if (of_property_read_u32_index(np,
- "atmel,pll-clk-output-ranges",
- offset + 2, &tmp))
- goto out_free_output;
- out[i] = tmp;
-
- if (num_cells == 3)
- continue;
-
- if (of_property_read_u32_index(np,
- "atmel,pll-clk-output-ranges",
- offset + 3, &tmp))
- goto out_free_output;
- icpll[i] = tmp;
- }
-
- characteristics->input = input;
- characteristics->num_output = num_output;
- characteristics->output = output;
- characteristics->out = out;
- characteristics->icpll = icpll;
- return characteristics;
-
-out_free_output:
- kfree(icpll);
- kfree(out);
- kfree(output);
-out_free_characteristics:
- kfree(characteristics);
- return NULL;
-}
-
-static void __init
-of_at91_clk_pll_setup(struct device_node *np,
- const struct clk_pll_layout *layout)
-{
- u32 id;
- struct clk_hw *hw;
- struct regmap *regmap;
- const char *parent_name;
- const char *name = np->name;
- struct clk_pll_characteristics *characteristics;
-
- if (of_property_read_u32(np, "reg", &id))
- return;
-
- parent_name = of_clk_get_parent_name(np, 0);
-
- of_property_read_string(np, "clock-output-names", &name);
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- characteristics = of_at91_clk_pll_get_characteristics(np);
- if (!characteristics)
- return;
-
- hw = at91_clk_register_pll(regmap, name, parent_name, id, layout,
- characteristics);
- if (IS_ERR(hw))
- goto out_free_characteristics;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
- return;
-
-out_free_characteristics:
- kfree(characteristics);
-}
-
-static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
-{
- of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
-}
-CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
- of_at91rm9200_clk_pll_setup);
-
-static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
-{
- of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
-}
-CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
- of_at91sam9g45_clk_pll_setup);
-
-static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
-{
- of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
-}
-CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
- of_at91sam9g20_clk_pllb_setup);
-
-static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
-{
- of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
-}
-CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
- of_sama5d3_clk_pll_setup);
diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c
index de803a2b27d3..e8c4f8b02f28 100644
--- a/drivers/clk/at91/clk-plldiv.c
+++ b/drivers/clk/at91/clk-plldiv.c
@@ -106,28 +106,3 @@ at91_clk_register_plldiv(struct regmap *regmap, const char *name,
return hw;
}
-
-static void __init
-of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
-{
- struct clk_hw *hw;
- const char *parent_name;
- const char *name = np->name;
- struct regmap *regmap;
-
- parent_name = of_clk_get_parent_name(np, 0);
-
- of_property_read_string(np, "clock-output-names", &name);
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- hw = at91_clk_register_plldiv(regmap, name, parent_name);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
-}
-CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
- of_at91sam9x5_clk_plldiv_setup);
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
index df302bfa8259..5bc68b9c5498 100644
--- a/drivers/clk/at91/clk-programmable.c
+++ b/drivers/clk/at91/clk-programmable.c
@@ -17,7 +17,6 @@
#include "pmc.h"
-#define PROG_SOURCE_MAX 5
#define PROG_ID_MAX 7
#define PROG_STATUS_MASK(id) (1 << ((id) + 8))
@@ -222,69 +221,3 @@ const struct clk_programmable_layout at91sam9x5_programmable_layout = {
.css_mask = 0x7,
.have_slck_mck = 0,
};
-
-static void __init
-of_at91_clk_prog_setup(struct device_node *np,
- const struct clk_programmable_layout *layout)
-{
- int num;
- u32 id;
- struct clk_hw *hw;
- unsigned int num_parents;
- const char *parent_names[PROG_SOURCE_MAX];
- const char *name;
- struct device_node *progclknp;
- struct regmap *regmap;
-
- num_parents = of_clk_get_parent_count(np);
- if (num_parents == 0 || num_parents > PROG_SOURCE_MAX)
- return;
-
- of_clk_parent_fill(np, parent_names, num_parents);
-
- num = of_get_child_count(np);
- if (!num || num > (PROG_ID_MAX + 1))
- return;
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- for_each_child_of_node(np, progclknp) {
- if (of_property_read_u32(progclknp, "reg", &id))
- continue;
-
- if (of_property_read_string(np, "clock-output-names", &name))
- name = progclknp->name;
-
- hw = at91_clk_register_programmable(regmap, name,
- parent_names, num_parents,
- id, layout);
- if (IS_ERR(hw))
- continue;
-
- of_clk_add_hw_provider(progclknp, of_clk_hw_simple_get, hw);
- }
-}
-
-
-static void __init of_at91rm9200_clk_prog_setup(struct device_node *np)
-{
- of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout);
-}
-CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable",
- of_at91rm9200_clk_prog_setup);
-
-static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np)
-{
- of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout);
-}
-CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable",
- of_at91sam9g45_clk_prog_setup);
-
-static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np)
-{
- of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout);
-}
-CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable",
- of_at91sam9x5_clk_prog_setup);
diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c
index a890132db68f..cbb146912f7a 100644
--- a/drivers/clk/at91/clk-slow.c
+++ b/drivers/clk/at91/clk-slow.c
@@ -79,33 +79,3 @@ at91_clk_register_sam9260_slow(struct regmap *regmap,
return hw;
}
-
-static void __init of_at91sam9260_clk_slow_setup(struct device_node *np)
-{
- struct clk_hw *hw;
- const char *parent_names[2];
- unsigned int num_parents;
- const char *name = np->name;
- struct regmap *regmap;
-
- num_parents = of_clk_get_parent_count(np);
- if (num_parents != 2)
- return;
-
- of_clk_parent_fill(np, parent_names, num_parents);
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- of_property_read_string(np, "clock-output-names", &name);
-
- hw = at91_clk_register_sam9260_slow(regmap, name, parent_names,
- num_parents);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
-}
-
-CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow",
- of_at91sam9260_clk_slow_setup);
diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c
index bbf5dc91777f..75679fd8a9c7 100644
--- a/drivers/clk/at91/clk-smd.c
+++ b/drivers/clk/at91/clk-smd.c
@@ -17,8 +17,6 @@
#include "pmc.h"
-#define SMD_SOURCE_MAX 2
-
#define SMD_DIV_SHIFT 8
#define SMD_MAX_DIV 0xf
@@ -142,33 +140,3 @@ at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
return hw;
}
-
-static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
-{
- struct clk_hw *hw;
- unsigned int num_parents;
- const char *parent_names[SMD_SOURCE_MAX];
- const char *name = np->name;
- struct regmap *regmap;
-
- num_parents = of_clk_get_parent_count(np);
- if (num_parents == 0 || num_parents > SMD_SOURCE_MAX)
- return;
-
- of_clk_parent_fill(np, parent_names, num_parents);
-
- of_property_read_string(np, "clock-output-names", &name);
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- hw = at91sam9x5_clk_register_smd(regmap, name, parent_names,
- num_parents);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
-}
-CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd",
- of_at91sam9x5_clk_smd_setup);
diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c
index 1ac0144a38c0..47bfca933403 100644
--- a/drivers/clk/at91/clk-system.c
+++ b/drivers/clk/at91/clk-system.c
@@ -123,40 +123,3 @@ at91_clk_register_system(struct regmap *regmap, const char *name,
return hw;
}
-
-static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
-{
- int num;
- u32 id;
- struct clk_hw *hw;
- const char *name;
- struct device_node *sysclknp;
- const char *parent_name;
- struct regmap *regmap;
-
- num = of_get_child_count(np);
- if (num > (SYSTEM_MAX_ID + 1))
- return;
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- for_each_child_of_node(np, sysclknp) {
- if (of_property_read_u32(sysclknp, "reg", &id))
- continue;
-
- if (of_property_read_string(np, "clock-output-names", &name))
- name = sysclknp->name;
-
- parent_name = of_clk_get_parent_name(sysclknp, 0);
-
- hw = at91_clk_register_system(regmap, name, parent_name, id);
- if (IS_ERR(hw))
- continue;
-
- of_clk_add_hw_provider(sysclknp, of_clk_hw_simple_get, hw);
- }
-}
-CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system",
- of_at91rm9200_clk_sys_setup);
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c
index a728320877dd..79ee1c760f2a 100644
--- a/drivers/clk/at91/clk-usb.c
+++ b/drivers/clk/at91/clk-usb.c
@@ -17,8 +17,6 @@
#include "pmc.h"
-#define USB_SOURCE_MAX 2
-
#define SAM9X5_USB_DIV_SHIFT 8
#define SAM9X5_USB_MAX_DIV 0xf
@@ -374,89 +372,3 @@ at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,
return hw;
}
-
-static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
-{
- struct clk_hw *hw;
- unsigned int num_parents;
- const char *parent_names[USB_SOURCE_MAX];
- const char *name = np->name;
- struct regmap *regmap;
-
- num_parents = of_clk_get_parent_count(np);
- if (num_parents == 0 || num_parents > USB_SOURCE_MAX)
- return;
-
- of_clk_parent_fill(np, parent_names, num_parents);
-
- of_property_read_string(np, "clock-output-names", &name);
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- hw = at91sam9x5_clk_register_usb(regmap, name, parent_names,
- num_parents);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
-}
-CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb",
- of_at91sam9x5_clk_usb_setup);
-
-static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)
-{
- struct clk_hw *hw;
- const char *parent_name;
- const char *name = np->name;
- struct regmap *regmap;
-
- parent_name = of_clk_get_parent_name(np, 0);
- if (!parent_name)
- return;
-
- of_property_read_string(np, "clock-output-names", &name);
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- hw = at91sam9n12_clk_register_usb(regmap, name, parent_name);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
-}
-CLK_OF_DECLARE(at91sam9n12_clk_usb, "atmel,at91sam9n12-clk-usb",
- of_at91sam9n12_clk_usb_setup);
-
-static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
-{
- struct clk_hw *hw;
- const char *parent_name;
- const char *name = np->name;
- u32 divisors[4] = {0, 0, 0, 0};
- struct regmap *regmap;
-
- parent_name = of_clk_get_parent_name(np, 0);
- if (!parent_name)
- return;
-
- of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4);
- if (!divisors[0])
- return;
-
- of_property_read_string(np, "clock-output-names", &name);
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
- hw = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
-}
-CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb",
- of_at91rm9200_clk_usb_setup);
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
index 6c69b6ac71e1..9a970abf3489 100644
--- a/drivers/clk/at91/clk-utmi.c
+++ b/drivers/clk/at91/clk-utmi.c
@@ -157,46 +157,3 @@ at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
return hw;
}
-
-static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
-{
- struct clk_hw *hw;
- const char *parent_name;
- const char *name = np->name;
- struct regmap *regmap_pmc, *regmap_sfr;
-
- parent_name = of_clk_get_parent_name(np, 0);
-
- of_property_read_string(np, "clock-output-names", &name);
-
- regmap_pmc = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap_pmc))
- return;
-
- /*
- * If the device supports different mainck rates, this value has to be
- * set in the UTMI Clock Trimming register.
- * - 9x5: mainck supports several rates but it is indicated that a
- * 12 MHz is needed in case of USB.
- * - sama5d3 and sama5d2: mainck supports several rates. Configuring
- * the FREQ field of the UTMI Clock Trimming register is mandatory.
- * - sama5d4: mainck is at 12 MHz.
- *
- * We only need to retrieve sama5d3 or sama5d2 sfr regmap.
- */
- regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr");
- if (IS_ERR(regmap_sfr)) {
- regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
- if (IS_ERR(regmap_sfr))
- regmap_sfr = NULL;
- }
-
- hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
- return;
-}
-CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi",
- of_at91sam9x5_clk_utmi_setup);
diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c
new file mode 100644
index 000000000000..b95bb4e2a927
--- /dev/null
+++ b/drivers/clk/at91/dt-compat.c
@@ -0,0 +1,961 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/clk-provider.h>
+#include <linux/clk/at91_pmc.h>
+#include <linux/of.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include "pmc.h"
+
+#define MASTER_SOURCE_MAX 4
+
+#define PERIPHERAL_AT91RM9200 0
+#define PERIPHERAL_AT91SAM9X5 1
+
+#define PERIPHERAL_MAX 64
+
+#define PERIPHERAL_ID_MIN 2
+
+#define PROG_SOURCE_MAX 5
+#define PROG_ID_MAX 7
+
+#define SYSTEM_MAX_ID 31
+
+#ifdef CONFIG_HAVE_AT91_AUDIO_PLL
+static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ const char *name = np->name;
+ const char *parent_name;
+ struct regmap *regmap;
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup,
+ "atmel,sama5d2-clk-audio-pll-frac",
+ of_sama5d2_clk_audio_pll_frac_setup);
+
+static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ const char *name = np->name;
+ const char *parent_name;
+ struct regmap *regmap;
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup,
+ "atmel,sama5d2-clk-audio-pll-pad",
+ of_sama5d2_clk_audio_pll_pad_setup);
+
+static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ const char *name = np->name;
+ const char *parent_name;
+ struct regmap *regmap;
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup,
+ "atmel,sama5d2-clk-audio-pll-pmc",
+ of_sama5d2_clk_audio_pll_pmc_setup);
+#endif /* CONFIG_HAVE_AT91_AUDIO_PLL */
+
+#ifdef CONFIG_HAVE_AT91_GENERATED_CLK
+#define GENERATED_SOURCE_MAX 6
+
+#define GCK_ID_I2S0 54
+#define GCK_ID_I2S1 55
+#define GCK_ID_CLASSD 59
+
+static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
+{
+ int num;
+ u32 id;
+ const char *name;
+ struct clk_hw *hw;
+ unsigned int num_parents;
+ const char *parent_names[GENERATED_SOURCE_MAX];
+ struct device_node *gcknp;
+ struct clk_range range = CLK_RANGE(0, 0);
+ struct regmap *regmap;
+
+ num_parents = of_clk_get_parent_count(np);
+ if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
+ return;
+
+ of_clk_parent_fill(np, parent_names, num_parents);
+
+ num = of_get_child_count(np);
+ if (!num || num > PERIPHERAL_MAX)
+ return;
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ for_each_child_of_node(np, gcknp) {
+ bool pll_audio = false;
+
+ if (of_property_read_u32(gcknp, "reg", &id))
+ continue;
+
+ if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
+ continue;
+
+ if (of_property_read_string(np, "clock-output-names", &name))
+ name = gcknp->name;
+
+ of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
+ &range);
+
+ if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&
+ (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||
+ id == GCK_ID_CLASSD))
+ pll_audio = true;
+
+ hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, name,
+ parent_names, num_parents,
+ id, pll_audio, &range);
+ if (IS_ERR(hw))
+ continue;
+
+ of_clk_add_hw_provider(gcknp, of_clk_hw_simple_get, hw);
+ }
+}
+CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated",
+ of_sama5d2_clk_generated_setup);
+#endif /* CONFIG_HAVE_AT91_GENERATED_CLK */
+
+#ifdef CONFIG_HAVE_AT91_H32MX
+static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ const char *name = np->name;
+ const char *parent_name;
+ struct regmap *regmap;
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ hw = at91_clk_register_h32mx(regmap, name, parent_name);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx",
+ of_sama5d4_clk_h32mx_setup);
+#endif /* CONFIG_HAVE_AT91_H32MX */
+
+#ifdef CONFIG_HAVE_AT91_I2S_MUX_CLK
+#define I2S_BUS_NR 2
+
+static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np)
+{
+ struct regmap *regmap_sfr;
+ u8 bus_id;
+ const char *parent_names[2];
+ struct device_node *i2s_mux_np;
+ struct clk_hw *hw;
+ int ret;
+
+ regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
+ if (IS_ERR(regmap_sfr))
+ return;
+
+ for_each_child_of_node(np, i2s_mux_np) {
+ if (of_property_read_u8(i2s_mux_np, "reg", &bus_id))
+ continue;
+
+ if (bus_id > I2S_BUS_NR)
+ continue;
+
+ ret = of_clk_parent_fill(i2s_mux_np, parent_names, 2);
+ if (ret != 2)
+ continue;
+
+ hw = at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name,
+ parent_names, 2, bus_id);
+ if (IS_ERR(hw))
+ continue;
+
+ of_clk_add_hw_provider(i2s_mux_np, of_clk_hw_simple_get, hw);
+ }
+}
+CLK_OF_DECLARE(sama5d2_clk_i2s_mux, "atmel,sama5d2-clk-i2s-mux",
+ of_sama5d2_clk_i2s_mux_setup);
+#endif /* CONFIG_HAVE_AT91_I2S_MUX_CLK */
+
+static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ const char *name = np->name;
+ const char *parent_name;
+ struct regmap *regmap;
+ bool bypass;
+
+ of_property_read_string(np, "clock-output-names", &name);
+ bypass = of_property_read_bool(np, "atmel,osc-bypass");
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ hw = at91_clk_register_main_osc(regmap, name, parent_name, bypass);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc",
+ of_at91rm9200_clk_main_osc_setup);
+
+static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ u32 frequency = 0;
+ u32 accuracy = 0;
+ const char *name = np->name;
+ struct regmap *regmap;
+
+ of_property_read_string(np, "clock-output-names", &name);
+ of_property_read_u32(np, "clock-frequency", &frequency);
+ of_property_read_u32(np, "clock-accuracy", &accuracy);
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ hw = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc",
+ of_at91sam9x5_clk_main_rc_osc_setup);
+
+static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ const char *parent_name;
+ const char *name = np->name;
+ struct regmap *regmap;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ of_property_read_string(np, "clock-output-names", &name);
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ hw = at91_clk_register_rm9200_main(regmap, name, parent_name);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
+ of_at91rm9200_clk_main_setup);
+
+static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ const char *parent_names[2];
+ unsigned int num_parents;
+ const char *name = np->name;
+ struct regmap *regmap;
+
+ num_parents = of_clk_get_parent_count(np);
+ if (num_parents == 0 || num_parents > 2)
+ return;
+
+ of_clk_parent_fill(np, parent_names, num_parents);
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ hw = at91_clk_register_sam9x5_main(regmap, name, parent_names,
+ num_parents);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main",
+ of_at91sam9x5_clk_main_setup);
+
+static struct clk_master_characteristics * __init
+of_at91_clk_master_get_characteristics(struct device_node *np)
+{
+ struct clk_master_characteristics *characteristics;
+
+ characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
+ if (!characteristics)
+ return NULL;
+
+ if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output))
+ goto out_free_characteristics;
+
+ of_property_read_u32_array(np, "atmel,clk-divisors",
+ characteristics->divisors, 4);
+
+ characteristics->have_div3_pres =
+ of_property_read_bool(np, "atmel,master-clk-have-div3-pres");
+
+ return characteristics;
+
+out_free_characteristics:
+ kfree(characteristics);
+ return NULL;
+}
+
+static void __init
+of_at91_clk_master_setup(struct device_node *np,
+ const struct clk_master_layout *layout)
+{
+ struct clk_hw *hw;
+ unsigned int num_parents;
+ const char *parent_names[MASTER_SOURCE_MAX];
+ const char *name = np->name;
+ struct clk_master_characteristics *characteristics;
+ struct regmap *regmap;
+
+ num_parents = of_clk_get_parent_count(np);
+ if (num_parents == 0 || num_parents > MASTER_SOURCE_MAX)
+ return;
+
+ of_clk_parent_fill(np, parent_names, num_parents);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ characteristics = of_at91_clk_master_get_characteristics(np);
+ if (!characteristics)
+ return;
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ hw = at91_clk_register_master(regmap, name, num_parents,
+ parent_names, layout,
+ characteristics);
+ if (IS_ERR(hw))
+ goto out_free_characteristics;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+ return;
+
+out_free_characteristics:
+ kfree(characteristics);
+}
+
+static void __init of_at91rm9200_clk_master_setup(struct device_node *np)
+{
+ of_at91_clk_master_setup(np, &at91rm9200_master_layout);
+}
+CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master",
+ of_at91rm9200_clk_master_setup);
+
+static void __init of_at91sam9x5_clk_master_setup(struct device_node *np)
+{
+ of_at91_clk_master_setup(np, &at91sam9x5_master_layout);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master",
+ of_at91sam9x5_clk_master_setup);
+
+static void __init
+of_at91_clk_periph_setup(struct device_node *np, u8 type)
+{
+ int num;
+ u32 id;
+ struct clk_hw *hw;
+ const char *parent_name;
+ const char *name;
+ struct device_node *periphclknp;
+ struct regmap *regmap;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ if (!parent_name)
+ return;
+
+ num = of_get_child_count(np);
+ if (!num || num > PERIPHERAL_MAX)
+ return;
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ for_each_child_of_node(np, periphclknp) {
+ if (of_property_read_u32(periphclknp, "reg", &id))
+ continue;
+
+ if (id >= PERIPHERAL_MAX)
+ continue;
+
+ if (of_property_read_string(np, "clock-output-names", &name))
+ name = periphclknp->name;
+
+ if (type == PERIPHERAL_AT91RM9200) {
+ hw = at91_clk_register_peripheral(regmap, name,
+ parent_name, id);
+ } else {
+ struct clk_range range = CLK_RANGE(0, 0);
+
+ of_at91_get_clk_range(periphclknp,
+ "atmel,clk-output-range",
+ &range);
+
+ hw = at91_clk_register_sam9x5_peripheral(regmap,
+ &pmc_pcr_lock,
+ name,
+ parent_name,
+ id, &range);
+ }
+
+ if (IS_ERR(hw))
+ continue;
+
+ of_clk_add_hw_provider(periphclknp, of_clk_hw_simple_get, hw);
+ }
+}
+
+static void __init of_at91rm9200_clk_periph_setup(struct device_node *np)
+{
+ of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200);
+}
+CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral",
+ of_at91rm9200_clk_periph_setup);
+
+static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np)
+{
+ of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral",
+ of_at91sam9x5_clk_periph_setup);
+
+static struct clk_pll_characteristics * __init
+of_at91_clk_pll_get_characteristics(struct device_node *np)
+{
+ int i;
+ int offset;
+ u32 tmp;
+ int num_output;
+ u32 num_cells;
+ struct clk_range input;
+ struct clk_range *output;
+ u8 *out = NULL;
+ u16 *icpll = NULL;
+ struct clk_pll_characteristics *characteristics;
+
+ if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
+ return NULL;
+
+ if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
+ &num_cells))
+ return NULL;
+
+ if (num_cells < 2 || num_cells > 4)
+ return NULL;
+
+ if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
+ return NULL;
+ num_output = tmp / (sizeof(u32) * num_cells);
+
+ characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
+ if (!characteristics)
+ return NULL;
+
+ output = kcalloc(num_output, sizeof(*output), GFP_KERNEL);
+ if (!output)
+ goto out_free_characteristics;
+
+ if (num_cells > 2) {
+ out = kcalloc(num_output, sizeof(*out), GFP_KERNEL);
+ if (!out)
+ goto out_free_output;
+ }
+
+ if (num_cells > 3) {
+ icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL);
+ if (!icpll)
+ goto out_free_output;
+ }
+
+ for (i = 0; i < num_output; i++) {
+ offset = i * num_cells;
+ if (of_property_read_u32_index(np,
+ "atmel,pll-clk-output-ranges",
+ offset, &tmp))
+ goto out_free_output;
+ output[i].min = tmp;
+ if (of_property_read_u32_index(np,
+ "atmel,pll-clk-output-ranges",
+ offset + 1, &tmp))
+ goto out_free_output;
+ output[i].max = tmp;
+
+ if (num_cells == 2)
+ continue;
+
+ if (of_property_read_u32_index(np,
+ "atmel,pll-clk-output-ranges",
+ offset + 2, &tmp))
+ goto out_free_output;
+ out[i] = tmp;
+
+ if (num_cells == 3)
+ continue;
+
+ if (of_property_read_u32_index(np,
+ "atmel,pll-clk-output-ranges",
+ offset + 3, &tmp))
+ goto out_free_output;
+ icpll[i] = tmp;
+ }
+
+ characteristics->input = input;
+ characteristics->num_output = num_output;
+ characteristics->output = output;
+ characteristics->out = out;
+ characteristics->icpll = icpll;
+ return characteristics;
+
+out_free_output:
+ kfree(icpll);
+ kfree(out);
+ kfree(output);
+out_free_characteristics:
+ kfree(characteristics);
+ return NULL;
+}
+
+static void __init
+of_at91_clk_pll_setup(struct device_node *np,
+ const struct clk_pll_layout *layout)
+{
+ u32 id;
+ struct clk_hw *hw;
+ struct regmap *regmap;
+ const char *parent_name;
+ const char *name = np->name;
+ struct clk_pll_characteristics *characteristics;
+
+ if (of_property_read_u32(np, "reg", &id))
+ return;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ characteristics = of_at91_clk_pll_get_characteristics(np);
+ if (!characteristics)
+ return;
+
+ hw = at91_clk_register_pll(regmap, name, parent_name, id, layout,
+ characteristics);
+ if (IS_ERR(hw))
+ goto out_free_characteristics;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+ return;
+
+out_free_characteristics:
+ kfree(characteristics);
+}
+
+static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
+}
+CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
+ of_at91rm9200_clk_pll_setup);
+
+static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
+}
+CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
+ of_at91sam9g45_clk_pll_setup);
+
+static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
+}
+CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
+ of_at91sam9g20_clk_pllb_setup);
+
+static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
+}
+CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
+ of_sama5d3_clk_pll_setup);
+
+static void __init
+of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ const char *parent_name;
+ const char *name = np->name;
+ struct regmap *regmap;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ hw = at91_clk_register_plldiv(regmap, name, parent_name);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
+ of_at91sam9x5_clk_plldiv_setup);
+
+static void __init
+of_at91_clk_prog_setup(struct device_node *np,
+ const struct clk_programmable_layout *layout)
+{
+ int num;
+ u32 id;
+ struct clk_hw *hw;
+ unsigned int num_parents;
+ const char *parent_names[PROG_SOURCE_MAX];
+ const char *name;
+ struct device_node *progclknp;
+ struct regmap *regmap;
+
+ num_parents = of_clk_get_parent_count(np);
+ if (num_parents == 0 || num_parents > PROG_SOURCE_MAX)
+ return;
+
+ of_clk_parent_fill(np, parent_names, num_parents);
+
+ num = of_get_child_count(np);
+ if (!num || num > (PROG_ID_MAX + 1))
+ return;
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ for_each_child_of_node(np, progclknp) {
+ if (of_property_read_u32(progclknp, "reg", &id))
+ continue;
+
+ if (of_property_read_string(np, "clock-output-names", &name))
+ name = progclknp->name;
+
+ hw = at91_clk_register_programmable(regmap, name,
+ parent_names, num_parents,
+ id, layout);
+ if (IS_ERR(hw))
+ continue;
+
+ of_clk_add_hw_provider(progclknp, of_clk_hw_simple_get, hw);
+ }
+}
+
+static void __init of_at91rm9200_clk_prog_setup(struct device_node *np)
+{
+ of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout);
+}
+CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable",
+ of_at91rm9200_clk_prog_setup);
+
+static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np)
+{
+ of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout);
+}
+CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable",
+ of_at91sam9g45_clk_prog_setup);
+
+static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np)
+{
+ of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable",
+ of_at91sam9x5_clk_prog_setup);
+
+static void __init of_at91sam9260_clk_slow_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ const char *parent_names[2];
+ unsigned int num_parents;
+ const char *name = np->name;
+ struct regmap *regmap;
+
+ num_parents = of_clk_get_parent_count(np);
+ if (num_parents != 2)
+ return;
+
+ of_clk_parent_fill(np, parent_names, num_parents);
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ hw = at91_clk_register_sam9260_slow(regmap, name, parent_names,
+ num_parents);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow",
+ of_at91sam9260_clk_slow_setup);
+
+#ifdef CONFIG_HAVE_AT91_SMD
+#define SMD_SOURCE_MAX 2
+
+static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ unsigned int num_parents;
+ const char *parent_names[SMD_SOURCE_MAX];
+ const char *name = np->name;
+ struct regmap *regmap;
+
+ num_parents = of_clk_get_parent_count(np);
+ if (num_parents == 0 || num_parents > SMD_SOURCE_MAX)
+ return;
+
+ of_clk_parent_fill(np, parent_names, num_parents);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ hw = at91sam9x5_clk_register_smd(regmap, name, parent_names,
+ num_parents);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd",
+ of_at91sam9x5_clk_smd_setup);
+#endif /* CONFIG_HAVE_AT91_SMD */
+
+static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
+{
+ int num;
+ u32 id;
+ struct clk_hw *hw;
+ const char *name;
+ struct device_node *sysclknp;
+ const char *parent_name;
+ struct regmap *regmap;
+
+ num = of_get_child_count(np);
+ if (num > (SYSTEM_MAX_ID + 1))
+ return;
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ for_each_child_of_node(np, sysclknp) {
+ if (of_property_read_u32(sysclknp, "reg", &id))
+ continue;
+
+ if (of_property_read_string(np, "clock-output-names", &name))
+ name = sysclknp->name;
+
+ parent_name = of_clk_get_parent_name(sysclknp, 0);
+
+ hw = at91_clk_register_system(regmap, name, parent_name, id);
+ if (IS_ERR(hw))
+ continue;
+
+ of_clk_add_hw_provider(sysclknp, of_clk_hw_simple_get, hw);
+ }
+}
+CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system",
+ of_at91rm9200_clk_sys_setup);
+
+#ifdef CONFIG_HAVE_AT91_USB_CLK
+#define USB_SOURCE_MAX 2
+
+static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ unsigned int num_parents;
+ const char *parent_names[USB_SOURCE_MAX];
+ const char *name = np->name;
+ struct regmap *regmap;
+
+ num_parents = of_clk_get_parent_count(np);
+ if (num_parents == 0 || num_parents > USB_SOURCE_MAX)
+ return;
+
+ of_clk_parent_fill(np, parent_names, num_parents);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ hw = at91sam9x5_clk_register_usb(regmap, name, parent_names,
+ num_parents);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb",
+ of_at91sam9x5_clk_usb_setup);
+
+static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ const char *parent_name;
+ const char *name = np->name;
+ struct regmap *regmap;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ if (!parent_name)
+ return;
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+
+ hw = at91sam9n12_clk_register_usb(regmap, name, parent_name);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(at91sam9n12_clk_usb, "atmel,at91sam9n12-clk-usb",
+ of_at91sam9n12_clk_usb_setup);
+
+static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ const char *parent_name;
+ const char *name = np->name;
+ u32 divisors[4] = {0, 0, 0, 0};
+ struct regmap *regmap;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ if (!parent_name)
+ return;
+
+ of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4);
+ if (!divisors[0])
+ return;
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ regmap = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap))
+ return;
+ hw = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb",
+ of_at91rm9200_clk_usb_setup);
+#endif /* CONFIG_HAVE_AT91_USB_CLK */
+
+#ifdef CONFIG_HAVE_AT91_UTMI
+static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
+{
+ struct clk_hw *hw;
+ const char *parent_name;
+ const char *name = np->name;
+ struct regmap *regmap_pmc, *regmap_sfr;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ regmap_pmc = syscon_node_to_regmap(of_get_parent(np));
+ if (IS_ERR(regmap_pmc))
+ return;
+
+ /*
+ * If the device supports different mainck rates, this value has to be
+ * set in the UTMI Clock Trimming register.
+ * - 9x5: mainck supports several rates but it is indicated that a
+ * 12 MHz is needed in case of USB.
+ * - sama5d3 and sama5d2: mainck supports several rates. Configuring
+ * the FREQ field of the UTMI Clock Trimming register is mandatory.
+ * - sama5d4: mainck is at 12 MHz.
+ *
+ * We only need to retrieve sama5d3 or sama5d2 sfr regmap.
+ */
+ regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr");
+ if (IS_ERR(regmap_sfr)) {
+ regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
+ if (IS_ERR(regmap_sfr))
+ regmap_sfr = NULL;
+ }
+
+ hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name);
+ if (IS_ERR(hw))
+ return;
+
+ of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi",
+ of_at91sam9x5_clk_utmi_setup);
+#endif /* CONFIG_HAVE_AT91_UTMI */
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 16/22] ARM: dts: at91: sama5d4: switch to new clock bindings
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (14 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 15/22] clk: at91: move DT compatibility code to its own file Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-16 14:21 ` [PATCH v2 17/22] ARM: dts: at91: sama5d2: switch to new binding Alexandre Belloni
` (6 subsequent siblings)
22 siblings, 0 replies; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Switch sama5d4 boards to the new PMC clock bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
arch/arm/boot/dts/at91-sama5d4ek.dts | 2 +-
arch/arm/boot/dts/sama5d4.dtsi | 535 +++------------------------
2 files changed, 49 insertions(+), 488 deletions(-)
diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts
index 0702a2f2b336..12d5af938aa3 100644
--- a/arch/arm/boot/dts/at91-sama5d4ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -115,7 +115,7 @@
wm8904: codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
- clocks = <&pck2>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 10>;
clock-names = "mclk";
};
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 92a35a1942b6..107a704514e0 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -137,7 +137,7 @@
reg = <0x00400000 0x100000
0xfc02c000 0x4000>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&udphs_clk>, <&utmi>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
clock-names = "pclk", "hclk";
status = "disabled";
@@ -264,7 +264,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -273,7 +273,7 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00600000 0x100000>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&utmi>, <&uhphs_clk>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
@@ -297,7 +297,7 @@
0x1 0x0 0x60000000 0x10000000
0x2 0x0 0x70000000 0x10000000
0x3 0x0 0x80000000 0x8000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
@@ -327,7 +327,7 @@
compatible = "atmel,sama5d4-hlcdc";
reg = <0xf0000000 0x4000>;
interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
status = "disabled";
@@ -356,7 +356,7 @@
reg = <0xf0004000 0x200>;
interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
- clocks = <&dma1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 50>;
clock-names = "dma_clk";
};
@@ -366,7 +366,7 @@
interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isi_data_0_7>;
- clocks = <&isi_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
clock-names = "isi_clk";
status = "disabled";
port {
@@ -378,7 +378,7 @@
ramc0: ramc@f0010000 {
compatible = "atmel,sama5d3-ddramc";
reg = <0xf0010000 0x200>;
- clocks = <&ddrck>, <&mpddr_clk>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>;
clock-names = "ddrck", "mpddr";
};
@@ -387,7 +387,7 @@
reg = <0xf0014000 0x200>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
- clocks = <&dma0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "dma_clk";
};
@@ -395,448 +395,9 @@
compatible = "atmel,sama5d4-pmc", "syscon";
reg = <0xf0018000 0x120>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main_rc_osc: main_rc_osc {
- compatible = "atmel,at91sam9x5-clk-main-rc-osc";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_MOSCRCS>;
- clock-frequency = <12000000>;
- clock-accuracy = <100000000>;
- };
-
- main_osc: main_osc {
- compatible = "atmel,at91rm9200-clk-main-osc";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- main: mainck {
- compatible = "atmel,at91sam9x5-clk-main";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_MOSCSELS>;
- clocks = <&main_rc_osc &main_osc>;
- };
-
- plla: pllack {
- compatible = "atmel,sama5d3-clk-pll";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <12000000 12000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
- };
-
- plladiv: plladivck {
- compatible = "atmel,at91sam9x5-clk-plldiv";
- #clock-cells = <0>;
- clocks = <&plla>;
- };
-
- utmi: utmick {
- compatible = "atmel,at91sam9x5-clk-utmi";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_LOCKU>;
- clocks = <&main>;
- };
-
- mck: masterck {
- compatible = "atmel,at91sam9x5-clk-master";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_MCKRDY>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
- atmel,clk-output-range = <125000000 200000000>;
- atmel,clk-divisors = <1 2 4 3>;
- };
-
- h32ck: h32mxck {
- #clock-cells = <0>;
- compatible = "atmel,sama5d4-clk-h32mx";
- clocks = <&mck>;
- };
-
- usb: usbck {
- compatible = "atmel,at91sam9x5-clk-usb";
- #clock-cells = <0>;
- clocks = <&plladiv>, <&utmi>;
- };
-
- prog: progck {
- compatible = "atmel,at91sam9x5-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
-
- prog2: prog2 {
- #clock-cells = <0>;
- reg = <2>;
- interrupts = <AT91_PMC_PCKRDY(2)>;
- };
- };
-
- smd: smdclk {
- compatible = "atmel,at91sam9x5-clk-smd";
- #clock-cells = <0>;
- clocks = <&plladiv>, <&utmi>;
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ddrck: ddrck {
- #clock-cells = <0>;
- reg = <2>;
- clocks = <&mck>;
- };
-
- lcdck: lcdck {
- #clock-cells = <0>;
- reg = <3>;
- clocks = <&mck>;
- };
-
- smdck: smdck {
- #clock-cells = <0>;
- reg = <4>;
- clocks = <&smd>;
- };
-
- uhpck: uhpck {
- #clock-cells = <0>;
- reg = <6>;
- clocks = <&usb>;
- };
-
- udpck: udpck {
- #clock-cells = <0>;
- reg = <7>;
- clocks = <&usb>;
- };
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
-
- pck2: pck2 {
- #clock-cells = <0>;
- reg = <10>;
- clocks = <&prog2>;
- };
- };
-
- periph32ck {
- compatible = "atmel,at91sam9x5-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&h32ck>;
-
- pioD_clk: pioD_clk {
- #clock-cells = <0>;
- reg = <5>;
- };
-
- usart0_clk: usart0_clk {
- #clock-cells = <0>;
- reg = <6>;
- };
-
- usart1_clk: usart1_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- icm_clk: icm_clk {
- #clock-cells = <0>;
- reg = <9>;
- };
-
- aes_clk: aes_clk {
- #clock-cells = <0>;
- reg = <12>;
- };
-
- tdes_clk: tdes_clk {
- #clock-cells = <0>;
- reg = <14>;
- };
-
- sha_clk: sha_clk {
- #clock-cells = <0>;
- reg = <15>;
- };
-
- matrix1_clk: matrix1_clk {
- #clock-cells = <0>;
- reg = <17>;
- };
-
- hsmc_clk: hsmc_clk {
- #clock-cells = <0>;
- reg = <22>;
- };
-
- pioA_clk: pioA_clk {
- #clock-cells = <0>;
- reg = <23>;
- };
-
- pioB_clk: pioB_clk {
- #clock-cells = <0>;
- reg = <24>;
- };
-
- pioC_clk: pioC_clk {
- #clock-cells = <0>;
- reg = <25>;
- };
-
- pioE_clk: pioE_clk {
- #clock-cells = <0>;
- reg = <26>;
- };
-
- uart0_clk: uart0_clk {
- #clock-cells = <0>;
- reg = <27>;
- };
-
- uart1_clk: uart1_clk {
- #clock-cells = <0>;
- reg = <28>;
- };
-
- usart2_clk: usart2_clk {
- #clock-cells = <0>;
- reg = <29>;
- };
-
- usart3_clk: usart3_clk {
- #clock-cells = <0>;
- reg = <30>;
- };
-
- usart4_clk: usart4_clk {
- #clock-cells = <0>;
- reg = <31>;
- };
-
- twi0_clk: twi0_clk {
- reg = <32>;
- #clock-cells = <0>;
- };
-
- twi1_clk: twi1_clk {
- #clock-cells = <0>;
- reg = <33>;
- };
-
- twi2_clk: twi2_clk {
- #clock-cells = <0>;
- reg = <34>;
- };
-
- mci0_clk: mci0_clk {
- #clock-cells = <0>;
- reg = <35>;
- };
-
- mci1_clk: mci1_clk {
- #clock-cells = <0>;
- reg = <36>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <37>;
- };
-
- spi1_clk: spi1_clk {
- #clock-cells = <0>;
- reg = <38>;
- };
-
- spi2_clk: spi2_clk {
- #clock-cells = <0>;
- reg = <39>;
- };
-
- tcb0_clk: tcb0_clk {
- #clock-cells = <0>;
- reg = <40>;
- };
-
- tcb1_clk: tcb1_clk {
- #clock-cells = <0>;
- reg = <41>;
- };
-
- tcb2_clk: tcb2_clk {
- #clock-cells = <0>;
- reg = <42>;
- };
-
- pwm_clk: pwm_clk {
- #clock-cells = <0>;
- reg = <43>;
- };
-
- adc_clk: adc_clk {
- #clock-cells = <0>;
- reg = <44>;
- };
-
- dbgu_clk: dbgu_clk {
- #clock-cells = <0>;
- reg = <45>;
- };
-
- uhphs_clk: uhphs_clk {
- #clock-cells = <0>;
- reg = <46>;
- };
-
- udphs_clk: udphs_clk {
- #clock-cells = <0>;
- reg = <47>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <48>;
- };
-
- ssc1_clk: ssc1_clk {
- #clock-cells = <0>;
- reg = <49>;
- };
-
- trng_clk: trng_clk {
- #clock-cells = <0>;
- reg = <53>;
- };
-
- macb0_clk: macb0_clk {
- #clock-cells = <0>;
- reg = <54>;
- };
-
- macb1_clk: macb1_clk {
- #clock-cells = <0>;
- reg = <55>;
- };
-
- fuse_clk: fuse_clk {
- #clock-cells = <0>;
- reg = <57>;
- };
-
- securam_clk: securam_clk {
- #clock-cells = <0>;
- reg = <59>;
- };
-
- smd_clk: smd_clk {
- #clock-cells = <0>;
- reg = <61>;
- };
-
- twi3_clk: twi3_clk {
- #clock-cells = <0>;
- reg = <62>;
- };
-
- catb_clk: catb_clk {
- #clock-cells = <0>;
- reg = <63>;
- };
- };
-
- periph64ck {
- compatible = "atmel,at91sam9x5-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- dma0_clk: dma0_clk {
- #clock-cells = <0>;
- reg = <8>;
- };
-
- cpkcc_clk: cpkcc_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- aesb_clk: aesb_clk {
- #clock-cells = <0>;
- reg = <13>;
- };
-
- mpddr_clk: mpddr_clk {
- #clock-cells = <0>;
- reg = <16>;
- };
-
- matrix0_clk: matrix0_clk {
- #clock-cells = <0>;
- reg = <18>;
- };
-
- vdec_clk: vdec_clk {
- #clock-cells = <0>;
- reg = <19>;
- };
-
- dma1_clk: dma1_clk {
- #clock-cells = <0>;
- reg = <50>;
- };
-
- lcdc_clk: lcdc_clk {
- #clock-cells = <0>;
- reg = <51>;
- };
-
- isi_clk: isi_clk {
- #clock-cells = <0>;
- reg = <52>;
- };
- };
+ #clock-cells = <2>;
+ clocks = <&clk32k>, <&main_xtal>;
+ clock-names = "slow_clk", "main_xtal";
};
mmc0: mmc@f8000000 {
@@ -852,7 +413,7 @@
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&mci0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 35>;
clock-names = "mci_clk";
};
@@ -869,7 +430,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
- clocks = <&uart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
clock-names = "usart";
status = "disabled";
};
@@ -887,7 +448,7 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(27))>;
dma-names = "tx", "rx";
- clocks = <&ssc0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
clock-names = "pclk";
status = "disabled";
};
@@ -897,7 +458,7 @@
reg = <0xf800c000 0x300>;
interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
- clocks = <&pwm_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
status = "disabled";
};
@@ -916,7 +477,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -936,7 +497,7 @@
pinctrl-0 = <&pinctrl_i2c0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
status = "disabled";
};
@@ -955,7 +516,7 @@
pinctrl-0 = <&pinctrl_i2c1>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
status = "disabled";
};
@@ -965,7 +526,7 @@
#size-cells = <0>;
reg = <0xf801c000 0x100>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb0_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
@@ -977,7 +538,7 @@
pinctrl-0 = <&pinctrl_macb0_rmii>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&macb0_clk>, <&macb0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>;
clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -997,7 +558,7 @@
pinctrl-0 = <&pinctrl_i2c2>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
status = "disabled";
};
@@ -1019,7 +580,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
- clocks = <&usart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "usart";
status = "disabled";
};
@@ -1037,7 +598,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
- clocks = <&usart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@@ -1055,7 +616,7 @@
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&mci1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
clock-names = "mci_clk";
};
@@ -1072,7 +633,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- clocks = <&uart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
clock-names = "usart";
status = "disabled";
};
@@ -1090,7 +651,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
- clocks = <&usart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
clock-names = "usart";
status = "disabled";
};
@@ -1108,7 +669,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
- clocks = <&usart3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
clock-names = "usart";
status = "disabled";
};
@@ -1126,7 +687,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart4>;
- clocks = <&usart4_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
clock-names = "usart";
status = "disabled";
};
@@ -1144,7 +705,7 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(29))>;
dma-names = "tx", "rx";
- clocks = <&ssc1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
clock-names = "pclk";
status = "disabled";
};
@@ -1164,7 +725,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- clocks = <&spi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -1184,7 +745,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- clocks = <&spi2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -1195,7 +756,7 @@
#size-cells = <0>;
reg = <0xfc020000 0x100>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb1_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
@@ -1205,7 +766,7 @@
#size-cells = <0>;
reg = <0xfc024000 0x100>;
interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb2_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
@@ -1217,7 +778,7 @@
pinctrl-0 = <&pinctrl_macb1_rmii>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&macb1_clk>, <&macb1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>;
clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -1226,14 +787,14 @@
compatible = "atmel,at91sam9g45-trng";
reg = <0xfc030000 0x100>;
interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&trng_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
};
adc0: adc@fc034000 {
compatible = "atmel,at91sam9x5-adc";
reg = <0xfc034000 0x100>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
- clocks = <&adc_clk>,
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 44>,
<&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk";
atmel,adc-channels-used = <0x01f>;
@@ -1276,7 +837,7 @@
<&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(40))>;
dma-names = "tx", "rx";
- clocks = <&aes_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "aes_clk";
status = "okay";
};
@@ -1290,7 +851,7 @@
<&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(43))>;
dma-names = "tx", "rx";
- clocks = <&tdes_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "tdes_clk";
status = "okay";
};
@@ -1302,7 +863,7 @@
dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(44))>;
dma-names = "tx";
- clocks = <&sha_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
clock-names = "sha_clk";
status = "okay";
};
@@ -1311,7 +872,7 @@
compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
reg = <0xfc05c000 0x1000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
- clocks = <&hsmc_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -1339,7 +900,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfc068630 0x10>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
- clocks = <&h32ck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
};
watchdog@fc068640 {
@@ -1370,7 +931,7 @@
interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&dbgu_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
clock-names = "usart";
status = "disabled";
};
@@ -1400,7 +961,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioA_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
};
pioB: gpio@fc06b000 {
@@ -1411,7 +972,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
};
pioC: gpio@fc06c000 {
@@ -1422,7 +983,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioC_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
};
pioD: gpio@fc068000 {
@@ -1433,7 +994,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioD_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
};
pioE: gpio@fc06d000 {
@@ -1444,7 +1005,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioE_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
};
/* pinctrl pin settings */
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 17/22] ARM: dts: at91: sama5d2: switch to new binding
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (15 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 16/22] ARM: dts: at91: sama5d4: switch to new clock bindings Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-16 14:21 ` [PATCH v2 18/22] ARM: dts: at91: at91sam9260: switch to new clock bindings Alexandre Belloni
` (5 subsequent siblings)
22 siblings, 0 replies; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Switch sama5d2 boards to the new PMC clock bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 12 +-
arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 2 +-
arch/arm/boot/dts/at91-sama5d2_xplained.dts | 4 +-
arch/arm/boot/dts/sama5d2.dtsi | 642 ++------------------
4 files changed, 64 insertions(+), 596 deletions(-)
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
index e86e0c00eb6b..2b0ddabe4178 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
@@ -165,7 +165,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&flx1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus_i2c>;
atmel,fifo-size = <16>;
@@ -211,7 +211,7 @@
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&flx3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "usart";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx3_default>;
@@ -223,7 +223,7 @@
compatible = "atmel,at91rm9200-spi";
reg = <0x400 0x200>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&flx3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "spi_clk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx3_default>;
@@ -240,7 +240,7 @@
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&flx4_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "usart";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
@@ -252,7 +252,7 @@
compatible = "atmel,at91rm9200-spi";
reg = <0x400 0x200>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&flx4_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "spi_clk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>;
@@ -268,7 +268,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&flx4_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
atmel,fifo-size = <16>;
diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
index b10dccd0958f..835ff9b715c7 100644
--- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
@@ -196,7 +196,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&flx0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
atmel,fifo-size = <16>;
diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index fcc85d70f36e..7546116b3b64 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -258,7 +258,7 @@
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&flx0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
clock-names = "usart";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
@@ -307,7 +307,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&flx4_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
atmel,fifo-size = <16>;
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 61f68e5c48e9..6c70a928defb 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -81,7 +81,7 @@
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x740000 0x1000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "apb_pclk";
port {
@@ -96,7 +96,7 @@
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x73C000 0x1000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "apb_pclk";
port {
@@ -148,7 +148,7 @@
reg = <0x00300000 0x100000
0xfc02c000 0x400>;
interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&udphs_clk>, <&utmi>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
clock-names = "pclk", "hclk";
status = "disabled";
@@ -275,7 +275,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00400000 0x100000>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -284,7 +284,7 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00500000 0x100000>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&utmi>, <&uhphs_clk>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
@@ -308,7 +308,7 @@
0x1 0x0 0x60000000 0x10000000
0x2 0x0 0x70000000 0x10000000
0x3 0x0 0x80000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
@@ -356,7 +356,7 @@
/* NFC SRAM banks */
0x00100000 0x00100000
>;
- clocks = <&hsmc_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
atmel,write-by-sram;
};
};
@@ -365,7 +365,7 @@
compatible = "atmel,sama5d2-sdhci";
reg = <0xa0000000 0x300>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
clock-names = "hclock", "multclk", "baseclk";
status = "disabled";
};
@@ -374,7 +374,7 @@
compatible = "atmel,sama5d2-sdhci";
reg = <0xb0000000 0x300>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
clock-names = "hclock", "multclk", "baseclk";
status = "disabled";
};
@@ -394,7 +394,7 @@
compatible = "atmel,sama5d2-hlcdc";
reg = <0xf0000000 0x2000>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
status = "disabled";
@@ -420,7 +420,7 @@
compatible = "atmel,sama5d2-isc";
reg = <0xf0008000 0x4000>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
- clocks = <&isc_clk>, <&iscck>, <&isc_gclk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>;
clock-names = "hclock", "iscck", "gck";
#clock-cells = <0>;
clock-output-names = "isc-mck";
@@ -430,7 +430,7 @@
ramc0: ramc@f000c000 {
compatible = "atmel,sama5d3-ddramc";
reg = <0xf000c000 0x200>;
- clocks = <&ddrck>, <&mpddr_clk>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "ddrck", "mpddr";
};
@@ -439,7 +439,7 @@
reg = <0xf0010000 0x1000>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
- clocks = <&dma0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "dma_clk";
};
@@ -449,7 +449,7 @@
reg = <0xf0004000 0x1000>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
- clocks = <&dma1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "dma_clk";
};
@@ -457,541 +457,9 @@
compatible = "atmel,sama5d2-pmc", "syscon";
reg = <0xf0014000 0x160>;
interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main_rc_osc: main_rc_osc {
- compatible = "atmel,at91sam9x5-clk-main-rc-osc";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_MOSCRCS>;
- clock-frequency = <12000000>;
- clock-accuracy = <100000000>;
- };
-
- main_osc: main_osc {
- compatible = "atmel,at91rm9200-clk-main-osc";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- main: mainck {
- compatible = "atmel,at91sam9x5-clk-main";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_MOSCSELS>;
- clocks = <&main_rc_osc &main_osc>;
- };
-
- plla: pllack {
- compatible = "atmel,sama5d3-clk-pll";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <12000000 12000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
- };
-
- plladiv: plladivck {
- compatible = "atmel,at91sam9x5-clk-plldiv";
- #clock-cells = <0>;
- clocks = <&plla>;
- };
-
- audio_pll_frac: audiopll_fracck {
- compatible = "atmel,sama5d2-clk-audio-pll-frac";
- #clock-cells = <0>;
- clocks = <&main>;
- };
-
- audio_pll_pad: audiopll_padck {
- compatible = "atmel,sama5d2-clk-audio-pll-pad";
- #clock-cells = <0>;
- clocks = <&audio_pll_frac>;
- };
-
- audio_pll_pmc: audiopll_pmcck {
- compatible = "atmel,sama5d2-clk-audio-pll-pmc";
- #clock-cells = <0>;
- clocks = <&audio_pll_frac>;
- };
-
- utmi: utmick {
- compatible = "atmel,at91sam9x5-clk-utmi";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_LOCKU>;
- clocks = <&main>;
- };
-
- mck: masterck {
- compatible = "atmel,at91sam9x5-clk-master";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_MCKRDY>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
- atmel,clk-output-range = <124000000 166000000>;
- atmel,clk-divisors = <1 2 4 3>;
- };
-
- h32ck: h32mxck {
- #clock-cells = <0>;
- compatible = "atmel,sama5d4-clk-h32mx";
- clocks = <&mck>;
- };
-
- usb: usbck {
- compatible = "atmel,at91sam9x5-clk-usb";
- #clock-cells = <0>;
- clocks = <&plladiv>, <&utmi>;
- };
-
- prog: progck {
- compatible = "atmel,at91sam9x5-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
-
- prog2: prog2 {
- #clock-cells = <0>;
- reg = <2>;
- interrupts = <AT91_PMC_PCKRDY(2)>;
- };
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ddrck: ddrck {
- #clock-cells = <0>;
- reg = <2>;
- clocks = <&mck>;
- };
-
- lcdck: lcdck {
- #clock-cells = <0>;
- reg = <3>;
- clocks = <&mck>;
- };
-
- uhpck: uhpck {
- #clock-cells = <0>;
- reg = <6>;
- clocks = <&usb>;
- };
-
- udpck: udpck {
- #clock-cells = <0>;
- reg = <7>;
- clocks = <&usb>;
- };
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
-
- pck2: pck2 {
- #clock-cells = <0>;
- reg = <10>;
- clocks = <&prog2>;
- };
-
- iscck: iscck {
- #clock-cells = <0>;
- reg = <18>;
- clocks = <&mck>;
- };
- };
-
- periph32ck {
- compatible = "atmel,at91sam9x5-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&h32ck>;
-
- macb0_clk: macb0_clk {
- #clock-cells = <0>;
- reg = <5>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- tdes_clk: tdes_clk {
- #clock-cells = <0>;
- reg = <11>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- matrix1_clk: matrix1_clk {
- #clock-cells = <0>;
- reg = <14>;
- };
-
- hsmc_clk: hsmc_clk {
- #clock-cells = <0>;
- reg = <17>;
- };
-
- pioA_clk: pioA_clk {
- #clock-cells = <0>;
- reg = <18>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- flx0_clk: flx0_clk {
- #clock-cells = <0>;
- reg = <19>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- flx1_clk: flx1_clk {
- #clock-cells = <0>;
- reg = <20>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- flx2_clk: flx2_clk {
- #clock-cells = <0>;
- reg = <21>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- flx3_clk: flx3_clk {
- #clock-cells = <0>;
- reg = <22>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- flx4_clk: flx4_clk {
- #clock-cells = <0>;
- reg = <23>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- uart0_clk: uart0_clk {
- #clock-cells = <0>;
- reg = <24>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- uart1_clk: uart1_clk {
- #clock-cells = <0>;
- reg = <25>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- uart2_clk: uart2_clk {
- #clock-cells = <0>;
- reg = <26>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- uart3_clk: uart3_clk {
- #clock-cells = <0>;
- reg = <27>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- uart4_clk: uart4_clk {
- #clock-cells = <0>;
- reg = <28>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- twi0_clk: twi0_clk {
- reg = <29>;
- #clock-cells = <0>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- twi1_clk: twi1_clk {
- #clock-cells = <0>;
- reg = <30>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <33>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- spi1_clk: spi1_clk {
- #clock-cells = <0>;
- reg = <34>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- tcb0_clk: tcb0_clk {
- #clock-cells = <0>;
- reg = <35>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- tcb1_clk: tcb1_clk {
- #clock-cells = <0>;
- reg = <36>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- pwm_clk: pwm_clk {
- #clock-cells = <0>;
- reg = <38>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- adc_clk: adc_clk {
- #clock-cells = <0>;
- reg = <40>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- uhphs_clk: uhphs_clk {
- #clock-cells = <0>;
- reg = <41>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- udphs_clk: udphs_clk {
- #clock-cells = <0>;
- reg = <42>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <43>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- ssc1_clk: ssc1_clk {
- #clock-cells = <0>;
- reg = <44>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- trng_clk: trng_clk {
- #clock-cells = <0>;
- reg = <47>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- pdmic_clk: pdmic_clk {
- #clock-cells = <0>;
- reg = <48>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- securam_clk: securam_clk {
- #clock-cells = <0>;
- reg = <51>;
- };
-
- i2s0_clk: i2s0_clk {
- #clock-cells = <0>;
- reg = <54>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- i2s1_clk: i2s1_clk {
- #clock-cells = <0>;
- reg = <55>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- can0_clk: can0_clk {
- #clock-cells = <0>;
- reg = <56>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- can1_clk: can1_clk {
- #clock-cells = <0>;
- reg = <57>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- classd_clk: classd_clk {
- #clock-cells = <0>;
- reg = <59>;
- atmel,clk-output-range = <0 83000000>;
- };
- };
-
- periph64ck {
- compatible = "atmel,at91sam9x5-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- dma0_clk: dma0_clk {
- #clock-cells = <0>;
- reg = <6>;
- };
-
- dma1_clk: dma1_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- aes_clk: aes_clk {
- #clock-cells = <0>;
- reg = <9>;
- };
-
- aesb_clk: aesb_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- sha_clk: sha_clk {
- #clock-cells = <0>;
- reg = <12>;
- };
-
- mpddr_clk: mpddr_clk {
- #clock-cells = <0>;
- reg = <13>;
- };
-
- matrix0_clk: matrix0_clk {
- #clock-cells = <0>;
- reg = <15>;
- };
-
- sdmmc0_hclk: sdmmc0_hclk {
- #clock-cells = <0>;
- reg = <31>;
- };
-
- sdmmc1_hclk: sdmmc1_hclk {
- #clock-cells = <0>;
- reg = <32>;
- };
-
- lcdc_clk: lcdc_clk {
- #clock-cells = <0>;
- reg = <45>;
- };
-
- isc_clk: isc_clk {
- #clock-cells = <0>;
- reg = <46>;
- };
-
- qspi0_clk: qspi0_clk {
- #clock-cells = <0>;
- reg = <52>;
- };
-
- qspi1_clk: qspi1_clk {
- #clock-cells = <0>;
- reg = <53>;
- };
- };
-
- gck {
- compatible = "atmel,sama5d2-clk-generated";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
-
- sdmmc0_gclk: sdmmc0_gclk {
- #clock-cells = <0>;
- reg = <31>;
- };
-
- sdmmc1_gclk: sdmmc1_gclk {
- #clock-cells = <0>;
- reg = <32>;
- };
-
- tcb0_gclk: tcb0_gclk {
- #clock-cells = <0>;
- reg = <35>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- tcb1_gclk: tcb1_gclk {
- #clock-cells = <0>;
- reg = <36>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- pwm_gclk: pwm_gclk {
- #clock-cells = <0>;
- reg = <38>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- isc_gclk: isc_gclk {
- #clock-cells = <0>;
- reg = <46>;
- };
-
- pdmic_gclk: pdmic_gclk {
- #clock-cells = <0>;
- reg = <48>;
- };
-
- i2s0_gclk: i2s0_gclk {
- #clock-cells = <0>;
- reg = <54>;
- };
-
- i2s1_gclk: i2s1_gclk {
- #clock-cells = <0>;
- reg = <55>;
- };
-
- can0_gclk: can0_gclk {
- #clock-cells = <0>;
- reg = <56>;
- atmel,clk-output-range = <0 80000000>;
- };
-
- can1_gclk: can1_gclk {
- #clock-cells = <0>;
- reg = <57>;
- atmel,clk-output-range = <0 80000000>;
- };
-
- classd_gclk: classd_gclk {
- #clock-cells = <0>;
- reg = <59>;
- atmel,clk-output-range = <0 100000000>;
- };
- };
+ #clock-cells = <2>;
+ clocks = <&clk32k>, <&main_xtal>;
+ clock-names = "slow_clk", "main_xtal";
};
qspi0: spi@f0020000 {
@@ -999,7 +467,7 @@
reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
reg-names = "qspi_base", "qspi_mmap";
interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&qspi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1010,7 +478,7 @@
reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
reg-names = "qspi_base", "qspi_mmap";
interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&qspi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1024,7 +492,7 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(30))>;
dma-names = "tx";
- clocks = <&sha_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "sha_clk";
status = "okay";
};
@@ -1040,7 +508,7 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(27))>;
dma-names = "tx", "rx";
- clocks = <&aes_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "aes_clk";
status = "okay";
};
@@ -1056,7 +524,7 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(7))>;
dma-names = "tx", "rx";
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
clock-names = "spi_clk";
atmel,fifo-size = <16>;
#address-cells = <1>;
@@ -1075,7 +543,7 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(22))>;
dma-names = "tx", "rx";
- clocks = <&ssc0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
clock-names = "pclk";
status = "disabled";
};
@@ -1088,7 +556,7 @@
67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&macb0_clk>, <&macb0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -1099,7 +567,7 @@
#size-cells = <0>;
reg = <0xf800c000 0x100>;
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb0_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
@@ -1109,7 +577,7 @@
#size-cells = <0>;
reg = <0xf8010000 0x100>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb1_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
@@ -1117,7 +585,7 @@
compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
reg = <0xf8014000 0x1000>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
- clocks = <&hsmc_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -1137,7 +605,7 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(50))>;
dma-names = "rx";
- clocks = <&pdmic_clk>, <&pdmic_gclk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>;
clock-names = "pclk", "gclk";
status = "disabled";
};
@@ -1153,7 +621,7 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(36))>;
dma-names = "tx", "rx";
- clocks = <&uart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
clock-names = "usart";
status = "disabled";
};
@@ -1169,7 +637,7 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(38))>;
dma-names = "tx", "rx";
- clocks = <&uart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
clock-names = "usart";
status = "disabled";
};
@@ -1185,7 +653,7 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(40))>;
dma-names = "tx", "rx";
- clocks = <&uart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
clock-names = "usart";
status = "disabled";
};
@@ -1203,7 +671,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
atmel,fifo-size = <16>;
status = "disabled";
};
@@ -1213,7 +681,7 @@
reg = <0xf802c000 0x4000>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
#pwm-cells = <3>;
- clocks = <&pwm_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
};
sfr: sfr@f8030000 {
@@ -1224,7 +692,7 @@
flx0: flexcom@f8034000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8034000 0x200>;
- clocks = <&flx0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8034000 0x800>;
@@ -1234,7 +702,7 @@
flx1: flexcom@f8038000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8038000 0x200>;
- clocks = <&flx1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8038000 0x800>;
@@ -1244,7 +712,7 @@
securam: sram@f8044000 {
compatible = "atmel,sama5d2-securam", "mmio-sram";
reg = <0xf8044000 0x1420>;
- clocks = <&securam_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xf8044000 0x1420>;
@@ -1269,7 +737,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xf8048030 0x10>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
- clocks = <&h32ck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
};
watchdog@f8048040 {
@@ -1302,10 +770,10 @@
interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
<64 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-names = "int0", "int1";
- clocks = <&can0_clk>, <&can0_gclk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>;
clock-names = "hclk", "cclk";
- assigned-clocks = <&can0_gclk>;
- assigned-clock-parents = <&utmi>;
+ assigned-clocks = <&pmc PMC_TYPE_GCK 56>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
assigned-clock-rates = <40000000>;
bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
status = "disabled";
@@ -1322,7 +790,7 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(9))>;
dma-names = "tx", "rx";
- clocks = <&spi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
clock-names = "spi_clk";
atmel,fifo-size = <16>;
#address-cells = <1>;
@@ -1341,7 +809,7 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(42))>;
dma-names = "tx", "rx";
- clocks = <&uart3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
clock-names = "usart";
status = "disabled";
};
@@ -1357,7 +825,7 @@
AT91_XDMAC_DT_PERID(44))>;
dma-names = "tx", "rx";
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&uart4_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
clock-names = "usart";
status = "disabled";
};
@@ -1365,7 +833,7 @@
flx2: flexcom@fc010000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xfc010000 0x200>;
- clocks = <&flx2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xfc010000 0x800>;
@@ -1375,7 +843,7 @@
flx3: flexcom@fc014000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xfc014000 0x200>;
- clocks = <&flx3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xfc014000 0x800>;
@@ -1385,7 +853,7 @@
flx4: flexcom@fc018000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xfc018000 0x200>;
- clocks = <&flx4_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xfc018000 0x800>;
@@ -1396,7 +864,7 @@
compatible = "atmel,at91sam9g45-trng";
reg = <0xfc01c000 0x100>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&trng_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
};
aic: interrupt-controller@fc020000 {
@@ -1420,7 +888,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
atmel,fifo-size = <16>;
status = "disabled";
};
@@ -1429,7 +897,7 @@
compatible = "atmel,sama5d2-adc";
reg = <0xfc030000 0x100>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&adc_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
clock-names = "adc_clk";
dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
dma-names = "rx";
@@ -1451,7 +919,7 @@
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
- clocks = <&pioA_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
};
secumod@fc040000 {
@@ -1470,7 +938,7 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(29))>;
dma-names = "tx", "rx";
- clocks = <&tdes_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
clock-names = "tdes_clk";
status = "okay";
};
@@ -1483,7 +951,7 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(47))>;
dma-names = "tx";
- clocks = <&classd_clk>, <&classd_gclk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
clock-names = "pclk", "gclk";
status = "disabled";
};
@@ -1495,10 +963,10 @@
interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
<65 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-names = "int0", "int1";
- clocks = <&can1_clk>, <&can1_gclk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
clock-names = "hclk", "cclk";
- assigned-clocks = <&can1_gclk>;
- assigned-clock-parents = <&utmi>;
+ assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
assigned-clock-rates = <40000000>;
bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
status = "disabled";
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 18/22] ARM: dts: at91: at91sam9260: switch to new clock bindings
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (16 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 17/22] ARM: dts: at91: sama5d2: switch to new binding Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-16 14:21 ` [PATCH v2 19/22] ARM: dts: at91: at91sam9261: " Alexandre Belloni
` (4 subsequent siblings)
22 siblings, 0 replies; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Switch at91sam9260 and at91sam9g20 boards to the new PMC clock bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
arch/arm/boot/dts/at91sam9260.dtsi | 308 +++--------------------------
arch/arm/boot/dts/at91sam9g20.dtsi | 23 +--
2 files changed, 31 insertions(+), 300 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 9118e29b6d6a..7cd9c3bc4dfb 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -113,276 +113,28 @@
compatible = "atmel,at91sam9260-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main_osc: main_osc {
- compatible = "atmel,at91rm9200-clk-main-osc";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- main: mainck {
- compatible = "atmel,at91rm9200-clk-main";
- #clock-cells = <0>;
- clocks = <&main_osc>;
- };
-
- slow_rc_osc: slow_rc_osc {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-accuracy = <50000000>;
- };
-
- clk32k: slck {
- compatible = "atmel,at91sam9260-clk-slow";
- #clock-cells = <0>;
- clocks = <&slow_rc_osc>, <&slow_xtal>;
- };
-
- plla: pllack {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <1000000 32000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <80000000 160000000 0 1>,
- <150000000 240000000 2 1>;
- };
-
- pllb: pllbck {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKB>;
- clocks = <&main>;
- reg = <1>;
- atmel,clk-input-range = <1000000 5000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
- };
-
- mck: masterck {
- compatible = "atmel,at91rm9200-clk-master";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
- clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
- atmel,clk-output-range = <0 105000000>;
- atmel,clk-divisors = <1 2 4 0>;
- };
-
- usb: usbck {
- compatible = "atmel,at91rm9200-clk-usb";
- #clock-cells = <0>;
- atmel,clk-divisors = <1 2 4 0>;
- clocks = <&pllb>;
- };
-
- prog: progck {
- compatible = "atmel,at91rm9200-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- uhpck: uhpck {
- #clock-cells = <0>;
- reg = <6>;
- clocks = <&usb>;
- };
-
- udpck: udpck {
- #clock-cells = <0>;
- reg = <7>;
- clocks = <&usb>;
- };
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
- };
-
- periphck {
- compatible = "atmel,at91rm9200-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- pioA_clk: pioA_clk {
- #clock-cells = <0>;
- reg = <2>;
- };
-
- pioB_clk: pioB_clk {
- #clock-cells = <0>;
- reg = <3>;
- };
-
- pioC_clk: pioC_clk {
- #clock-cells = <0>;
- reg = <4>;
- };
-
- adc_clk: adc_clk {
- #clock-cells = <0>;
- reg = <5>;
- };
-
- usart0_clk: usart0_clk {
- #clock-cells = <0>;
- reg = <6>;
- };
-
- usart1_clk: usart1_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- usart2_clk: usart2_clk {
- #clock-cells = <0>;
- reg = <8>;
- };
-
- mci0_clk: mci0_clk {
- #clock-cells = <0>;
- reg = <9>;
- };
-
- udc_clk: udc_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- twi0_clk: twi0_clk {
- reg = <11>;
- #clock-cells = <0>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <12>;
- };
-
- spi1_clk: spi1_clk {
- #clock-cells = <0>;
- reg = <13>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <14>;
- };
-
- tc0_clk: tc0_clk {
- #clock-cells = <0>;
- reg = <17>;
- };
-
- tc1_clk: tc1_clk {
- #clock-cells = <0>;
- reg = <18>;
- };
-
- tc2_clk: tc2_clk {
- #clock-cells = <0>;
- reg = <19>;
- };
-
- ohci_clk: ohci_clk {
- #clock-cells = <0>;
- reg = <20>;
- };
-
- macb0_clk: macb0_clk {
- #clock-cells = <0>;
- reg = <21>;
- };
-
- isi_clk: isi_clk {
- #clock-cells = <0>;
- reg = <22>;
- };
-
- usart3_clk: usart3_clk {
- #clock-cells = <0>;
- reg = <23>;
- };
-
- uart0_clk: uart0_clk {
- #clock-cells = <0>;
- reg = <24>;
- };
-
- uart1_clk: uart1_clk {
- #clock-cells = <0>;
- reg = <25>;
- };
-
- tc3_clk: tc3_clk {
- #clock-cells = <0>;
- reg = <26>;
- };
-
- tc4_clk: tc4_clk {
- #clock-cells = <0>;
- reg = <27>;
- };
-
- tc5_clk: tc5_clk {
- #clock-cells = <0>;
- reg = <28>;
- };
- };
+ #clock-cells = <2>;
+ clocks = <&slow_xtal>, <&main_xtal>;
+ clock-names = "slow_xtal", "main_xtal";
};
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
- clocks = <&clk32k>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
- clocks = <&clk32k>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
};
pit: timer@fffffd30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
tcb0: timer@fffa0000 {
@@ -393,7 +145,7 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE PMC_SLOW>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -405,7 +157,7 @@
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
27 IRQ_TYPE_LEVEL_HIGH 0
28 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE PMC_SLOW>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -746,7 +498,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioA_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
@@ -757,7 +509,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff800 {
@@ -768,7 +520,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioC_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
};
@@ -778,7 +530,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -791,7 +543,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
- clocks = <&usart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "usart";
status = "disabled";
};
@@ -804,7 +556,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
- clocks = <&usart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@@ -817,7 +569,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
- clocks = <&usart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
@@ -830,7 +582,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
- clocks = <&usart3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "usart";
status = "disabled";
};
@@ -843,7 +595,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
- clocks = <&uart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
clock-names = "usart";
status = "disabled";
};
@@ -856,7 +608,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- clocks = <&uart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
clock-names = "usart";
status = "disabled";
};
@@ -867,7 +619,7 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
- clocks = <&macb0_clk>, <&macb0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>;
clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -876,7 +628,7 @@
compatible = "atmel,at91sam9260-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&udc_clk>, <&udpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>;
clock-names = "pclk", "hclk";
status = "disabled";
};
@@ -887,7 +639,7 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
status = "disabled";
};
@@ -898,7 +650,7 @@
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
- clocks = <&mci0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "mci_clk";
status = "disabled";
};
@@ -909,7 +661,7 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- clocks = <&ssc0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "pclk";
status = "disabled";
};
@@ -922,7 +674,7 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -935,7 +687,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- clocks = <&spi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -946,7 +698,7 @@
compatible = "atmel,at91sam9260-adc";
reg = <0xfffe0000 0x100>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&adc_clk>, <&adc_op_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xf>;
@@ -981,7 +733,7 @@
compatible = "atmel,at91sam9260-rtt";
reg = <0xfffffd20 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&clk32k>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
status = "disabled";
};
@@ -989,7 +741,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&clk32k>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
@@ -1007,7 +759,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -1027,7 +779,7 @@
0x5 0x0 0x60000000 0x10000000
0x6 0x0 0x70000000 0x10000000
0x7 0x0 0x80000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 90705ee6008b..e976fd6bc6fd 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -40,28 +40,7 @@
};
pmc: pmc@fffffc00 {
- plla: pllack {
- atmel,clk-input-range = <2000000 32000000>;
- atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
- <695000000 750000000 1 0>,
- <645000000 700000000 2 0>,
- <595000000 650000000 3 0>,
- <545000000 600000000 0 1>,
- <495000000 550000000 1 1>,
- <445000000 500000000 2 1>,
- <400000000 450000000 3 1>;
- };
-
- pllb: pllbck {
- compatible = "atmel,at91sam9g20-clk-pllb";
- atmel,clk-input-range = <2000000 32000000>;
- atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
- };
-
- mck: masterck {
- atmel,clk-output-range = <0 133000000>;
- atmel,clk-divisors = <1 2 4 6>;
- };
+ compatible = "atmel,at91sam9g20-pmc", "atmel,at91sam9260-pmc", "syscon";
};
};
};
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 19/22] ARM: dts: at91: at91sam9261: switch to new clock bindings
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (17 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 18/22] ARM: dts: at91: at91sam9260: switch to new clock bindings Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-16 14:21 ` [PATCH v2 20/22] ARM: dts: at91: at91sam9263: " Alexandre Belloni
` (3 subsequent siblings)
22 siblings, 0 replies; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Switch at91sam9261 boards to the new PMC clock bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
arch/arm/boot/dts/at91sam9261.dtsi | 287 +++--------------------------
1 file changed, 23 insertions(+), 264 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index 33f09d5ea020..01d700b63b45 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -75,7 +75,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&ohci_clk>, <&hclk0>, <&uhpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 16>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -86,7 +86,7 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fb>;
- clocks = <&lcd_clk>, <&hclk1>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_SYSTEM 17>;
clock-names = "lcdc_clk", "hclk";
status = "disabled";
};
@@ -106,7 +106,7 @@
0x5 0x0 0x60000000 0x10000000
0x6 0x0 0x70000000 0x10000000
0x7 0x0 0x80000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
@@ -132,7 +132,7 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
<18 IRQ_TYPE_LEVEL_HIGH 0>,
<19 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -140,7 +140,7 @@
compatible = "atmel,at91sam9261-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&udc_clk>, <&udpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>;
clock-names = "pclk", "hclk";
atmel,matrix = <&matrix>;
status = "disabled";
@@ -154,7 +154,7 @@
pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&mci0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "mci_clk";
status = "disabled";
};
@@ -167,7 +167,7 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
status = "disabled";
};
@@ -179,7 +179,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
- clocks = <&usart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "usart";
status = "disabled";
};
@@ -192,7 +192,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
- clocks = <&usart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@@ -205,7 +205,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
- clocks = <&usart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
@@ -216,7 +216,7 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- clocks = <&ssc0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "pclk";
status = "disabled";
};
@@ -227,7 +227,7 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
- clocks = <&ssc1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
clock-names = "pclk";
status = "disabled";
};
@@ -238,7 +238,7 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
- clocks = <&ssc2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
clock-names = "pclk";
status = "disabled";
};
@@ -252,7 +252,7 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -265,7 +265,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- clocks = <&spi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -299,7 +299,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -563,7 +563,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioA_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
@@ -574,7 +574,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff800 {
@@ -585,7 +585,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioC_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
};
@@ -593,250 +593,9 @@
compatible = "atmel,at91sam9261-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main_osc: main_osc {
- compatible = "atmel,at91rm9200-clk-main-osc";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- main: mainck {
- compatible = "atmel,at91rm9200-clk-main";
- #clock-cells = <0>;
- clocks = <&main_osc>;
- };
-
- plla: pllack {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <1000000 32000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
- <190000000 240000000 2 1>;
- };
-
- pllb: pllbck {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKB>;
- clocks = <&main>;
- reg = <1>;
- atmel,clk-input-range = <1000000 5000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
- };
-
- mck: masterck {
- compatible = "atmel,at91rm9200-clk-master";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
- clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
- atmel,clk-output-range = <0 94000000>;
- atmel,clk-divisors = <1 2 4 0>;
- };
-
- usb: usbck {
- compatible = "atmel,at91rm9200-clk-usb";
- #clock-cells = <0>;
- atmel,clk-divisors = <1 2 4 0>;
- clocks = <&pllb>;
- };
-
- prog: progck {
- compatible = "atmel,at91rm9200-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
-
- prog2: prog2 {
- #clock-cells = <0>;
- reg = <2>;
- interrupts = <AT91_PMC_PCKRDY(2)>;
- };
-
- prog3: prog3 {
- #clock-cells = <0>;
- reg = <3>;
- interrupts = <AT91_PMC_PCKRDY(3)>;
- };
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- uhpck: uhpck {
- #clock-cells = <0>;
- reg = <6>;
- clocks = <&usb>;
- };
-
- udpck: udpck {
- #clock-cells = <0>;
- reg = <7>;
- clocks = <&usb>;
- };
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
-
- pck2: pck2 {
- #clock-cells = <0>;
- reg = <10>;
- clocks = <&prog2>;
- };
-
- pck3: pck3 {
- #clock-cells = <0>;
- reg = <11>;
- clocks = <&prog3>;
- };
-
- hclk0: hclk0 {
- #clock-cells = <0>;
- reg = <16>;
- clocks = <&mck>;
- };
-
- hclk1: hclk1 {
- #clock-cells = <0>;
- reg = <17>;
- clocks = <&mck>;
- };
- };
-
- periphck {
- compatible = "atmel,at91rm9200-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- pioA_clk: pioA_clk {
- #clock-cells = <0>;
- reg = <2>;
- };
-
- pioB_clk: pioB_clk {
- #clock-cells = <0>;
- reg = <3>;
- };
-
- pioC_clk: pioC_clk {
- #clock-cells = <0>;
- reg = <4>;
- };
-
- usart0_clk: usart0_clk {
- #clock-cells = <0>;
- reg = <6>;
- };
-
- usart1_clk: usart1_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- usart2_clk: usart2_clk {
- #clock-cells = <0>;
- reg = <8>;
- };
-
- mci0_clk: mci0_clk {
- #clock-cells = <0>;
- reg = <9>;
- };
-
- udc_clk: udc_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- twi0_clk: twi0_clk {
- reg = <11>;
- #clock-cells = <0>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <12>;
- };
-
- spi1_clk: spi1_clk {
- #clock-cells = <0>;
- reg = <13>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <14>;
- };
-
- ssc1_clk: ssc1_clk {
- #clock-cells = <0>;
- reg = <15>;
- };
-
- ssc2_clk: ssc2_clk {
- #clock-cells = <0>;
- reg = <16>;
- };
-
- tc0_clk: tc0_clk {
- #clock-cells = <0>;
- reg = <17>;
- };
-
- tc1_clk: tc1_clk {
- #clock-cells = <0>;
- reg = <18>;
- };
-
- tc2_clk: tc2_clk {
- #clock-cells = <0>;
- reg = <19>;
- };
-
- ohci_clk: ohci_clk {
- #clock-cells = <0>;
- reg = <20>;
- };
-
- lcd_clk: lcd_clk {
- #clock-cells = <0>;
- reg = <21>;
- };
- };
+ #clock-cells = <2>;
+ clocks = <&slow_xtal>, <&main_xtal>;
+ clock-names = "slow_xtal", "main_xtal";
};
rstc@fffffd00 {
@@ -855,7 +614,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
rtc@fffffd20 {
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 20/22] ARM: dts: at91: at91sam9263: switch to new clock bindings
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (18 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 19/22] ARM: dts: at91: at91sam9261: " Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-16 14:21 ` [PATCH v2 21/22] ARM: dts: at91: at91sam9x5: " Alexandre Belloni
` (2 subsequent siblings)
22 siblings, 0 replies; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Switch at91sam9263 boards to the new PMC clock bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
arch/arm/boot/dts/at91sam9263.dtsi | 315 +++--------------------------
1 file changed, 30 insertions(+), 285 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index af68a86c9973..c5766da4e54e 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -96,264 +96,9 @@
compatible = "atmel,at91sam9263-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main_osc: main_osc {
- compatible = "atmel,at91rm9200-clk-main-osc";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- main: mainck {
- compatible = "atmel,at91rm9200-clk-main";
- #clock-cells = <0>;
- clocks = <&main_osc>;
- };
-
- plla: pllack {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <1000000 32000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
- <190000000 240000000 2 1>;
- };
-
- pllb: pllbck {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKB>;
- clocks = <&main>;
- reg = <1>;
- atmel,clk-input-range = <1000000 32000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
- <190000000 240000000 2 1>;
- };
-
- mck: masterck {
- compatible = "atmel,at91rm9200-clk-master";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
- clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
- atmel,clk-output-range = <0 120000000>;
- atmel,clk-divisors = <1 2 4 0>;
- };
-
- usb: usbck {
- compatible = "atmel,at91rm9200-clk-usb";
- #clock-cells = <0>;
- atmel,clk-divisors = <1 2 4 0>;
- clocks = <&pllb>;
- };
-
- prog: progck {
- compatible = "atmel,at91rm9200-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
-
- prog2: prog2 {
- #clock-cells = <0>;
- reg = <2>;
- interrupts = <AT91_PMC_PCKRDY(2)>;
- };
-
- prog3: prog3 {
- #clock-cells = <0>;
- reg = <3>;
- interrupts = <AT91_PMC_PCKRDY(3)>;
- };
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- uhpck: uhpck {
- #clock-cells = <0>;
- reg = <6>;
- clocks = <&usb>;
- };
-
- udpck: udpck {
- #clock-cells = <0>;
- reg = <7>;
- clocks = <&usb>;
- };
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
-
- pck2: pck2 {
- #clock-cells = <0>;
- reg = <10>;
- clocks = <&prog2>;
- };
-
- pck3: pck3 {
- #clock-cells = <0>;
- reg = <11>;
- clocks = <&prog3>;
- };
- };
-
- periphck {
- compatible = "atmel,at91rm9200-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- pioA_clk: pioA_clk {
- #clock-cells = <0>;
- reg = <2>;
- };
-
- pioB_clk: pioB_clk {
- #clock-cells = <0>;
- reg = <3>;
- };
-
- pioCDE_clk: pioCDE_clk {
- #clock-cells = <0>;
- reg = <4>;
- };
-
- usart0_clk: usart0_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- usart1_clk: usart1_clk {
- #clock-cells = <0>;
- reg = <8>;
- };
-
- usart2_clk: usart2_clk {
- #clock-cells = <0>;
- reg = <9>;
- };
-
- mci0_clk: mci0_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- mci1_clk: mci1_clk {
- #clock-cells = <0>;
- reg = <11>;
- };
-
- can_clk: can_clk {
- #clock-cells = <0>;
- reg = <12>;
- };
-
- twi0_clk: twi0_clk {
- #clock-cells = <0>;
- reg = <13>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <14>;
- };
-
- spi1_clk: spi1_clk {
- #clock-cells = <0>;
- reg = <15>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <16>;
- };
-
- ssc1_clk: ssc1_clk {
- #clock-cells = <0>;
- reg = <17>;
- };
-
- ac97_clk: ac97_clk {
- #clock-cells = <0>;
- reg = <18>;
- };
-
- tcb_clk: tcb_clk {
- #clock-cells = <0>;
- reg = <19>;
- };
-
- pwm_clk: pwm_clk {
- #clock-cells = <0>;
- reg = <20>;
- };
-
- macb0_clk: macb0_clk {
- #clock-cells = <0>;
- reg = <21>;
- };
-
- g2de_clk: g2de_clk {
- #clock-cells = <0>;
- reg = <23>;
- };
-
- udc_clk: udc_clk {
- #clock-cells = <0>;
- reg = <24>;
- };
-
- isi_clk: isi_clk {
- #clock-cells = <0>;
- reg = <25>;
- };
-
- lcd_clk: lcd_clk {
- #clock-cells = <0>;
- reg = <26>;
- };
-
- dma_clk: dma_clk {
- #clock-cells = <0>;
- reg = <27>;
- };
-
- ohci_clk: ohci_clk {
- #clock-cells = <0>;
- reg = <29>;
- };
- };
+ #clock-cells = <2>;
+ clocks = <&slow_xtal>, <&main_xtal>;
+ clock-names = "slow_xtal", "main_xtal";
};
ramc0: ramc@ffffe200 {
@@ -385,7 +130,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
tcb0: timer@fff7c000 {
@@ -394,7 +139,7 @@
#size-cells = <0>;
reg = <0xfff7c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb_clk>, <&slow_xtal>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>;
clock-names = "t0_clk", "slow_clk";
};
@@ -736,7 +481,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioA_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff400 {
@@ -747,7 +492,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff600 {
@@ -758,7 +503,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioCDE_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
pioD: gpio@fffff800 {
@@ -769,7 +514,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioCDE_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
pioE: gpio@fffffa00 {
@@ -780,7 +525,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioCDE_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
};
@@ -790,7 +535,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -803,7 +548,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
- clocks = <&usart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@@ -816,7 +561,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
- clocks = <&usart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
@@ -829,7 +574,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
- clocks = <&usart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "usart";
status = "disabled";
};
@@ -840,7 +585,7 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- clocks = <&ssc0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
clock-names = "pclk";
status = "disabled";
};
@@ -851,7 +596,7 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
- clocks = <&ssc1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
clock-names = "pclk";
status = "disabled";
};
@@ -862,7 +607,7 @@
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ac97>;
- clocks = <&ac97_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
clock-names = "ac97_clk";
status = "disabled";
};
@@ -873,7 +618,7 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
- clocks = <&macb0_clk>, <&macb0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>;
clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -882,7 +627,7 @@
compatible = "atmel,at91sam9263-udc";
reg = <0xfff78000 0x4000>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&udc_clk>, <&udpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_SYSTEM 7>;
clock-names = "pclk", "hclk";
status = "disabled";
};
@@ -893,7 +638,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
status = "disabled";
};
@@ -904,7 +649,7 @@
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&mci0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
clock-names = "mci_clk";
status = "disabled";
};
@@ -916,7 +661,7 @@
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&mci1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
clock-names = "mci_clk";
status = "disabled";
};
@@ -940,7 +685,7 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -953,7 +698,7 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- clocks = <&spi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -963,7 +708,7 @@
reg = <0xfffb8000 0x300>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
- clocks = <&pwm_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
clock-names = "pwm_clk";
status = "disabled";
};
@@ -974,7 +719,7 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_rx_tx>;
- clocks = <&can_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "can_clk";
};
@@ -1007,7 +752,7 @@
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fb>;
- clocks = <&lcd_clk>, <&lcd_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 26>;
clock-names = "lcdc_clk", "hclk";
status = "disabled";
};
@@ -1016,7 +761,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00a00000 0x100000>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -1034,7 +779,7 @@
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller0: nand-controller {
@@ -1055,7 +800,7 @@
reg = <0x80000000 0x20000000>;
ranges = <0x0 0x0 0x80000000 0x10000000
0x1 0x0 0x90000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller1: nand-controller {
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 21/22] ARM: dts: at91: at91sam9x5: switch to new clock bindings
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (19 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 20/22] ARM: dts: at91: at91sam9263: " Alexandre Belloni
@ 2018-10-16 14:21 ` Alexandre Belloni
2018-10-16 14:22 ` [PATCH v2 22/22] ARM: dts: at91: at91sam9rl: " Alexandre Belloni
2018-10-17 16:50 ` [PATCH v2 00/22] clk: at91: Rework DT bindings Stephen Boyd
22 siblings, 0 replies; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:21 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Switch at91sam9x5 boards to the new PMC clock bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
arch/arm/boot/dts/at91sam9g15.dtsi | 4 +
arch/arm/boot/dts/at91sam9g25.dtsi | 4 +
arch/arm/boot/dts/at91sam9g25ek.dts | 4 +-
arch/arm/boot/dts/at91sam9g35.dtsi | 4 +
arch/arm/boot/dts/at91sam9x25.dtsi | 4 +
arch/arm/boot/dts/at91sam9x35.dtsi | 4 +
arch/arm/boot/dts/at91sam9x5.dtsi | 326 +++--------------------
arch/arm/boot/dts/at91sam9x5_can.dtsi | 18 +-
arch/arm/boot/dts/at91sam9x5_isi.dtsi | 11 +-
arch/arm/boot/dts/at91sam9x5_lcd.dtsi | 19 +-
arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 11 +-
arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 11 +-
arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 11 +-
13 files changed, 62 insertions(+), 369 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
index 27de7dc0f0e0..b34a6c65bd44 100644
--- a/arch/arm/boot/dts/at91sam9g15.dtsi
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -24,6 +24,10 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
+
+ pmc: pmc@fffffc00 {
+ compatible = "atmel,at91sam9g15-pmc", "atmel,at91sam9x5-pmc", "syscon";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index 0898213f3bb2..d8bb56253e64 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -26,6 +26,10 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
+
+ pmc: pmc@fffffc00 {
+ compatible = "atmel,at91sam9g25-pmc", "atmel,at91sam9x5-pmc", "syscon";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 31fecc2cdaf9..ac730812a81d 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -32,9 +32,9 @@
pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;
- clocks = <&pck0>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 8>;
clock-names = "xvclk";
- assigned-clocks = <&pck0>;
+ assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>;
assigned-clock-rates = <25000000>;
status = "okay";
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
index ff4115886f97..333e158feb61 100644
--- a/arch/arm/boot/dts/at91sam9g35.dtsi
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -25,6 +25,10 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
+
+ pmc: pmc@fffffc00 {
+ compatible = "atmel,at91sam9g35-pmc", "atmel,at91sam9x5-pmc", "syscon";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index 3c5fa3388997..a99703a262c9 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -27,6 +27,10 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
+
+ pmc: pmc@fffffc00 {
+ compatible = "atmel,at91sam9x25-pmc", "atmel,at91sam9x5-pmc", "syscon";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index d9054e8167b7..bca274d33f68 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -26,6 +26,10 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
+
+ pmc: pmc@fffffc00 {
+ compatible = "atmel,at91sam9x35-pmc", "atmel,at91sam9x5-pmc", "syscon";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 11c0ef102ab1..07443a387a8f 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -111,7 +111,7 @@
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
- clocks = <&ddrck>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 2>;
clock-names = "ddrck";
};
@@ -124,269 +124,9 @@
compatible = "atmel,at91sam9x5-pmc", "syscon";
reg = <0xfffffc00 0x200>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main_rc_osc: main_rc_osc {
- compatible = "atmel,at91sam9x5-clk-main-rc-osc";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
- clock-frequency = <12000000>;
- clock-accuracy = <50000000>;
- };
-
- main_osc: main_osc {
- compatible = "atmel,at91rm9200-clk-main-osc";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- main: mainck {
- compatible = "atmel,at91sam9x5-clk-main";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
- clocks = <&main_rc_osc>, <&main_osc>;
- };
-
- plla: pllack {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <2000000 32000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <745000000 800000000 0 0
- 695000000 750000000 1 0
- 645000000 700000000 2 0
- 595000000 650000000 3 0
- 545000000 600000000 0 1
- 495000000 555000000 1 1
- 445000000 500000000 2 1
- 400000000 450000000 3 1>;
- };
-
- plladiv: plladivck {
- compatible = "atmel,at91sam9x5-clk-plldiv";
- #clock-cells = <0>;
- clocks = <&plla>;
- };
-
- utmi: utmick {
- compatible = "atmel,at91sam9x5-clk-utmi";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKU>;
- clocks = <&main>;
- };
-
- mck: masterck {
- compatible = "atmel,at91sam9x5-clk-master";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
- atmel,clk-output-range = <0 133333333>;
- atmel,clk-divisors = <1 2 4 3>;
- atmel,master-clk-have-div3-pres;
- };
-
- usb: usbck {
- compatible = "atmel,at91sam9x5-clk-usb";
- #clock-cells = <0>;
- clocks = <&plladiv>, <&utmi>;
- };
-
- prog: progck {
- compatible = "atmel,at91sam9x5-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
- };
-
- smd: smdclk {
- compatible = "atmel,at91sam9x5-clk-smd";
- #clock-cells = <0>;
- clocks = <&plladiv>, <&utmi>;
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ddrck: ddrck {
- #clock-cells = <0>;
- reg = <2>;
- clocks = <&mck>;
- };
-
- smdck: smdck {
- #clock-cells = <0>;
- reg = <4>;
- clocks = <&smd>;
- };
-
- uhpck: uhpck {
- #clock-cells = <0>;
- reg = <6>;
- clocks = <&usb>;
- };
-
- udpck: udpck {
- #clock-cells = <0>;
- reg = <7>;
- clocks = <&usb>;
- };
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
- };
-
- periphck {
- compatible = "atmel,at91sam9x5-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- pioAB_clk: pioAB_clk {
- #clock-cells = <0>;
- reg = <2>;
- };
-
- pioCD_clk: pioCD_clk {
- #clock-cells = <0>;
- reg = <3>;
- };
-
- smd_clk: smd_clk {
- #clock-cells = <0>;
- reg = <4>;
- };
-
- usart0_clk: usart0_clk {
- #clock-cells = <0>;
- reg = <5>;
- };
-
- usart1_clk: usart1_clk {
- #clock-cells = <0>;
- reg = <6>;
- };
-
- usart2_clk: usart2_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- twi0_clk: twi0_clk {
- reg = <9>;
- #clock-cells = <0>;
- };
-
- twi1_clk: twi1_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- twi2_clk: twi2_clk {
- #clock-cells = <0>;
- reg = <11>;
- };
-
- mci0_clk: mci0_clk {
- #clock-cells = <0>;
- reg = <12>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <13>;
- };
-
- spi1_clk: spi1_clk {
- #clock-cells = <0>;
- reg = <14>;
- };
-
- uart0_clk: uart0_clk {
- #clock-cells = <0>;
- reg = <15>;
- };
-
- uart1_clk: uart1_clk {
- #clock-cells = <0>;
- reg = <16>;
- };
-
- tcb0_clk: tcb0_clk {
- #clock-cells = <0>;
- reg = <17>;
- };
-
- pwm_clk: pwm_clk {
- #clock-cells = <0>;
- reg = <18>;
- };
-
- adc_clk: adc_clk {
- #clock-cells = <0>;
- reg = <19>;
- };
-
- dma0_clk: dma0_clk {
- #clock-cells = <0>;
- reg = <20>;
- };
-
- dma1_clk: dma1_clk {
- #clock-cells = <0>;
- reg = <21>;
- };
-
- uhphs_clk: uhphs_clk {
- #clock-cells = <0>;
- reg = <22>;
- };
-
- udphs_clk: udphs_clk {
- #clock-cells = <0>;
- reg = <23>;
- };
-
- mci1_clk: mci1_clk {
- #clock-cells = <0>;
- reg = <26>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <28>;
- };
- };
+ #clock-cells = <2>;
+ clocks = <&clk32k>, <&main_xtal>;
+ clock-names = "slow_clk", "main_xtal";
};
reset_controller: rstc@fffffe00 {
@@ -405,7 +145,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
sckc@fffffe50 {
@@ -438,7 +178,7 @@
#size-cells = <0>;
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb0_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
@@ -448,7 +188,7 @@
#size-cells = <0>;
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb0_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
@@ -457,7 +197,7 @@
reg = <0xffffec00 0x200>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
- clocks = <&dma0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
clock-names = "dma_clk";
};
@@ -466,7 +206,7 @@
reg = <0xffffee00 0x200>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
- clocks = <&dma1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
clock-names = "dma_clk";
};
@@ -864,7 +604,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioAB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
@@ -876,7 +616,7 @@
#gpio-lines = <19>;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioAB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioC: gpio@fffff800 {
@@ -887,7 +627,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioCD_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioD: gpio@fffffa00 {
@@ -899,7 +639,7 @@
#gpio-lines = <22>;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioCD_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
};
@@ -912,7 +652,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- clocks = <&ssc0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
clock-names = "pclk";
status = "disabled";
};
@@ -924,7 +664,7 @@
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
dma-names = "rxtx";
pinctrl-names = "default";
- clocks = <&mci0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "mci_clk";
#address-cells = <1>;
#size-cells = <0>;
@@ -938,7 +678,7 @@
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
dma-names = "rxtx";
pinctrl-names = "default";
- clocks = <&mci1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
clock-names = "mci_clk";
#address-cells = <1>;
#size-cells = <0>;
@@ -954,7 +694,7 @@
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,
<&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -968,7 +708,7 @@
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>,
<&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
- clocks = <&usart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
clock-names = "usart";
status = "disabled";
};
@@ -982,7 +722,7 @@
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>,
<&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
- clocks = <&usart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "usart";
status = "disabled";
};
@@ -996,7 +736,7 @@
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>,
<&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
- clocks = <&usart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@@ -1012,7 +752,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
status = "disabled";
};
@@ -1027,7 +767,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&twi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
status = "disabled";
};
@@ -1042,7 +782,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&twi2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
status = "disabled";
};
@@ -1052,7 +792,7 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
- clocks = <&uart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
clock-names = "usart";
status = "disabled";
};
@@ -1063,7 +803,7 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- clocks = <&uart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
clock-names = "usart";
status = "disabled";
};
@@ -1074,7 +814,7 @@
compatible = "atmel,at91sam9x5-adc";
reg = <0xf804c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&adc_clk>,
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>,
<&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
@@ -1121,7 +861,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -1137,7 +877,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- clocks = <&spi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -1149,7 +889,7 @@
reg = <0x00500000 0x80000
0xf803c000 0x400>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&utmi>, <&udphs_clk>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "hclk", "pclk";
status = "disabled";
@@ -1229,7 +969,7 @@
compatible = "atmel,at91sam9rl-pwm";
reg = <0xf8034000 0x300>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
- clocks = <&pwm_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
#pwm-cells = <3>;
status = "disabled";
};
@@ -1239,7 +979,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -1248,7 +988,7 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&utmi>, <&uhphs_clk>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
@@ -1266,7 +1006,7 @@
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi
index 8eb2f9c1b978..125f9e3b49ad 100644
--- a/arch/arm/boot/dts/at91sam9x5_can.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi
@@ -13,27 +13,13 @@
/ {
ahb {
apb {
- pmc: pmc@fffffc00 {
- periphck {
- can0_clk: can0_clk {
- #clock-cells = <0>;
- reg = <29>;
- };
-
- can1_clk: can1_clk {
- #clock-cells = <0>;
- reg = <30>;
- };
- };
- };
-
can0: can@f8000000 {
compatible = "atmel,at91sam9x5-can";
reg = <0xf8000000 0x300>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_rx_tx>;
- clocks = <&can0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
clock-names = "can_clk";
status = "disabled";
};
@@ -44,7 +30,7 @@
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_rx_tx>;
- clocks = <&can1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
clock-names = "can_clk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
index 8fc45ca4dcb5..c3e45b57b6a2 100644
--- a/arch/arm/boot/dts/at91sam9x5_isi.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
@@ -44,22 +44,13 @@
};
};
- pmc: pmc@fffffc00 {
- periphck {
- isi_clk: isi_clk {
- #clock-cells = <0>;
- reg = <25>;
- };
- };
- };
-
isi: isi@f8048000 {
compatible = "atmel,at91sam9g45-isi";
reg = <0xf8048000 0x4000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isi_data_0_7>;
- clocks = <&isi_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
clock-names = "isi_clk";
status = "disabled";
port {
diff --git a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi
index 1629db9dd563..12595fb11691 100644
--- a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi
@@ -17,7 +17,7 @@
compatible = "atmel,at91sam9x5-hlcdc";
reg = <0xf8038000 0x4000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
status = "disabled";
@@ -143,23 +143,6 @@
};
};
};
-
- pmc: pmc@fffffc00 {
- periphck {
- lcdc_clk: lcdc_clk {
- #clock-cells = <0>;
- reg = <25>;
- };
- };
-
- systemck {
- lcdck: lcdck {
- #clock-cells = <0>;
- reg = <3>;
- clocks = <&mck>;
- };
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
index 73d7e30965ba..57c2e5a4fb53 100644
--- a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
@@ -43,22 +43,13 @@
};
};
- pmc: pmc@fffffc00 {
- periphck {
- macb0_clk: macb0_clk {
- #clock-cells = <0>;
- reg = <24>;
- };
- };
- };
-
macb0: ethernet@f802c000 {
compatible = "cdns,at91sam9260-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
- clocks = <&macb0_clk>, <&macb0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
clock-names = "hclk", "pclk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
index d81980c40c7d..59b8da87d3c1 100644
--- a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
@@ -31,22 +31,13 @@
};
};
- pmc: pmc@fffffc00 {
- periphck {
- macb1_clk: macb1_clk {
- #clock-cells = <0>;
- reg = <27>;
- };
- };
- };
-
macb1: ethernet@f8030000 {
compatible = "cdns,at91sam9260-macb", "cdns,macb";
reg = <0xf8030000 0x100>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb1_rmii>;
- clocks = <&macb1_clk>, <&macb1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
clock-names = "hclk", "pclk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
index a32d12b406a3..9102dfbed5d8 100644
--- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -42,15 +42,6 @@
};
};
- pmc: pmc@fffffc00 {
- periphck {
- usart3_clk: usart3_clk {
- #clock-cells = <0>;
- reg = <8>;
- };
- };
- };
-
usart3: serial@f8028000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8028000 0x200>;
@@ -60,7 +51,7 @@
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>,
<&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
- clocks = <&usart3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 22/22] ARM: dts: at91: at91sam9rl: switch to new clock bindings
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (20 preceding siblings ...)
2018-10-16 14:21 ` [PATCH v2 21/22] ARM: dts: at91: at91sam9x5: " Alexandre Belloni
@ 2018-10-16 14:22 ` Alexandre Belloni
2018-10-17 16:50 ` [PATCH v2 00/22] clk: at91: Rework DT bindings Stephen Boyd
22 siblings, 0 replies; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-16 14:22 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Switch at91sam9rl boards to the new PMC clock bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
arch/arm/boot/dts/at91sam9rl.dtsi | 239 +++---------------------------
1 file changed, 23 insertions(+), 216 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 8fb22030f00b..3862ff2f26e0 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -88,7 +88,7 @@
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fb>;
- clocks = <&lcd_clk>, <&lcd_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "hclk", "lcdc_clk";
status = "disabled";
};
@@ -106,7 +106,7 @@
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
@@ -132,7 +132,7 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
<17 IRQ_TYPE_LEVEL_HIGH 0>,
<18 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>, <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -143,7 +143,7 @@
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
- clocks = <&mci0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
clock-names = "mci_clk";
status = "disabled";
};
@@ -154,7 +154,7 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
status = "disabled";
};
@@ -175,7 +175,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
- clocks = <&usart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "usart";
status = "disabled";
};
@@ -188,7 +188,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
- clocks = <&usart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@@ -201,7 +201,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
- clocks = <&usart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
@@ -214,7 +214,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
- clocks = <&usart3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "usart";
status = "disabled";
};
@@ -242,7 +242,7 @@
reg = <0xfffc8000 0x300>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
- clocks = <&pwm_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
clock-names = "pwm_clk";
status = "disabled";
};
@@ -255,7 +255,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -266,7 +266,7 @@
compatible = "atmel,at91sam9rl-adc";
reg = <0xfffd0000 0x100>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&adc_clk>, <&adc_op_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0x3f>;
@@ -304,7 +304,7 @@
reg = <0x00600000 0x100000>,
<0xfffd4000 0x4000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&udphs_clk>, <&utmi>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
clock-names = "pclk", "hclk";
status = "disabled";
@@ -366,7 +366,7 @@
reg = <0xffffe600 0x200>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
- clocks = <&dma0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
clock-names = "dma_clk";
};
@@ -399,7 +399,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -794,7 +794,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioA_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
@@ -805,7 +805,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff800 {
@@ -816,7 +816,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioC_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
pioD: gpio@fffffa00 {
@@ -827,7 +827,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioD_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
};
};
@@ -835,202 +835,9 @@
compatible = "atmel,at91sam9rl-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main: mainck {
- compatible = "atmel,at91rm9200-clk-main";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- plla: pllack {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <1000000 32000000>;
- #atmel,pll-clk-output-range-cells = <3>;
- atmel,pll-clk-output-ranges = <80000000 200000000 0>,
- <190000000 240000000 2>;
- };
-
- utmi: utmick {
- compatible = "atmel,at91sam9x5-clk-utmi";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_LOCKU>;
- clocks = <&main>;
- };
-
- mck: masterck {
- compatible = "atmel,at91rm9200-clk-master";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
- clocks = <&clk32k>, <&main>, <&plla>, <&utmi>;
- atmel,clk-output-range = <0 94000000>;
- atmel,clk-divisors = <1 2 4 0>;
- };
-
- prog: progck {
- compatible = "atmel,at91rm9200-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
-
- };
-
- periphck {
- compatible = "atmel,at91rm9200-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- pioA_clk: pioA_clk {
- #clock-cells = <0>;
- reg = <2>;
- };
-
- pioB_clk: pioB_clk {
- #clock-cells = <0>;
- reg = <3>;
- };
-
- pioC_clk: pioC_clk {
- #clock-cells = <0>;
- reg = <4>;
- };
-
- pioD_clk: pioD_clk {
- #clock-cells = <0>;
- reg = <5>;
- };
-
- usart0_clk: usart0_clk {
- #clock-cells = <0>;
- reg = <6>;
- };
-
- usart1_clk: usart1_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- usart2_clk: usart2_clk {
- #clock-cells = <0>;
- reg = <8>;
- };
-
- usart3_clk: usart3_clk {
- #clock-cells = <0>;
- reg = <9>;
- };
-
- mci0_clk: mci0_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- twi0_clk: twi0_clk {
- #clock-cells = <0>;
- reg = <11>;
- };
-
- twi1_clk: twi1_clk {
- #clock-cells = <0>;
- reg = <12>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <13>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <14>;
- };
-
- ssc1_clk: ssc1_clk {
- #clock-cells = <0>;
- reg = <15>;
- };
-
- tc0_clk: tc0_clk {
- #clock-cells = <0>;
- reg = <16>;
- };
-
- tc1_clk: tc1_clk {
- #clock-cells = <0>;
- reg = <17>;
- };
-
- tc2_clk: tc2_clk {
- #clock-cells = <0>;
- reg = <18>;
- };
-
- pwm_clk: pwm_clk {
- #clock-cells = <0>;
- reg = <19>;
- };
-
- adc_clk: adc_clk {
- #clock-cells = <0>;
- reg = <20>;
- };
-
- dma0_clk: dma0_clk {
- #clock-cells = <0>;
- reg = <21>;
- };
-
- udphs_clk: udphs_clk {
- #clock-cells = <0>;
- reg = <22>;
- };
-
- lcd_clk: lcd_clk {
- #clock-cells = <0>;
- reg = <23>;
- };
- };
+ #clock-cells = <2>;
+ clocks = <&clk32k>, <&main_xtal>;
+ clock-names = "slow_clk", "main_xtal";
};
rstc@fffffd00 {
@@ -1049,7 +856,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
watchdog@fffffd40 {
--
2.19.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* Re: [PATCH v2 00/22] clk: at91: Rework DT bindings
2018-10-16 14:21 [PATCH v2 00/22] clk: at91: Rework DT bindings Alexandre Belloni
` (21 preceding siblings ...)
2018-10-16 14:22 ` [PATCH v2 22/22] ARM: dts: at91: at91sam9rl: " Alexandre Belloni
@ 2018-10-17 16:50 ` Stephen Boyd
2018-10-17 17:27 ` Alexandre Belloni
22 siblings, 1 reply; 40+ messages in thread
From: Stephen Boyd @ 2018-10-17 16:50 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
Quoting Alexandre Belloni (2018-10-16 07:21:38)
> This is the promised rework of the at91 PMC clocks driver. It is mainly
> necessary to remove the DTC warnings but it also complies with the CCF
> rule that there should be one node per controller instead of one node
> per clock.
>
> This only handles the PMC, I'm planning to also rework the SCKC bindings
> later (without breaking the DT ABI).
>
> The series is based on top of v4.19-rc1.
>
> The first two patches are actually fixes and may be considered for this
> cycle.
>
> I'll take the device tree changes through the at91 tree as DT backward
> compatibility is working.
>
I get the following warnings and errors from my auto checker script:
ERROR: need consistent spacing around '+' (ctx:WxV)
#167: FILE: drivers/clk/at91/sama5d4.c:137:
+ sama5d4_pmc = pmc_data_allocate(PMC_MCK2 +1,
^
drivers/clk/at91/clk-i2s-mux.c:49:15: warning: symbol 'at91_clk_i2s_mux_register' was not declared. Should it be static?
drivers/clk/at91/clk-audio-pll.c:447:15: warning: symbol 'at91_clk_register_audio_pll_frac' was not declared. Should it be static?
drivers/clk/at91/clk-audio-pll.c:477:15: warning: symbol 'at91_clk_register_audio_pll_pad' was not declared. Should it be static?
drivers/clk/at91/clk-audio-pll.c:508:15: warning: symbol 'at91_clk_register_audio_pll_pmc' was not declared. Should it be static?
drivers/clk/at91/sama5d4.c:123 sama5d4_pmc_setup() warn: unsigned 'i' is never less than zero.
drivers/clk/at91/sama5d4.c:129 sama5d4_pmc_setup() warn: unsigned 'i' is never less than zero.
drivers/clk/at91/sama5d2.c:140 sama5d2_pmc_setup() warn: unsigned 'i' is never less than zero.
drivers/clk/at91/sama5d2.c:146 sama5d2_pmc_setup() warn: unsigned 'i' is never less than zero.
drivers/clk/at91/at91sam9x5.c:132 at91sam9x5_pmc_setup() warn: unsigned 'i' is never less than zero.
drivers/clk/at91/at91sam9x5.c:138 at91sam9x5_pmc_setup() warn: unsigned 'i' is never less than zero.
drivers/clk/at91/at91sam9rl.c:76 at91sam9rl_pmc_setup() warn: unsigned 'i' is never less than zero.
drivers/clk/at91/at91sam9rl.c:82 at91sam9rl_pmc_setup() warn: unsigned 'i' is never less than zero.
drivers/clk/at91/at91sam9260.c:341 at91sam926x_pmc_setup() warn: unsigned 'i' is never less than zero.
drivers/clk/at91/at91sam9260.c:347 at91sam926x_pmc_setup() warn: unsigned 'i' is never less than zero.
I fixed them with the below patch, that I'll squash into the right
place. Things look good!
diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c
index 49aeee6c31a6..b1af5a395423 100644
--- a/drivers/clk/at91/at91sam9260.c
+++ b/drivers/clk/at91/at91sam9260.c
@@ -334,7 +334,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
const char *slck_name;
struct regmap *regmap;
struct clk_hw *hw;
- unsigned int i;
+ int i;
bool bypass;
i = of_property_match_string(np, "clock-names", "slow_xtal");
diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c
index 5532fba5825b..5aeef68b4bdd 100644
--- a/drivers/clk/at91/at91sam9rl.c
+++ b/drivers/clk/at91/at91sam9rl.c
@@ -70,7 +70,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
const char *parent_names[6];
struct regmap *regmap;
struct clk_hw *hw;
- unsigned int i;
+ int i;
i = of_property_match_string(np, "clock-names", "slow_clk");
if (i < 0)
diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c
index 3cdf227ce159..2fe225a697df 100644
--- a/drivers/clk/at91/at91sam9x5.c
+++ b/drivers/clk/at91/at91sam9x5.c
@@ -125,7 +125,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
const char *parent_names[6];
struct regmap *regmap;
struct clk_hw *hw;
- unsigned int i;
+ int i;
bool bypass;
i = of_property_match_string(np, "clock-names", "slow_clk");
diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c
index 96e3c6405351..36d77146a3bd 100644
--- a/drivers/clk/at91/clk-audio-pll.c
+++ b/drivers/clk/at91/clk-audio-pll.c
@@ -43,6 +43,8 @@
#include <linux/regmap.h>
#include <linux/slab.h>
+#include "pmc.h"
+
#define AUDIO_PLL_DIV_FRAC BIT(22)
#define AUDIO_PLL_ND_MAX (AT91_PMC_AUDIO_PLL_ND_MASK >> \
AT91_PMC_AUDIO_PLL_ND_OFFSET)
diff --git a/drivers/clk/at91/clk-i2s-mux.c b/drivers/clk/at91/clk-i2s-mux.c
index dfdffa5409e6..fe6ce172b8b0 100644
--- a/drivers/clk/at91/clk-i2s-mux.c
+++ b/drivers/clk/at91/clk-i2s-mux.c
@@ -14,6 +14,8 @@
#include <soc/at91/atmel-sfr.h>
+#include "pmc.h"
+
struct clk_i2s_mux {
struct clk_hw hw;
struct regmap *regmap;
diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
index 07f1f1d613ff..d69ad96fe988 100644
--- a/drivers/clk/at91/sama5d2.c
+++ b/drivers/clk/at91/sama5d2.c
@@ -133,7 +133,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
const char *parent_names[6];
struct regmap *regmap, *regmap_sfr;
struct clk_hw *hw;
- unsigned int i;
+ int i;
bool bypass;
i = of_property_match_string(np, "clock-names", "slow_clk");
diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c
index 64b9f438f73b..e358be7f6c8d 100644
--- a/drivers/clk/at91/sama5d4.c
+++ b/drivers/clk/at91/sama5d4.c
@@ -116,7 +116,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
const char *parent_names[5];
struct regmap *regmap;
struct clk_hw *hw;
- unsigned int i;
+ int i;
bool bypass;
i = of_property_match_string(np, "clock-names", "slow_clk");
@@ -134,7 +134,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
if (IS_ERR(regmap))
return;
- sama5d4_pmc = pmc_data_allocate(PMC_MCK2 +1,
+ sama5d4_pmc = pmc_data_allocate(PMC_MCK2 + 1,
nck(sama5d4_systemck),
nck(sama5d4_periph32ck), 0);
if (!sama5d4_pmc)
^ permalink raw reply related [flat|nested] 40+ messages in thread
* Re: [PATCH v2 00/22] clk: at91: Rework DT bindings
2018-10-17 16:50 ` [PATCH v2 00/22] clk: at91: Rework DT bindings Stephen Boyd
@ 2018-10-17 17:27 ` Alexandre Belloni
0 siblings, 0 replies; 40+ messages in thread
From: Alexandre Belloni @ 2018-10-17 17:27 UTC (permalink / raw)
To: Stephen Boyd
Cc: Nicolas Ferre, Michael Turquette, Thomas Petazzoni, linux-clk,
devicetree, linux-arm-kernel, linux-kernel
On 17/10/2018 09:50:20-0700, Stephen Boyd wrote:
> Quoting Alexandre Belloni (2018-10-16 07:21:38)
> > This is the promised rework of the at91 PMC clocks driver. It is mainly
> > necessary to remove the DTC warnings but it also complies with the CCF
> > rule that there should be one node per controller instead of one node
> > per clock.
> >
> > This only handles the PMC, I'm planning to also rework the SCKC bindings
> > later (without breaking the DT ABI).
> >
> > The series is based on top of v4.19-rc1.
> >
> > The first two patches are actually fixes and may be considered for this
> > cycle.
> >
> > I'll take the device tree changes through the at91 tree as DT backward
> > compatibility is working.
> >
>
> I get the following warnings and errors from my auto checker script:
>
> ERROR: need consistent spacing around '+' (ctx:WxV)
> #167: FILE: drivers/clk/at91/sama5d4.c:137:
> + sama5d4_pmc = pmc_data_allocate(PMC_MCK2 +1,
> ^
>
> drivers/clk/at91/clk-i2s-mux.c:49:15: warning: symbol 'at91_clk_i2s_mux_register' was not declared. Should it be static?
> drivers/clk/at91/clk-audio-pll.c:447:15: warning: symbol 'at91_clk_register_audio_pll_frac' was not declared. Should it be static?
> drivers/clk/at91/clk-audio-pll.c:477:15: warning: symbol 'at91_clk_register_audio_pll_pad' was not declared. Should it be static?
> drivers/clk/at91/clk-audio-pll.c:508:15: warning: symbol 'at91_clk_register_audio_pll_pmc' was not declared. Should it be static?
> drivers/clk/at91/sama5d4.c:123 sama5d4_pmc_setup() warn: unsigned 'i' is never less than zero.
> drivers/clk/at91/sama5d4.c:129 sama5d4_pmc_setup() warn: unsigned 'i' is never less than zero.
> drivers/clk/at91/sama5d2.c:140 sama5d2_pmc_setup() warn: unsigned 'i' is never less than zero.
> drivers/clk/at91/sama5d2.c:146 sama5d2_pmc_setup() warn: unsigned 'i' is never less than zero.
> drivers/clk/at91/at91sam9x5.c:132 at91sam9x5_pmc_setup() warn: unsigned 'i' is never less than zero.
> drivers/clk/at91/at91sam9x5.c:138 at91sam9x5_pmc_setup() warn: unsigned 'i' is never less than zero.
> drivers/clk/at91/at91sam9rl.c:76 at91sam9rl_pmc_setup() warn: unsigned 'i' is never less than zero.
> drivers/clk/at91/at91sam9rl.c:82 at91sam9rl_pmc_setup() warn: unsigned 'i' is never less than zero.
> drivers/clk/at91/at91sam9260.c:341 at91sam926x_pmc_setup() warn: unsigned 'i' is never less than zero.
> drivers/clk/at91/at91sam9260.c:347 at91sam926x_pmc_setup() warn: unsigned 'i' is never less than zero.
>
> I fixed them with the below patch, that I'll squash into the right
> place. Things look good!
>
The patch seems good to me.
> diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c
> index 49aeee6c31a6..b1af5a395423 100644
> --- a/drivers/clk/at91/at91sam9260.c
> +++ b/drivers/clk/at91/at91sam9260.c
> @@ -334,7 +334,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
> const char *slck_name;
> struct regmap *regmap;
> struct clk_hw *hw;
> - unsigned int i;
> + int i;
> bool bypass;
>
> i = of_property_match_string(np, "clock-names", "slow_xtal");
> diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c
> index 5532fba5825b..5aeef68b4bdd 100644
> --- a/drivers/clk/at91/at91sam9rl.c
> +++ b/drivers/clk/at91/at91sam9rl.c
> @@ -70,7 +70,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
> const char *parent_names[6];
> struct regmap *regmap;
> struct clk_hw *hw;
> - unsigned int i;
> + int i;
>
> i = of_property_match_string(np, "clock-names", "slow_clk");
> if (i < 0)
> diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c
> index 3cdf227ce159..2fe225a697df 100644
> --- a/drivers/clk/at91/at91sam9x5.c
> +++ b/drivers/clk/at91/at91sam9x5.c
> @@ -125,7 +125,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
> const char *parent_names[6];
> struct regmap *regmap;
> struct clk_hw *hw;
> - unsigned int i;
> + int i;
> bool bypass;
>
> i = of_property_match_string(np, "clock-names", "slow_clk");
> diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c
> index 96e3c6405351..36d77146a3bd 100644
> --- a/drivers/clk/at91/clk-audio-pll.c
> +++ b/drivers/clk/at91/clk-audio-pll.c
> @@ -43,6 +43,8 @@
> #include <linux/regmap.h>
> #include <linux/slab.h>
>
> +#include "pmc.h"
> +
> #define AUDIO_PLL_DIV_FRAC BIT(22)
> #define AUDIO_PLL_ND_MAX (AT91_PMC_AUDIO_PLL_ND_MASK >> \
> AT91_PMC_AUDIO_PLL_ND_OFFSET)
> diff --git a/drivers/clk/at91/clk-i2s-mux.c b/drivers/clk/at91/clk-i2s-mux.c
> index dfdffa5409e6..fe6ce172b8b0 100644
> --- a/drivers/clk/at91/clk-i2s-mux.c
> +++ b/drivers/clk/at91/clk-i2s-mux.c
> @@ -14,6 +14,8 @@
>
> #include <soc/at91/atmel-sfr.h>
>
> +#include "pmc.h"
> +
> struct clk_i2s_mux {
> struct clk_hw hw;
> struct regmap *regmap;
> diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
> index 07f1f1d613ff..d69ad96fe988 100644
> --- a/drivers/clk/at91/sama5d2.c
> +++ b/drivers/clk/at91/sama5d2.c
> @@ -133,7 +133,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
> const char *parent_names[6];
> struct regmap *regmap, *regmap_sfr;
> struct clk_hw *hw;
> - unsigned int i;
> + int i;
> bool bypass;
>
> i = of_property_match_string(np, "clock-names", "slow_clk");
> diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c
> index 64b9f438f73b..e358be7f6c8d 100644
> --- a/drivers/clk/at91/sama5d4.c
> +++ b/drivers/clk/at91/sama5d4.c
> @@ -116,7 +116,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
> const char *parent_names[5];
> struct regmap *regmap;
> struct clk_hw *hw;
> - unsigned int i;
> + int i;
> bool bypass;
>
> i = of_property_match_string(np, "clock-names", "slow_clk");
> @@ -134,7 +134,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
> if (IS_ERR(regmap))
> return;
>
> - sama5d4_pmc = pmc_data_allocate(PMC_MCK2 +1,
> + sama5d4_pmc = pmc_data_allocate(PMC_MCK2 + 1,
> nck(sama5d4_systemck),
> nck(sama5d4_periph32ck), 0);
> if (!sama5d4_pmc)
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 40+ messages in thread