From: Qais Yousef <qais.yousef@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Hannes Reinecke <hare@suse.de>,
John Garry <john.garry@huawei.com>,
Ming Lei <ming.lei@redhat.com>,
tglx@linutronix.de, chenxiang66@hisilicon.com,
bigeasy@linutronix.de, linux-kernel@vger.kernel.org,
hare@suse.com, hch@lst.de, axboe@kernel.dk, bvanassche@acm.org,
peterz@infradead.org, mingo@redhat.com
Subject: Re: [PATCH RFC 1/1] genirq: Make threaded handler use irq affinity for managed interrupt
Date: Mon, 9 Dec 2019 15:49:32 +0000 [thread overview]
Message-ID: <20191209154932.dyysdktbosi3vlbx@e107158-lin.cambridge.arm.com> (raw)
In-Reply-To: <c06752c858229854b37af3b47779b126@www.loen.fr>
On 12/09/19 15:17, Marc Zyngier wrote:
> On 2019-12-09 15:09, Hannes Reinecke wrote:
>
> [slight digression]
>
> > My idea here is slightly different: can't we leverage SMT?
> > Most modern CPUs do SMT (I guess even ARM does it nowadays)
> > (Yes, I know about spectre and things. We're talking performance here
> > :-)
>
> I only know two of those: Cavium TX2 and ARM Neoverse-E1.
There's the Cortex-A65 too.
--
Qais Yousef
> ARM SMT CPUs are the absolute minority (and I can't say I'm displeased).
>
> M,
> --
> Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2019-12-09 15:49 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-06 14:35 [PATCH RFC 0/1] Threaded handler uses irq affinity for when the interrupt is managed John Garry
2019-12-06 14:35 ` [PATCH RFC 1/1] genirq: Make threaded handler use irq affinity for managed interrupt John Garry
2019-12-06 15:22 ` Marc Zyngier
2019-12-06 16:16 ` John Garry
2019-12-07 8:03 ` Ming Lei
2019-12-09 14:30 ` John Garry
2019-12-09 15:09 ` Hannes Reinecke
2019-12-09 15:17 ` Marc Zyngier
2019-12-09 15:25 ` Hannes Reinecke
2019-12-09 15:36 ` Marc Zyngier
2019-12-09 15:49 ` Qais Yousef [this message]
2019-12-09 15:55 ` Marc Zyngier
2019-12-10 1:43 ` Ming Lei
2019-12-10 9:45 ` John Garry
2019-12-10 10:06 ` Ming Lei
2019-12-10 10:28 ` Marc Zyngier
2019-12-10 10:59 ` John Garry
2019-12-10 11:36 ` Marc Zyngier
2019-12-10 12:05 ` John Garry
2019-12-10 18:32 ` Marc Zyngier
2019-12-11 9:41 ` John Garry
2019-12-13 10:07 ` John Garry
2019-12-13 10:31 ` Marc Zyngier
2019-12-13 12:08 ` John Garry
2019-12-14 10:59 ` Marc Zyngier
2019-12-11 17:09 ` John Garry
2019-12-12 22:38 ` Ming Lei
2019-12-13 11:12 ` John Garry
2019-12-13 13:18 ` Ming Lei
2019-12-13 15:43 ` John Garry
2019-12-13 17:12 ` Ming Lei
2019-12-13 17:50 ` John Garry
2019-12-14 13:56 ` Marc Zyngier
2019-12-16 10:47 ` John Garry
2019-12-16 11:40 ` Marc Zyngier
2019-12-16 14:17 ` John Garry
2019-12-16 18:00 ` Marc Zyngier
2019-12-16 18:50 ` John Garry
2019-12-20 11:30 ` John Garry
2019-12-20 14:43 ` Marc Zyngier
2019-12-20 15:38 ` John Garry
2019-12-20 16:16 ` Marc Zyngier
2019-12-20 23:31 ` Ming Lei
2019-12-23 9:07 ` Marc Zyngier
2019-12-23 10:26 ` John Garry
2019-12-23 10:47 ` Marc Zyngier
2019-12-23 11:35 ` John Garry
2019-12-24 1:59 ` Ming Lei
2019-12-24 11:20 ` Marc Zyngier
2019-12-25 0:48 ` Ming Lei
2020-01-02 10:35 ` John Garry
2020-01-03 0:46 ` Ming Lei
2020-01-03 10:41 ` John Garry
2020-01-03 11:29 ` Ming Lei
2020-01-03 11:50 ` John Garry
2020-01-04 12:03 ` Ming Lei
2020-05-30 7:46 ` [tip: irq/core] irqchip/gic-v3-its: Balance initial LPI affinity across CPUs tip-bot2 for Marc Zyngier
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