From: Ming Lei <ming.lei@redhat.com>
To: John Garry <john.garry@huawei.com>
Cc: Marc Zyngier <maz@kernel.org>,
tglx@linutronix.de, "chenxiang (M)" <chenxiang66@hisilicon.com>,
bigeasy@linutronix.de, linux-kernel@vger.kernel.org,
hare@suse.com, hch@lst.de, axboe@kernel.dk, bvanassche@acm.org,
peterz@infradead.org, mingo@redhat.com
Subject: Re: [PATCH RFC 1/1] genirq: Make threaded handler use irq affinity for managed interrupt
Date: Sat, 21 Dec 2019 07:31:38 +0800 [thread overview]
Message-ID: <20191220233138.GB12403@ming.t460p> (raw)
In-Reply-To: <a5154365-59c5-429b-559e-94ad6dffcdb0@huawei.com>
On Fri, Dec 20, 2019 at 03:38:24PM +0000, John Garry wrote:
> > > We've got some more results and it looks promising.
> > >
> > > So with your patch we get a performance boost of 3180.1K -> 3294.9K
> > > IOPS in the D06 SAS env. Then when we change the driver to use
> > > threaded interrupt handler (mainline currently uses tasklet), we get a
> > > boost again up to 3415K IOPS.
> > >
> > > Now this is essentially the same figure we had with using threaded
> > > handler + the gen irq change in spreading the handler CPU affinity. We
> > > did also test your patch + gen irq change and got a performance drop,
> > > to 3347K IOPS.
> > >
> > > So tentatively I'd say your patch may be all we need.
> >
> > OK.
> >
> > > FYI, here is how the effective affinity is looking for both SAS
> > > controllers with your patch:
> > >
> > > 74:02.0
> > > irq 81, cpu list 24-29, effective list 24 cq
> > > irq 82, cpu list 30-35, effective list 30 cq
> >
> > Cool.
> >
> > [...]
> >
> > > As for your patch itself, I'm still concerned of possible regressions
> > > if we don't apply this effective interrupt affinity spread policy to
> > > only managed interrupts.
> >
> > I'll try and revise that as I post the patch, probably at some point
> > between now and Christmas. I still think we should find a way to
> > address this for the D05 SAS driver though, maybe by managing the
> > affinity yourself in the driver. But this requires experimentation.
>
> I've already done something experimental for the driver to manage the
> affinity, and performance is generally much better:
>
> https://github.com/hisilicon/kernel-dev/commit/e15bd404ed1086fed44da34ed3bd37a8433688a7
>
> But I still think it's wise to only consider managed interrupts for now.
>
> >
> > > JFYI, about NVMe CPU lockup issue, there are 2 works on going here:
> > >
> > > https://lore.kernel.org/linux-nvme/20191209175622.1964-1-kbusch@kernel.org/T/#t
> > >
> > >
> > > https://lore.kernel.org/linux-block/20191218071942.22336-1-ming.lei@redhat.com/T/#t
> > >
> >
> > I've also managed to trigger some of them now that I have access to
> > a decent box with nvme storage.
>
> I only have 2x NVMe SSDs when this occurs - I should not be hitting this...
>
> Out of curiosity, have you tried
> > with the SMMU disabled? I'm wondering whether we hit some livelock
> > condition on unmapping buffers...
>
> No, but I can give it a try. Doing that should lower the CPU usage, though,
> so maybe masks the issue - probably not.
Lots of CPU lockup can is performance issue if there isn't obvious bug.
I am wondering if you may explain it a bit why enabling SMMU may save
CPU a it?
Thanks,
Ming
next prev parent reply other threads:[~2019-12-20 23:32 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-06 14:35 [PATCH RFC 0/1] Threaded handler uses irq affinity for when the interrupt is managed John Garry
2019-12-06 14:35 ` [PATCH RFC 1/1] genirq: Make threaded handler use irq affinity for managed interrupt John Garry
2019-12-06 15:22 ` Marc Zyngier
2019-12-06 16:16 ` John Garry
2019-12-07 8:03 ` Ming Lei
2019-12-09 14:30 ` John Garry
2019-12-09 15:09 ` Hannes Reinecke
2019-12-09 15:17 ` Marc Zyngier
2019-12-09 15:25 ` Hannes Reinecke
2019-12-09 15:36 ` Marc Zyngier
2019-12-09 15:49 ` Qais Yousef
2019-12-09 15:55 ` Marc Zyngier
2019-12-10 1:43 ` Ming Lei
2019-12-10 9:45 ` John Garry
2019-12-10 10:06 ` Ming Lei
2019-12-10 10:28 ` Marc Zyngier
2019-12-10 10:59 ` John Garry
2019-12-10 11:36 ` Marc Zyngier
2019-12-10 12:05 ` John Garry
2019-12-10 18:32 ` Marc Zyngier
2019-12-11 9:41 ` John Garry
2019-12-13 10:07 ` John Garry
2019-12-13 10:31 ` Marc Zyngier
2019-12-13 12:08 ` John Garry
2019-12-14 10:59 ` Marc Zyngier
2019-12-11 17:09 ` John Garry
2019-12-12 22:38 ` Ming Lei
2019-12-13 11:12 ` John Garry
2019-12-13 13:18 ` Ming Lei
2019-12-13 15:43 ` John Garry
2019-12-13 17:12 ` Ming Lei
2019-12-13 17:50 ` John Garry
2019-12-14 13:56 ` Marc Zyngier
2019-12-16 10:47 ` John Garry
2019-12-16 11:40 ` Marc Zyngier
2019-12-16 14:17 ` John Garry
2019-12-16 18:00 ` Marc Zyngier
2019-12-16 18:50 ` John Garry
2019-12-20 11:30 ` John Garry
2019-12-20 14:43 ` Marc Zyngier
2019-12-20 15:38 ` John Garry
2019-12-20 16:16 ` Marc Zyngier
2019-12-20 23:31 ` Ming Lei [this message]
2019-12-23 9:07 ` Marc Zyngier
2019-12-23 10:26 ` John Garry
2019-12-23 10:47 ` Marc Zyngier
2019-12-23 11:35 ` John Garry
2019-12-24 1:59 ` Ming Lei
2019-12-24 11:20 ` Marc Zyngier
2019-12-25 0:48 ` Ming Lei
2020-01-02 10:35 ` John Garry
2020-01-03 0:46 ` Ming Lei
2020-01-03 10:41 ` John Garry
2020-01-03 11:29 ` Ming Lei
2020-01-03 11:50 ` John Garry
2020-01-04 12:03 ` Ming Lei
2020-05-30 7:46 ` [tip: irq/core] irqchip/gic-v3-its: Balance initial LPI affinity across CPUs tip-bot2 for Marc Zyngier
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