* [PATCH net-next v2 0/4] DP83869 Enhancements @ 2020-05-20 12:18 Dan Murphy 2020-05-20 12:18 ` [PATCH net-next v2 1/4] net: phy: dp83869: Update port-mirroring to read straps Dan Murphy ` (3 more replies) 0 siblings, 4 replies; 27+ messages in thread From: Dan Murphy @ 2020-05-20 12:18 UTC (permalink / raw) To: andrew, f.fainelli, hkallweit1, davem Cc: netdev, linux-kernel, devicetree, Dan Murphy Hello These are improvements to the DP83869 Ethernet PHY driver. OP-mode and port mirroring may be strapped on the device but the software only retrives these settings from the device tree. Reading the straps and initializing the associated stored variables so when setting the PHY up and down the PHY's configuration values will be retained. The PHY also supports RGMII internal delays. Implement this feature as it was done in the DP83867 device. Dan Murphy (4): net: phy: dp83869: Update port-mirroring to read straps net: phy: dp83869: Set opmode from straps dt-bindings: net: Add RGMII internal delay for DP83869 net: dp83869: Add RGMII internal delay configuration .../devicetree/bindings/net/ti,dp83869.yaml | 16 +++ drivers/net/phy/dp83869.c | 120 +++++++++++++++++- include/dt-bindings/net/ti-dp83869.h | 18 +++ 3 files changed, 150 insertions(+), 4 deletions(-) -- 2.26.2 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH net-next v2 1/4] net: phy: dp83869: Update port-mirroring to read straps 2020-05-20 12:18 [PATCH net-next v2 0/4] DP83869 Enhancements Dan Murphy @ 2020-05-20 12:18 ` Dan Murphy 2020-05-20 12:18 ` [PATCH net-next v2 2/4] net: phy: dp83869: Set opmode from straps Dan Murphy ` (2 subsequent siblings) 3 siblings, 0 replies; 27+ messages in thread From: Dan Murphy @ 2020-05-20 12:18 UTC (permalink / raw) To: andrew, f.fainelli, hkallweit1, davem Cc: netdev, linux-kernel, devicetree, Dan Murphy The device tree may not have the property set for port mirroring because the hardware may have it strapped. If the property is not in the DT then check the straps and set the port mirroring bit appropriately. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Dan Murphy <dmurphy@ti.com> --- drivers/net/phy/dp83869.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index 7996a4aea8d2..073a0f7754a5 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -66,6 +66,7 @@ /* STRAP_STS1 bits */ #define DP83869_STRAP_STS1_RESERVED BIT(11) +#define DP83869_STRAP_MIRROR_ENABLED BIT(12) /* PHYCTRL bits */ #define DP83869_RX_FIFO_SHIFT 12 @@ -191,10 +192,18 @@ static int dp83869_of_init(struct phy_device *phydev) else if (of_property_read_bool(of_node, "ti,min-output-impedance")) dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN; - if (of_property_read_bool(of_node, "enet-phy-lane-swap")) + if (of_property_read_bool(of_node, "enet-phy-lane-swap")) { dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; - else - dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS; + } else { + /* If the lane swap is not in the DT then check the straps */ + ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); + if (ret < 0) + return ret; + if (ret & DP83869_STRAP_MIRROR_ENABLED) + dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; + else + dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS; + } if (of_property_read_u32(of_node, "rx-fifo-depth", &dp83869->rx_fifo_depth)) -- 2.26.2 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH net-next v2 2/4] net: phy: dp83869: Set opmode from straps 2020-05-20 12:18 [PATCH net-next v2 0/4] DP83869 Enhancements Dan Murphy 2020-05-20 12:18 ` [PATCH net-next v2 1/4] net: phy: dp83869: Update port-mirroring to read straps Dan Murphy @ 2020-05-20 12:18 ` Dan Murphy 2020-05-20 15:49 ` Florian Fainelli 2020-05-20 12:18 ` [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 Dan Murphy 2020-05-20 12:18 ` [PATCH net-next v2 4/4] net: dp83869: Add RGMII internal delay configuration Dan Murphy 3 siblings, 1 reply; 27+ messages in thread From: Dan Murphy @ 2020-05-20 12:18 UTC (permalink / raw) To: andrew, f.fainelli, hkallweit1, davem Cc: netdev, linux-kernel, devicetree, Dan Murphy If the op-mode for the device is not set in the device tree then set the strapped op-mode and store it for later configuration. Signed-off-by: Dan Murphy <dmurphy@ti.com> --- v2 - Fixed val declaration from u16 to int drivers/net/phy/dp83869.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index 073a0f7754a5..cfb22a21a2e6 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -65,6 +65,7 @@ #define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0) /* STRAP_STS1 bits */ +#define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0) #define DP83869_STRAP_STS1_RESERVED BIT(11) #define DP83869_STRAP_MIRROR_ENABLED BIT(12) @@ -161,6 +162,20 @@ static int dp83869_config_port_mirroring(struct phy_device *phydev) DP83869_CFG3_PORT_MIRROR_EN); } +static int dp83869_set_strapped_mode(struct phy_device *phydev) +{ + struct dp83869_private *dp83869 = phydev->priv; + int val; + + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); + if (val < 0) + return val; + + dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK; + + return 0; +} + #ifdef CONFIG_OF_MDIO static int dp83869_of_init(struct phy_device *phydev) { @@ -185,6 +200,10 @@ static int dp83869_of_init(struct phy_device *phydev) if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) return -EINVAL; + } else { + ret = dp83869_set_strapped_mode(phydev); + if (ret) + return ret; } if (of_property_read_bool(of_node, "ti,max-output-impedance")) @@ -218,7 +237,7 @@ static int dp83869_of_init(struct phy_device *phydev) #else static int dp83869_of_init(struct phy_device *phydev) { - return 0; + return dp83869_set_strapped_mode(phydev); } #endif /* CONFIG_OF_MDIO */ -- 2.26.2 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 2/4] net: phy: dp83869: Set opmode from straps 2020-05-20 12:18 ` [PATCH net-next v2 2/4] net: phy: dp83869: Set opmode from straps Dan Murphy @ 2020-05-20 15:49 ` Florian Fainelli 0 siblings, 0 replies; 27+ messages in thread From: Florian Fainelli @ 2020-05-20 15:49 UTC (permalink / raw) To: Dan Murphy, andrew, hkallweit1, davem; +Cc: netdev, linux-kernel, devicetree On 5/20/2020 5:18 AM, Dan Murphy wrote: > If the op-mode for the device is not set in the device tree then set > the strapped op-mode and store it for later configuration. > > Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> -- Florian ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 2020-05-20 12:18 [PATCH net-next v2 0/4] DP83869 Enhancements Dan Murphy 2020-05-20 12:18 ` [PATCH net-next v2 1/4] net: phy: dp83869: Update port-mirroring to read straps Dan Murphy 2020-05-20 12:18 ` [PATCH net-next v2 2/4] net: phy: dp83869: Set opmode from straps Dan Murphy @ 2020-05-20 12:18 ` Dan Murphy 2020-05-20 13:56 ` Andrew Lunn 2020-05-20 12:18 ` [PATCH net-next v2 4/4] net: dp83869: Add RGMII internal delay configuration Dan Murphy 3 siblings, 1 reply; 27+ messages in thread From: Dan Murphy @ 2020-05-20 12:18 UTC (permalink / raw) To: andrew, f.fainelli, hkallweit1, davem Cc: netdev, linux-kernel, devicetree, Dan Murphy Add the internal delay values into the header and update the binding with the internal delay properties. Signed-off-by: Dan Murphy <dmurphy@ti.com> --- .../devicetree/bindings/net/ti,dp83869.yaml | 16 ++++++++++++++++ include/dt-bindings/net/ti-dp83869.h | 18 ++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ti,dp83869.yaml b/Documentation/devicetree/bindings/net/ti,dp83869.yaml index 5b69ef03bbf7..344015ab9081 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83869.yaml +++ b/Documentation/devicetree/bindings/net/ti,dp83869.yaml @@ -64,6 +64,20 @@ properties: Operational mode for the PHY. If this is not set then the operational mode is set by the straps. see dt-bindings/net/ti-dp83869.h for values + ti,rx-internal-delay: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83869.h + for applicable values. Required only if interface type is + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID. + + ti,tx-internal-delay: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83869.h + for applicable values. Required only if interface type is + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID. + required: - reg @@ -80,5 +94,7 @@ examples: ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>; ti,max-output-impedance = "true"; ti,clk-output-sel = <DP83869_CLK_O_SEL_CHN_A_RCLK>; + ti,rx-internal-delay = <DP83869_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83869_RGMIIDCTL_2_75_NS>; }; }; diff --git a/include/dt-bindings/net/ti-dp83869.h b/include/dt-bindings/net/ti-dp83869.h index 218b1a64e975..77d104a40f1f 100644 --- a/include/dt-bindings/net/ti-dp83869.h +++ b/include/dt-bindings/net/ti-dp83869.h @@ -16,6 +16,24 @@ #define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 #define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 +/* RGMIIDCTL internal delay for rx and tx */ +#define DP83869_RGMIIDCTL_250_PS 0x0 +#define DP83869_RGMIIDCTL_500_PS 0x1 +#define DP83869_RGMIIDCTL_750_PS 0x2 +#define DP83869_RGMIIDCTL_1_NS 0x3 +#define DP83869_RGMIIDCTL_1_25_NS 0x4 +#define DP83869_RGMIIDCTL_1_50_NS 0x5 +#define DP83869_RGMIIDCTL_1_75_NS 0x6 +#define DP83869_RGMIIDCTL_2_00_NS 0x7 +#define DP83869_RGMIIDCTL_2_25_NS 0x8 +#define DP83869_RGMIIDCTL_2_50_NS 0x9 +#define DP83869_RGMIIDCTL_2_75_NS 0xa +#define DP83869_RGMIIDCTL_3_00_NS 0xb +#define DP83869_RGMIIDCTL_3_25_NS 0xc +#define DP83869_RGMIIDCTL_3_50_NS 0xd +#define DP83869_RGMIIDCTL_3_75_NS 0xe +#define DP83869_RGMIIDCTL_4_00_NS 0xf + /* IO_MUX_CFG - Clock output selection */ #define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 #define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1 -- 2.26.2 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 2020-05-20 12:18 ` [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 Dan Murphy @ 2020-05-20 13:56 ` Andrew Lunn 2020-05-20 15:28 ` Dan Murphy 0 siblings, 1 reply; 27+ messages in thread From: Andrew Lunn @ 2020-05-20 13:56 UTC (permalink / raw) To: Dan Murphy Cc: f.fainelli, hkallweit1, davem, netdev, linux-kernel, devicetree On Wed, May 20, 2020 at 07:18:34AM -0500, Dan Murphy wrote: > Add the internal delay values into the header and update the binding > with the internal delay properties. > > Signed-off-by: Dan Murphy <dmurphy@ti.com> > --- > .../devicetree/bindings/net/ti,dp83869.yaml | 16 ++++++++++++++++ > include/dt-bindings/net/ti-dp83869.h | 18 ++++++++++++++++++ > 2 files changed, 34 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/ti,dp83869.yaml b/Documentation/devicetree/bindings/net/ti,dp83869.yaml > index 5b69ef03bbf7..344015ab9081 100644 > --- a/Documentation/devicetree/bindings/net/ti,dp83869.yaml > +++ b/Documentation/devicetree/bindings/net/ti,dp83869.yaml > @@ -64,6 +64,20 @@ properties: > Operational mode for the PHY. If this is not set then the operational > mode is set by the straps. see dt-bindings/net/ti-dp83869.h for values > > + ti,rx-internal-delay: > + $ref: /schemas/types.yaml#definitions/uint32 > + description: | > + RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83869.h > + for applicable values. Required only if interface type is > + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID. Hi Dan Having it required with PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID is pretty unusual. Normally these properties are used to fine tune the delay, if the default of 2ns does not work. Andrew ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 2020-05-20 13:56 ` Andrew Lunn @ 2020-05-20 15:28 ` Dan Murphy 2020-05-20 15:30 ` Dan Murphy 2020-05-20 15:36 ` Andrew Lunn 0 siblings, 2 replies; 27+ messages in thread From: Dan Murphy @ 2020-05-20 15:28 UTC (permalink / raw) To: Andrew Lunn Cc: f.fainelli, hkallweit1, davem, netdev, linux-kernel, devicetree Andrew On 5/20/20 8:56 AM, Andrew Lunn wrote: > On Wed, May 20, 2020 at 07:18:34AM -0500, Dan Murphy wrote: >> Add the internal delay values into the header and update the binding >> with the internal delay properties. >> >> Signed-off-by: Dan Murphy <dmurphy@ti.com> >> --- >> .../devicetree/bindings/net/ti,dp83869.yaml | 16 ++++++++++++++++ >> include/dt-bindings/net/ti-dp83869.h | 18 ++++++++++++++++++ >> 2 files changed, 34 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/net/ti,dp83869.yaml b/Documentation/devicetree/bindings/net/ti,dp83869.yaml >> index 5b69ef03bbf7..344015ab9081 100644 >> --- a/Documentation/devicetree/bindings/net/ti,dp83869.yaml >> +++ b/Documentation/devicetree/bindings/net/ti,dp83869.yaml >> @@ -64,6 +64,20 @@ properties: >> Operational mode for the PHY. If this is not set then the operational >> mode is set by the straps. see dt-bindings/net/ti-dp83869.h for values >> >> + ti,rx-internal-delay: >> + $ref: /schemas/types.yaml#definitions/uint32 >> + description: | >> + RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83869.h >> + for applicable values. Required only if interface type is >> + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID. > Hi Dan > > Having it required with PHY_INTERFACE_MODE_RGMII_ID or > PHY_INTERFACE_MODE_RGMII_RXID is pretty unusual. Normally these > properties are used to fine tune the delay, if the default of 2ns does > not work. Also if the MAC phy-mode is configured with RGMII-ID and no internal delay values defined wouldn't that be counter intuitive? The driver will error out if the RGMII-ID is used and there was no internal delay defined for either rx or tx making either one required. The MAC node needs to indicate to use the internal delay for RGMII other wise the driver should ignore the internal delay programming as these internal delays are not applicable to SGMII or MII modes. The RGMII mode can be used if the default 2ns delay is acceptable. Thus why we are documenting in the binding when the internal delay is required as putting these under "required" is not correct. Dan > > Andrew ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 2020-05-20 15:28 ` Dan Murphy @ 2020-05-20 15:30 ` Dan Murphy 2020-05-20 15:36 ` Andrew Lunn 1 sibling, 0 replies; 27+ messages in thread From: Dan Murphy @ 2020-05-20 15:30 UTC (permalink / raw) To: Andrew Lunn Cc: f.fainelli, hkallweit1, davem, netdev, linux-kernel, devicetree Andrew On 5/20/20 10:28 AM, Dan Murphy wrote: > Andrew > > On 5/20/20 8:56 AM, Andrew Lunn wrote: >> On Wed, May 20, 2020 at 07:18:34AM -0500, Dan Murphy wrote: >>> Add the internal delay values into the header and update the binding >>> with the internal delay properties. >>> >>> Signed-off-by: Dan Murphy <dmurphy@ti.com> >>> --- >>> .../devicetree/bindings/net/ti,dp83869.yaml | 16 ++++++++++++++++ >>> include/dt-bindings/net/ti-dp83869.h | 18 >>> ++++++++++++++++++ >>> 2 files changed, 34 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/net/ti,dp83869.yaml >>> b/Documentation/devicetree/bindings/net/ti,dp83869.yaml >>> index 5b69ef03bbf7..344015ab9081 100644 >>> --- a/Documentation/devicetree/bindings/net/ti,dp83869.yaml >>> +++ b/Documentation/devicetree/bindings/net/ti,dp83869.yaml >>> @@ -64,6 +64,20 @@ properties: >>> Operational mode for the PHY. If this is not set then the >>> operational >>> mode is set by the straps. see dt-bindings/net/ti-dp83869.h >>> for values >>> + ti,rx-internal-delay: >>> + $ref: /schemas/types.yaml#definitions/uint32 >>> + description: | >>> + RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83869.h >>> + for applicable values. Required only if interface type is >>> + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID. >> Hi Dan >> >> Having it required with PHY_INTERFACE_MODE_RGMII_ID or >> PHY_INTERFACE_MODE_RGMII_RXID is pretty unusual. Normally these >> properties are used to fine tune the delay, if the default of 2ns does >> not work. > > Also if the MAC phy-mode is configured with RGMII-ID and no internal > delay values defined wouldn't that be counter intuitive? > > The driver will error out if the RGMII-ID is used and there was no > internal delay defined for either rx or tx making either one required. > > The MAC node needs to indicate to use the internal delay for RGMII > other wise the driver should ignore the internal delay programming as > these internal delays are not applicable to SGMII or MII modes. The > RGMII mode can be used if the default 2ns delay is acceptable. > > Thus why we are documenting in the binding when the internal delay is > required as putting these under "required" is not correct. > > Dan > This is also the same for the DP83867 PHY as that PHY and the 83869 have a few identical features like internal delay, WoL and downshifting. Dan >> >> Andrew ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 2020-05-20 15:28 ` Dan Murphy 2020-05-20 15:30 ` Dan Murphy @ 2020-05-20 15:36 ` Andrew Lunn 2020-05-20 15:56 ` Dan Murphy 1 sibling, 1 reply; 27+ messages in thread From: Andrew Lunn @ 2020-05-20 15:36 UTC (permalink / raw) To: Dan Murphy Cc: f.fainelli, hkallweit1, davem, netdev, linux-kernel, devicetree > > Hi Dan > > > > Having it required with PHY_INTERFACE_MODE_RGMII_ID or > > PHY_INTERFACE_MODE_RGMII_RXID is pretty unusual. Normally these > > properties are used to fine tune the delay, if the default of 2ns does > > not work. > > Also if the MAC phy-mode is configured with RGMII-ID and no internal delay > values defined wouldn't that be counter intuitive? Most PHYs don't allow the delay to be fine tuned. You just pass for example PHY_INTERFACE_MODE_RGMII_ID to the PHY driver and it enables a 2ns delay. That is what people expect, and is documented. Being able to tune the delay is an optional extra, which some PHYs support, but that is always above and beyond PHY_INTERFACE_MODE_RGMII_ID. Andrew ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 2020-05-20 15:36 ` Andrew Lunn @ 2020-05-20 15:56 ` Dan Murphy 2020-05-20 16:03 ` Florian Fainelli 2020-05-20 16:43 ` Andrew Lunn 0 siblings, 2 replies; 27+ messages in thread From: Dan Murphy @ 2020-05-20 15:56 UTC (permalink / raw) To: Andrew Lunn Cc: f.fainelli, hkallweit1, davem, netdev, linux-kernel, devicetree Andrew On 5/20/20 10:36 AM, Andrew Lunn wrote: >>> Hi Dan >>> >>> Having it required with PHY_INTERFACE_MODE_RGMII_ID or >>> PHY_INTERFACE_MODE_RGMII_RXID is pretty unusual. Normally these >>> properties are used to fine tune the delay, if the default of 2ns does >>> not work. >> Also if the MAC phy-mode is configured with RGMII-ID and no internal delay >> values defined wouldn't that be counter intuitive? > Most PHYs don't allow the delay to be fine tuned. You just pass for > example PHY_INTERFACE_MODE_RGMII_ID to the PHY driver and it enables a > 2ns delay. That is what people expect, and is documented. > Being able to tune the delay is an optional extra, which some PHYs > support, but that is always above and beyond > PHY_INTERFACE_MODE_RGMII_ID. I am interested in knowing where that is documented. I want to RTM I grepped for a few different words but came up empty Since this is a tuneable phy we need to program the ID. 2ns is the default value Maybe I can change it from Required to Configurable or Used. Dan > Andrew ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 2020-05-20 15:56 ` Dan Murphy @ 2020-05-20 16:03 ` Florian Fainelli 2020-05-20 16:43 ` Andrew Lunn 1 sibling, 0 replies; 27+ messages in thread From: Florian Fainelli @ 2020-05-20 16:03 UTC (permalink / raw) To: Dan Murphy, Andrew Lunn Cc: hkallweit1, davem, netdev, linux-kernel, devicetree On 5/20/2020 8:56 AM, Dan Murphy wrote: > Andrew > > On 5/20/20 10:36 AM, Andrew Lunn wrote: >>>> Hi Dan >>>> >>>> Having it required with PHY_INTERFACE_MODE_RGMII_ID or >>>> PHY_INTERFACE_MODE_RGMII_RXID is pretty unusual. Normally these >>>> properties are used to fine tune the delay, if the default of 2ns does >>>> not work. >>> Also if the MAC phy-mode is configured with RGMII-ID and no internal >>> delay >>> values defined wouldn't that be counter intuitive? >> Most PHYs don't allow the delay to be fine tuned. You just pass for >> example PHY_INTERFACE_MODE_RGMII_ID to the PHY driver and it enables a >> 2ns delay. That is what people expect, and is documented. > >> Being able to tune the delay is an optional extra, which some PHYs >> support, but that is always above and beyond >> PHY_INTERFACE_MODE_RGMII_ID. > > I am interested in knowing where that is documented. I want to RTM I > grepped for a few different words but came up empty > > Since this is a tuneable phy we need to program the ID. 2ns is the > default value > > Maybe I can change it from Required to Configurable or Used. I do not think this is properly documented, it is an established practice, but it should be clearly documented somewhere, I do not know whether that belongs in the PHY Device Tree binding or if this belongs to the PHY documentation. -- Florian ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 2020-05-20 15:56 ` Dan Murphy 2020-05-20 16:03 ` Florian Fainelli @ 2020-05-20 16:43 ` Andrew Lunn 2020-05-20 17:20 ` Dan Murphy 1 sibling, 1 reply; 27+ messages in thread From: Andrew Lunn @ 2020-05-20 16:43 UTC (permalink / raw) To: Dan Murphy Cc: f.fainelli, hkallweit1, davem, netdev, linux-kernel, devicetree > I am interested in knowing where that is documented. I want to RTM I > grepped for a few different words but came up empty Hi Dan It probably is not well documented, but one example would be Documentation/devicetree/bindings/net/ethernet-controller.yaml says: # RX and TX delays are added by the MAC when required - rgmii # RGMII with internal RX and TX delays provided by the PHY, # the MAC should not add the RX or TX delays in this case - rgmii-id # RGMII with internal RX delay provided by the PHY, the MAC # should not add an RX delay in this case - rgmii-rxid # RGMII with internal TX delay provided by the PHY, the MAC # should not add an TX delay in this case Andrew ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 2020-05-20 16:43 ` Andrew Lunn @ 2020-05-20 17:20 ` Dan Murphy 2020-05-20 17:45 ` Florian Fainelli 0 siblings, 1 reply; 27+ messages in thread From: Dan Murphy @ 2020-05-20 17:20 UTC (permalink / raw) To: Andrew Lunn Cc: f.fainelli, hkallweit1, davem, netdev, linux-kernel, devicetree Andrew/Florian On 5/20/20 11:43 AM, Andrew Lunn wrote: >> I am interested in knowing where that is documented. I want to RTM I >> grepped for a few different words but came up empty > Hi Dan > > It probably is not well documented, but one example would be > > Documentation/devicetree/bindings/net/ethernet-controller.yaml > > says: > > # RX and TX delays are added by the MAC when required > - rgmii > > # RGMII with internal RX and TX delays provided by the PHY, > # the MAC should not add the RX or TX delays in this case > - rgmii-id > > # RGMII with internal RX delay provided by the PHY, the MAC > # should not add an RX delay in this case > - rgmii-rxid > > # RGMII with internal TX delay provided by the PHY, the MAC > # should not add an TX delay in this case > > Andrew OKI I read that. I also looked at a couple other drivers too. I am wondering if rx-internal-delay and tx-internal-delay should become a common property like tx/rx fifo-depth And properly document how to use it or at least the expectation on use. Dan ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 2020-05-20 17:20 ` Dan Murphy @ 2020-05-20 17:45 ` Florian Fainelli 2020-05-20 17:52 ` Dan Murphy 0 siblings, 1 reply; 27+ messages in thread From: Florian Fainelli @ 2020-05-20 17:45 UTC (permalink / raw) To: Dan Murphy, Andrew Lunn Cc: hkallweit1, davem, netdev, linux-kernel, devicetree On 5/20/2020 10:20 AM, Dan Murphy wrote: > Andrew/Florian > > On 5/20/20 11:43 AM, Andrew Lunn wrote: >>> I am interested in knowing where that is documented. I want to RTM I >>> grepped for a few different words but came up empty >> Hi Dan >> >> It probably is not well documented, but one example would be >> >> Documentation/devicetree/bindings/net/ethernet-controller.yaml >> >> says: >> >> # RX and TX delays are added by the MAC when required >> - rgmii >> >> # RGMII with internal RX and TX delays provided by the PHY, >> # the MAC should not add the RX or TX delays in this case >> - rgmii-id >> >> # RGMII with internal RX delay provided by the PHY, the MAC >> # should not add an RX delay in this case >> - rgmii-rxid >> >> # RGMII with internal TX delay provided by the PHY, the MAC >> # should not add an TX delay in this case >> >> Andrew > > OKI I read that. I also looked at a couple other drivers too. > > I am wondering if rx-internal-delay and tx-internal-delay should become > a common property like tx/rx fifo-depth > > And properly document how to use it or at least the expectation on use. Yes they should, and they should have an unit associated with the name. -- Florian ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 2020-05-20 17:45 ` Florian Fainelli @ 2020-05-20 17:52 ` Dan Murphy 2020-05-20 19:27 ` Andrew Lunn 0 siblings, 1 reply; 27+ messages in thread From: Dan Murphy @ 2020-05-20 17:52 UTC (permalink / raw) To: Florian Fainelli, Andrew Lunn Cc: hkallweit1, davem, netdev, linux-kernel, devicetree Florian On 5/20/20 12:45 PM, Florian Fainelli wrote: > > On 5/20/2020 10:20 AM, Dan Murphy wrote: >> Andrew/Florian >> >> On 5/20/20 11:43 AM, Andrew Lunn wrote: >>>> I am interested in knowing where that is documented. I want to RTM I >>>> grepped for a few different words but came up empty >>> Hi Dan >>> >>> It probably is not well documented, but one example would be >>> >>> Documentation/devicetree/bindings/net/ethernet-controller.yaml >>> >>> says: >>> >>> # RX and TX delays are added by the MAC when required >>> - rgmii >>> >>> # RGMII with internal RX and TX delays provided by the PHY, >>> # the MAC should not add the RX or TX delays in this case >>> - rgmii-id >>> >>> # RGMII with internal RX delay provided by the PHY, the MAC >>> # should not add an RX delay in this case >>> - rgmii-rxid >>> >>> # RGMII with internal TX delay provided by the PHY, the MAC >>> # should not add an TX delay in this case >>> >>> Andrew >> OKI I read that. I also looked at a couple other drivers too. >> >> I am wondering if rx-internal-delay and tx-internal-delay should become >> a common property like tx/rx fifo-depth >>> And properly document how to use it or at least the expectation on use. > Yes they should, and they should have an unit associated with the name. UGH I think I just got volunteered to do make them common. Dan ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 2020-05-20 17:52 ` Dan Murphy @ 2020-05-20 19:27 ` Andrew Lunn 2020-05-20 20:02 ` Dan Murphy 0 siblings, 1 reply; 27+ messages in thread From: Andrew Lunn @ 2020-05-20 19:27 UTC (permalink / raw) To: Dan Murphy Cc: Florian Fainelli, hkallweit1, davem, netdev, linux-kernel, devicetree Hi Dan > UGH I think I just got volunteered to do make them common. There is code you can copy from PHY drivers. :-) What would be kind of nice is if the validate was in the core as well. Pass a list of possible delays in pS, and it will do a phydev_err() if what is in DT does not match one of the listed delays. Take a look around at what current drivers do and see if you can find a nice abstraction which will work for a few drivers. We cannot easily convert existing drivers without breaking DT, but a design which works in theory for what we currently have has a good chance of working for any new PHY driver. Andrew ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 2020-05-20 19:27 ` Andrew Lunn @ 2020-05-20 20:02 ` Dan Murphy 2020-05-20 20:44 ` Andrew Lunn 0 siblings, 1 reply; 27+ messages in thread From: Dan Murphy @ 2020-05-20 20:02 UTC (permalink / raw) To: Andrew Lunn Cc: Florian Fainelli, hkallweit1, davem, netdev, linux-kernel, devicetree Andrew On 5/20/20 2:27 PM, Andrew Lunn wrote: > Hi Dan > >> UGH I think I just got volunteered to do make them common. > There is code you can copy from PHY drivers. :-) > > What would be kind of nice is if the validate was in the core as > well. Pass a list of possible delays in pS, and it will do a > phydev_err() if what is in DT does not match one of the listed > delays. Take a look around at what current drivers do and see if you > can find a nice abstraction which will work for a few drivers. We > cannot easily convert existing drivers without breaking DT, but a > design which works in theory for what we currently have has a good > chance of working for any new PHY driver. I think adding it in the core would be a bit of a challenge. I think each PHY driver needs to handle parsing and validating this property on its own (like fifo-depth). It is a PHY specific setting. Take the DP83867/9 and the ADIN1200/ADIN1300. The 8386X devices has a delta granularity of 250pS and the AD devices is 200pS per each setting And the 867/9 has 3x more values (15) vs only 5 for the AD PHY. And the Atheros AR803x PHY does use rgmii-id in the yaml, which I guess is what you were pointing out, that if set the PHY uses a default 2nS delay and it is not configurable. Same with the Broadcomm. Ack to not changing already existing drivers which is only 2 the AD PHY and the DP83867 PHY. But I can update the yaml for the 83867 and mark the TI specific properties as deprecated in favor of the new properties like I did with fifo-depth. Dan > Andrew ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 2020-05-20 20:02 ` Dan Murphy @ 2020-05-20 20:44 ` Andrew Lunn 2020-05-20 20:55 ` Dan Murphy 0 siblings, 1 reply; 27+ messages in thread From: Andrew Lunn @ 2020-05-20 20:44 UTC (permalink / raw) To: Dan Murphy Cc: Florian Fainelli, hkallweit1, davem, netdev, linux-kernel, devicetree > I think adding it in the core would be a bit of a challenge. I think each > PHY driver needs to handle parsing and validating this property on its own > (like fifo-depth). It is a PHY specific setting. fifo-depth yes. But some delays follow a common pattern. e.g. Documentation/devicetree/bindings/net/micrel-ksz90x1.txt Device Tree Value Delay Pad Skew Register Value ----------------------------------------------------- 0 -840ps 0000 200 -720ps 0001 400 -600ps 0010 600 -480ps 0011 800 -360ps 0100 1000 -240ps 0101 1200 -120ps 0110 1400 0ps 0111 1600 120ps 1000 1800 240ps 1001 2000 360ps 1010 2200 480ps 1011 2400 600ps 1100 2600 720ps 1101 2800 840ps 1110 3000 960ps 1111 Documentation/devicetree/bindings/net/adi,adin.yaml adi,rx-internal-delay-ps: description: | RGMII RX Clock Delay used only when PHY operates in RGMII mode with internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. enum: [ 1600, 1800, 2000, 2200, 2400 ] default: 2000 adi,tx-internal-delay-ps: description: | RGMII TX Clock Delay used only when PHY operates in RGMII mode with internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds. enum: [ 1600, 1800, 2000, 2200, 2400 ] default: 2000 Documentation/devicetree/bindings/net/apm-xgene-enet.txt - tx-delay: Delay value for RGMII bridge TX clock. Valid values are between 0 to 7, that maps to 417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps Default value is 4, which corresponds to 1611 ps - rx-delay: Delay value for RGMII bridge RX clock. Valid values are between 0 to 7, that maps to 273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps Default value is 2, which corresponds to 899 ps You could implement checking against a table of valid values, which is something you need for your PHY. You could even consider making it a 2D table, and return the register value, not the delay? Andrew ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 2020-05-20 20:44 ` Andrew Lunn @ 2020-05-20 20:55 ` Dan Murphy 0 siblings, 0 replies; 27+ messages in thread From: Dan Murphy @ 2020-05-20 20:55 UTC (permalink / raw) To: Andrew Lunn Cc: Florian Fainelli, hkallweit1, davem, netdev, linux-kernel, devicetree Andrew On 5/20/20 3:44 PM, Andrew Lunn wrote: >> I think adding it in the core would be a bit of a challenge. I think each >> PHY driver needs to handle parsing and validating this property on its own >> (like fifo-depth). It is a PHY specific setting. > fifo-depth yes. But some delays follow a common pattern. > > e.g. > Documentation/devicetree/bindings/net/micrel-ksz90x1.txt > > Device Tree Value Delay Pad Skew Register Value > ----------------------------------------------------- > 0 -840ps 0000 > 200 -720ps 0001 > 400 -600ps 0010 > 600 -480ps 0011 > 800 -360ps 0100 > 1000 -240ps 0101 > 1200 -120ps 0110 > 1400 0ps 0111 > 1600 120ps 1000 > 1800 240ps 1001 > 2000 360ps 1010 > 2200 480ps 1011 > 2400 600ps 1100 > 2600 720ps 1101 > 2800 840ps 1110 > 3000 960ps 1111 > > Documentation/devicetree/bindings/net/adi,adin.yaml > > adi,rx-internal-delay-ps: > description: | > RGMII RX Clock Delay used only when PHY operates in RGMII mode with > internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. > enum: [ 1600, 1800, 2000, 2200, 2400 ] > default: 2000 > > adi,tx-internal-delay-ps: > description: | > RGMII TX Clock Delay used only when PHY operates in RGMII mode with > internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds. > enum: [ 1600, 1800, 2000, 2200, 2400 ] > default: 2000 > > Documentation/devicetree/bindings/net/apm-xgene-enet.txt > > - tx-delay: Delay value for RGMII bridge TX clock. > Valid values are between 0 to 7, that maps to > 417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps > Default value is 4, which corresponds to 1611 ps > - rx-delay: Delay value for RGMII bridge RX clock. > Valid values are between 0 to 7, that maps to > 273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps > Default value is 2, which corresponds to 899 ps > > You could implement checking against a table of valid values, which is > something you need for your PHY. You could even consider making it a > 2D table, and return the register value, not the delay? So provide a helper function that will just basically parse an array and return the indexed value. The outlier here is the AD device since the index to value is not 1-1 mapping. Not sure we need a 2D table like the AD driver. I actually implemented this in the dp83869 a bit ago and have done this in a few other non-PHY drivers. I guess I can look at making it a utility function in the networking space. Dan > > Andrew ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH net-next v2 4/4] net: dp83869: Add RGMII internal delay configuration 2020-05-20 12:18 [PATCH net-next v2 0/4] DP83869 Enhancements Dan Murphy ` (2 preceding siblings ...) 2020-05-20 12:18 ` [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 Dan Murphy @ 2020-05-20 12:18 ` Dan Murphy 3 siblings, 0 replies; 27+ messages in thread From: Dan Murphy @ 2020-05-20 12:18 UTC (permalink / raw) To: andrew, f.fainelli, hkallweit1, davem Cc: netdev, linux-kernel, devicetree, Dan Murphy Add RGMII internal delay configuration for Rx and Tx. Signed-off-by: Dan Murphy <dmurphy@ti.com> --- drivers/net/phy/dp83869.c | 84 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index cfb22a21a2e6..f08008050177 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -99,6 +99,14 @@ #define DP83869_OP_MODE_MII BIT(5) #define DP83869_SGMII_RGMII_BRIDGE BIT(6) +/* RGMIIDCTL bits */ +#define DP83869_RGMII_TX_CLK_DELAY_MAX 0xf +#define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4 +#define DP83869_RGMII_TX_CLK_DELAY_INV (DP83869_RGMII_TX_CLK_DELAY_MAX + 1) +#define DP83869_RGMII_RX_CLK_DELAY_MAX 0xf +#define DP83869_RGMII_RX_CLK_DELAY_SHIFT 0 +#define DP83869_RGMII_RX_CLK_DELAY_INV (DP83869_RGMII_RX_CLK_DELAY_MAX + 1) + enum { DP83869_PORT_MIRRORING_KEEP, DP83869_PORT_MIRRORING_EN, @@ -108,6 +116,8 @@ enum { struct dp83869_private { int tx_fifo_depth; int rx_fifo_depth; + u32 rx_id_delay; + u32 tx_id_delay; int io_impedance; int port_mirroring; bool rxctrl_strap_quirk; @@ -232,6 +242,26 @@ static int dp83869_of_init(struct phy_device *phydev) &dp83869->tx_fifo_depth)) dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; + dp83869->rx_id_delay = DP83869_RGMII_RX_CLK_DELAY_INV; + ret = of_property_read_u32(of_node, "ti,rx-internal-delay", + &dp83869->rx_id_delay); + if (!ret && dp83869->rx_id_delay > DP83869_RGMII_RX_CLK_DELAY_MAX) { + phydev_err(phydev, + "ti,rx-internal-delay value of %u out of range\n", + dp83869->rx_id_delay); + return -EINVAL; + } + + dp83869->tx_id_delay = DP83869_RGMII_TX_CLK_DELAY_INV; + ret = of_property_read_u32(of_node, "ti,tx-internal-delay", + &dp83869->tx_id_delay); + if (!ret && dp83869->tx_id_delay > DP83869_RGMII_TX_CLK_DELAY_MAX) { + phydev_err(phydev, + "ti,tx-internal-delay value of %u out of range\n", + dp83869->tx_id_delay); + return -EINVAL; + } + return ret; } #else @@ -270,6 +300,29 @@ static int dp83869_configure_rgmii(struct phy_device *phydev, return ret; } +static int dp83869_verify_rgmii_cfg(struct phy_device *phydev) +{ + struct dp83869_private *dp83869 = phydev->priv; + + /* RX delay *must* be specified if internal delay of RX is used. */ + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && + dp83869->rx_id_delay == DP83869_RGMII_RX_CLK_DELAY_INV) { + phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); + return -EINVAL; + } + + /* TX delay *must* be specified if internal delay of TX is used. */ + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && + dp83869->tx_id_delay == DP83869_RGMII_TX_CLK_DELAY_INV) { + phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); + return -EINVAL; + } + + return 0; +} + static int dp83869_configure_mode(struct phy_device *phydev, struct dp83869_private *dp83869) { @@ -371,6 +424,11 @@ static int dp83869_config_init(struct phy_device *phydev) { struct dp83869_private *dp83869 = phydev->priv; int ret, val; + u16 delay; + + ret = dp83869_verify_rgmii_cfg(phydev); + if (ret) + return ret; ret = dp83869_configure_mode(phydev, dp83869); if (ret) @@ -394,6 +452,32 @@ static int dp83869_config_init(struct phy_device *phydev) dp83869->clk_output_sel << DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); + if (phy_interface_is_rgmii(phydev)) { + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); + + val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | DP83869_RGMII_RX_CLK_DELAY_EN); + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + val |= (DP83869_RGMII_TX_CLK_DELAY_EN | DP83869_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + val |= DP83869_RGMII_TX_CLK_DELAY_EN; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + val |= DP83869_RGMII_RX_CLK_DELAY_EN; + + phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, val); + + delay = 0; + if (dp83869->rx_id_delay != DP83869_RGMII_RX_CLK_DELAY_INV) + delay |= dp83869->rx_id_delay; + if (dp83869->tx_id_delay != DP83869_RGMII_TX_CLK_DELAY_INV) + delay |= dp83869->tx_id_delay << + DP83869_RGMII_TX_CLK_DELAY_SHIFT; + + phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL, + delay); + } + return ret; } -- 2.26.2 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH net-next v2 0/4] RGMII Internal delay common property @ 2020-05-22 12:25 Dan Murphy 2020-05-22 12:25 ` [PATCH net-next v2 4/4] net: dp83869: Add RGMII internal delay configuration Dan Murphy 0 siblings, 1 reply; 27+ messages in thread From: Dan Murphy @ 2020-05-22 12:25 UTC (permalink / raw) To: andrew, f.fainelli, hkallweit1, davem, robh Cc: netdev, linux-kernel, devicetree, Dan Murphy Hello The RGMII internal delay is a common setting found in most RGMII capable PHY devices. It was found that many vendor specific device tree properties exist to do the same function. This creates a common property to be used for PHY's that have tunable internal delays for the Rx and Tx paths. Dan Murphy (4): dt-bindings: net: Add tx and rx internal delays net: phy: Add a helper to return the index for of the internal delay dt-bindings: net: Add RGMII internal delay for DP83869 net: dp83869: Add RGMII internal delay configuration .../bindings/net/ethernet-controller.yaml | 14 +++ .../devicetree/bindings/net/ti,dp83869.yaml | 16 +++ drivers/net/phy/dp83869.c | 101 ++++++++++++++++++ drivers/net/phy/phy_device.c | 45 ++++++++ include/linux/phy.h | 2 + 5 files changed, 178 insertions(+) -- 2.26.2 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH net-next v2 4/4] net: dp83869: Add RGMII internal delay configuration 2020-05-22 12:25 [PATCH net-next v2 0/4] RGMII Internal delay common property Dan Murphy @ 2020-05-22 12:25 ` Dan Murphy 2020-05-22 16:13 ` Florian Fainelli 0 siblings, 1 reply; 27+ messages in thread From: Dan Murphy @ 2020-05-22 12:25 UTC (permalink / raw) To: andrew, f.fainelli, hkallweit1, davem, robh Cc: netdev, linux-kernel, devicetree, Dan Murphy Add RGMII internal delay configuration for Rx and Tx. Signed-off-by: Dan Murphy <dmurphy@ti.com> --- drivers/net/phy/dp83869.c | 101 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index cfb22a21a2e6..a9008d32e2b6 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -99,6 +99,14 @@ #define DP83869_OP_MODE_MII BIT(5) #define DP83869_SGMII_RGMII_BRIDGE BIT(6) +/* RGMIIDCTL bits */ +#define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4 +#define DP83869_RGMII_CLK_DELAY_INV 0 + +static int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, 1750, + 2000, 2250, 2500, 2750, 3000, 3250, + 3500, 3750, 4000}; + enum { DP83869_PORT_MIRRORING_KEEP, DP83869_PORT_MIRRORING_EN, @@ -108,6 +116,8 @@ enum { struct dp83869_private { int tx_fifo_depth; int rx_fifo_depth; + u32 rx_id_delay; + u32 tx_id_delay; int io_impedance; int port_mirroring; bool rxctrl_strap_quirk; @@ -182,6 +192,7 @@ static int dp83869_of_init(struct phy_device *phydev) struct dp83869_private *dp83869 = phydev->priv; struct device *dev = &phydev->mdio.dev; struct device_node *of_node = dev->of_node; + int delay_size = ARRAY_SIZE(dp83869_internal_delay); int ret; if (!of_node) @@ -232,6 +243,26 @@ static int dp83869_of_init(struct phy_device *phydev) &dp83869->tx_fifo_depth)) dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; + dp83869->rx_id_delay = DP83869_RGMII_CLK_DELAY_INV; + ret = of_property_read_u32(of_node, "rx-internal-delay-ps", + &dp83869->rx_id_delay); + if (!ret && dp83869->rx_id_delay > dp83869_internal_delay[delay_size]) { + phydev_err(phydev, + "rx-internal-delay value of %u out of range\n", + dp83869->rx_id_delay); + return -EINVAL; + } + + dp83869->tx_id_delay = DP83869_RGMII_CLK_DELAY_INV; + ret = of_property_read_u32(of_node, "tx-internal-delay-ps", + &dp83869->tx_id_delay); + if (!ret && dp83869->tx_id_delay > dp83869_internal_delay[delay_size]) { + phydev_err(phydev, + "tx-internal-delay value of %u out of range\n", + dp83869->tx_id_delay); + return -EINVAL; + } + return ret; } #else @@ -270,6 +301,29 @@ static int dp83869_configure_rgmii(struct phy_device *phydev, return ret; } +static int dp83869_verify_rgmii_cfg(struct phy_device *phydev) +{ + struct dp83869_private *dp83869 = phydev->priv; + + /* RX delay *must* be specified if internal delay of RX is used. */ + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && + dp83869->rx_id_delay == DP83869_RGMII_CLK_DELAY_INV) { + phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); + return -EINVAL; + } + + /* TX delay *must* be specified if internal delay of TX is used. */ + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && + dp83869->tx_id_delay == DP83869_RGMII_CLK_DELAY_INV) { + phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); + return -EINVAL; + } + + return 0; +} + static int dp83869_configure_mode(struct phy_device *phydev, struct dp83869_private *dp83869) { @@ -371,6 +425,12 @@ static int dp83869_config_init(struct phy_device *phydev) { struct dp83869_private *dp83869 = phydev->priv; int ret, val; + int delay_size = ARRAY_SIZE(dp83869_internal_delay); + int delay = 0; + + ret = dp83869_verify_rgmii_cfg(phydev); + if (ret) + return ret; ret = dp83869_configure_mode(phydev, dp83869); if (ret) @@ -394,6 +454,47 @@ static int dp83869_config_init(struct phy_device *phydev) dp83869->clk_output_sel << DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); + if (phy_interface_is_rgmii(phydev)) { + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); + + val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | DP83869_RGMII_RX_CLK_DELAY_EN); + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + val |= (DP83869_RGMII_TX_CLK_DELAY_EN | DP83869_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + val |= DP83869_RGMII_TX_CLK_DELAY_EN; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + val |= DP83869_RGMII_RX_CLK_DELAY_EN; + + phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, val); + + if (dp83869->rx_id_delay) { + val = phy_get_delay_index(phydev, + &dp83869_internal_delay[0], + delay_size, + dp83869->rx_id_delay); + if (val < 0) + return val; + + delay |= val; + } + + if (dp83869->tx_id_delay) { + val = phy_get_delay_index(phydev, + &dp83869_internal_delay[0], + delay_size, + dp83869->tx_id_delay); + if (val < 0) + return val; + + delay |= val << DP83869_RGMII_TX_CLK_DELAY_SHIFT; + } + + phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL, + delay); + } + return ret; } -- 2.26.2 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 4/4] net: dp83869: Add RGMII internal delay configuration 2020-05-22 12:25 ` [PATCH net-next v2 4/4] net: dp83869: Add RGMII internal delay configuration Dan Murphy @ 2020-05-22 16:13 ` Florian Fainelli 2020-05-22 18:50 ` Dan Murphy 0 siblings, 1 reply; 27+ messages in thread From: Florian Fainelli @ 2020-05-22 16:13 UTC (permalink / raw) To: Dan Murphy, andrew, hkallweit1, davem, robh Cc: netdev, linux-kernel, devicetree On 5/22/2020 5:25 AM, Dan Murphy wrote: > Add RGMII internal delay configuration for Rx and Tx. > > Signed-off-by: Dan Murphy <dmurphy@ti.com> > --- > drivers/net/phy/dp83869.c | 101 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 101 insertions(+) > > diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c > index cfb22a21a2e6..a9008d32e2b6 100644 > --- a/drivers/net/phy/dp83869.c > +++ b/drivers/net/phy/dp83869.c > @@ -99,6 +99,14 @@ > #define DP83869_OP_MODE_MII BIT(5) > #define DP83869_SGMII_RGMII_BRIDGE BIT(6) > > +/* RGMIIDCTL bits */ > +#define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4 > +#define DP83869_RGMII_CLK_DELAY_INV 0 > + > +static int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, 1750, > + 2000, 2250, 2500, 2750, 3000, 3250, > + 3500, 3750, 4000}; > + > enum { > DP83869_PORT_MIRRORING_KEEP, > DP83869_PORT_MIRRORING_EN, > @@ -108,6 +116,8 @@ enum { > struct dp83869_private { > int tx_fifo_depth; > int rx_fifo_depth; > + u32 rx_id_delay; > + u32 tx_id_delay; > int io_impedance; > int port_mirroring; > bool rxctrl_strap_quirk; > @@ -182,6 +192,7 @@ static int dp83869_of_init(struct phy_device *phydev) > struct dp83869_private *dp83869 = phydev->priv; > struct device *dev = &phydev->mdio.dev; > struct device_node *of_node = dev->of_node; > + int delay_size = ARRAY_SIZE(dp83869_internal_delay); > int ret; > > if (!of_node) > @@ -232,6 +243,26 @@ static int dp83869_of_init(struct phy_device *phydev) > &dp83869->tx_fifo_depth)) > dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; > > + dp83869->rx_id_delay = DP83869_RGMII_CLK_DELAY_INV; > + ret = of_property_read_u32(of_node, "rx-internal-delay-ps", > + &dp83869->rx_id_delay); > + if (!ret && dp83869->rx_id_delay > dp83869_internal_delay[delay_size]) { > + phydev_err(phydev, > + "rx-internal-delay value of %u out of range\n", > + dp83869->rx_id_delay); > + return -EINVAL; > + } > + > + dp83869->tx_id_delay = DP83869_RGMII_CLK_DELAY_INV; > + ret = of_property_read_u32(of_node, "tx-internal-delay-ps", > + &dp83869->tx_id_delay); > + if (!ret && dp83869->tx_id_delay > dp83869_internal_delay[delay_size]) { > + phydev_err(phydev, > + "tx-internal-delay value of %u out of range\n", > + dp83869->tx_id_delay); > + return -EINVAL; > + } This is the kind of validation that I would be expecting from the PHY library to do, in fact, since you use Device Tree standard property, I would expect you only need to pass the maximum delay value and some storage for your array of delays. > + > return ret; > } > #else > @@ -270,6 +301,29 @@ static int dp83869_configure_rgmii(struct phy_device *phydev, > return ret; > } > > +static int dp83869_verify_rgmii_cfg(struct phy_device *phydev) > +{ > + struct dp83869_private *dp83869 = phydev->priv; > + > + /* RX delay *must* be specified if internal delay of RX is used. */ > + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || > + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && > + dp83869->rx_id_delay == DP83869_RGMII_CLK_DELAY_INV) { > + phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); > + return -EINVAL; > + } > + > + /* TX delay *must* be specified if internal delay of TX is used. */ > + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || > + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && > + dp83869->tx_id_delay == DP83869_RGMII_CLK_DELAY_INV) { > + phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); > + return -EINVAL; > + } > + > + return 0; > +} > + > static int dp83869_configure_mode(struct phy_device *phydev, > struct dp83869_private *dp83869) > { > @@ -371,6 +425,12 @@ static int dp83869_config_init(struct phy_device *phydev) > { > struct dp83869_private *dp83869 = phydev->priv; > int ret, val; > + int delay_size = ARRAY_SIZE(dp83869_internal_delay); > + int delay = 0; > + > + ret = dp83869_verify_rgmii_cfg(phydev); > + if (ret) > + return ret; > > ret = dp83869_configure_mode(phydev, dp83869); > if (ret) > @@ -394,6 +454,47 @@ static int dp83869_config_init(struct phy_device *phydev) > dp83869->clk_output_sel << > DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); > > + if (phy_interface_is_rgmii(phydev)) { > + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); > + > + val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | DP83869_RGMII_RX_CLK_DELAY_EN); > + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) > + val |= (DP83869_RGMII_TX_CLK_DELAY_EN | DP83869_RGMII_RX_CLK_DELAY_EN); > + > + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) > + val |= DP83869_RGMII_TX_CLK_DELAY_EN; > + > + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) > + val |= DP83869_RGMII_RX_CLK_DELAY_EN; > + > + phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, val); > + > + if (dp83869->rx_id_delay) { > + val = phy_get_delay_index(phydev, > + &dp83869_internal_delay[0], > + delay_size, > + dp83869->rx_id_delay); > + if (val < 0) > + return val; > + > + delay |= val; Don't you need to do a bitwise AND with the maximum delay value supported by the range since you do a Read/Modify/Write operation here? > + } > + > + if (dp83869->tx_id_delay) { > + val = phy_get_delay_index(phydev, > + &dp83869_internal_delay[0], > + delay_size, > + dp83869->tx_id_delay); > + if (val < 0) > + return val; > + > + delay |= val << DP83869_RGMII_TX_CLK_DELAY_SHIFT; Likewise. > + } > + > + phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL, > + delay); > + } > + > return ret; > } > > -- Florian ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 4/4] net: dp83869: Add RGMII internal delay configuration 2020-05-22 16:13 ` Florian Fainelli @ 2020-05-22 18:50 ` Dan Murphy 2020-05-23 15:09 ` Andrew Lunn 0 siblings, 1 reply; 27+ messages in thread From: Dan Murphy @ 2020-05-22 18:50 UTC (permalink / raw) To: Florian Fainelli, andrew, hkallweit1, davem, robh Cc: netdev, linux-kernel, devicetree Florian On 5/22/20 11:13 AM, Florian Fainelli wrote: > > On 5/22/2020 5:25 AM, Dan Murphy wrote: >> Add RGMII internal delay configuration for Rx and Tx. >> >> Signed-off-by: Dan Murphy <dmurphy@ti.com> >> --- >> drivers/net/phy/dp83869.c | 101 ++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 101 insertions(+) >> >> diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c >> index cfb22a21a2e6..a9008d32e2b6 100644 >> --- a/drivers/net/phy/dp83869.c >> +++ b/drivers/net/phy/dp83869.c >> @@ -99,6 +99,14 @@ >> #define DP83869_OP_MODE_MII BIT(5) >> #define DP83869_SGMII_RGMII_BRIDGE BIT(6) >> >> +/* RGMIIDCTL bits */ >> +#define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4 >> +#define DP83869_RGMII_CLK_DELAY_INV 0 >> + >> +static int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, 1750, >> + 2000, 2250, 2500, 2750, 3000, 3250, >> + 3500, 3750, 4000}; >> + >> enum { >> DP83869_PORT_MIRRORING_KEEP, >> DP83869_PORT_MIRRORING_EN, >> @@ -108,6 +116,8 @@ enum { >> struct dp83869_private { >> int tx_fifo_depth; >> int rx_fifo_depth; >> + u32 rx_id_delay; >> + u32 tx_id_delay; >> int io_impedance; >> int port_mirroring; >> bool rxctrl_strap_quirk; >> @@ -182,6 +192,7 @@ static int dp83869_of_init(struct phy_device *phydev) >> struct dp83869_private *dp83869 = phydev->priv; >> struct device *dev = &phydev->mdio.dev; >> struct device_node *of_node = dev->of_node; >> + int delay_size = ARRAY_SIZE(dp83869_internal_delay); >> int ret; >> >> if (!of_node) >> @@ -232,6 +243,26 @@ static int dp83869_of_init(struct phy_device *phydev) >> &dp83869->tx_fifo_depth)) >> dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; >> >> + dp83869->rx_id_delay = DP83869_RGMII_CLK_DELAY_INV; >> + ret = of_property_read_u32(of_node, "rx-internal-delay-ps", >> + &dp83869->rx_id_delay); >> + if (!ret && dp83869->rx_id_delay > dp83869_internal_delay[delay_size]) { >> + phydev_err(phydev, >> + "rx-internal-delay value of %u out of range\n", >> + dp83869->rx_id_delay); >> + return -EINVAL; >> + } >> + >> + dp83869->tx_id_delay = DP83869_RGMII_CLK_DELAY_INV; >> + ret = of_property_read_u32(of_node, "tx-internal-delay-ps", >> + &dp83869->tx_id_delay); >> + if (!ret && dp83869->tx_id_delay > dp83869_internal_delay[delay_size]) { >> + phydev_err(phydev, >> + "tx-internal-delay value of %u out of range\n", >> + dp83869->tx_id_delay); >> + return -EINVAL; >> + } > This is the kind of validation that I would be expecting from the PHY > library to do, in fact, since you use Device Tree standard property, I > would expect you only need to pass the maximum delay value and some > storage for your array of delays. Actually the PHY library will return either the 0th index if the value is to small or the max index if the value is to large based on the array passed in so maybe this check is unnecessary. >> + >> return ret; >> } >> #else >> @@ -270,6 +301,29 @@ static int dp83869_configure_rgmii(struct phy_device *phydev, >> return ret; >> } >> >> +static int dp83869_verify_rgmii_cfg(struct phy_device *phydev) >> +{ >> + struct dp83869_private *dp83869 = phydev->priv; >> + >> + /* RX delay *must* be specified if internal delay of RX is used. */ >> + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || >> + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && >> + dp83869->rx_id_delay == DP83869_RGMII_CLK_DELAY_INV) { >> + phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); >> + return -EINVAL; >> + } >> + >> + /* TX delay *must* be specified if internal delay of TX is used. */ >> + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || >> + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && >> + dp83869->tx_id_delay == DP83869_RGMII_CLK_DELAY_INV) { >> + phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); >> + return -EINVAL; >> + } >> + >> + return 0; >> +} >> + >> static int dp83869_configure_mode(struct phy_device *phydev, >> struct dp83869_private *dp83869) >> { >> @@ -371,6 +425,12 @@ static int dp83869_config_init(struct phy_device *phydev) >> { >> struct dp83869_private *dp83869 = phydev->priv; >> int ret, val; >> + int delay_size = ARRAY_SIZE(dp83869_internal_delay); >> + int delay = 0; >> + >> + ret = dp83869_verify_rgmii_cfg(phydev); >> + if (ret) >> + return ret; >> >> ret = dp83869_configure_mode(phydev, dp83869); >> if (ret) >> @@ -394,6 +454,47 @@ static int dp83869_config_init(struct phy_device *phydev) >> dp83869->clk_output_sel << >> DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); >> >> + if (phy_interface_is_rgmii(phydev)) { >> + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); >> + >> + val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | DP83869_RGMII_RX_CLK_DELAY_EN); >> + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) >> + val |= (DP83869_RGMII_TX_CLK_DELAY_EN | DP83869_RGMII_RX_CLK_DELAY_EN); >> + >> + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) >> + val |= DP83869_RGMII_TX_CLK_DELAY_EN; >> + >> + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) >> + val |= DP83869_RGMII_RX_CLK_DELAY_EN; >> + >> + phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, val); >> + >> + if (dp83869->rx_id_delay) { >> + val = phy_get_delay_index(phydev, >> + &dp83869_internal_delay[0], >> + delay_size, >> + dp83869->rx_id_delay); >> + if (val < 0) >> + return val; >> + >> + delay |= val; > Don't you need to do a bitwise AND with the maximum delay value > supported by the range since you do a Read/Modify/Write operation here? There is not RMW here. This is a write to the RGMIIDCTL register. > >> + } >> + >> + if (dp83869->tx_id_delay) { >> + val = phy_get_delay_index(phydev, >> + &dp83869_internal_delay[0], >> + delay_size, >> + dp83869->tx_id_delay); >> + if (val < 0) >> + return val; >> + >> + delay |= val << DP83869_RGMII_TX_CLK_DELAY_SHIFT; > Likewise. Same as above Dan ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 4/4] net: dp83869: Add RGMII internal delay configuration 2020-05-22 18:50 ` Dan Murphy @ 2020-05-23 15:09 ` Andrew Lunn 2020-05-23 21:40 ` Dan Murphy 0 siblings, 1 reply; 27+ messages in thread From: Andrew Lunn @ 2020-05-23 15:09 UTC (permalink / raw) To: Dan Murphy Cc: Florian Fainelli, hkallweit1, davem, robh, netdev, linux-kernel, devicetree > > > + dp83869->tx_id_delay = DP83869_RGMII_CLK_DELAY_INV; > > > + ret = of_property_read_u32(of_node, "tx-internal-delay-ps", > > > + &dp83869->tx_id_delay); > > > + if (!ret && dp83869->tx_id_delay > dp83869_internal_delay[delay_size]) { > > > + phydev_err(phydev, > > > + "tx-internal-delay value of %u out of range\n", > > > + dp83869->tx_id_delay); > > > + return -EINVAL; > > > + } > > This is the kind of validation that I would be expecting from the PHY > > library to do, in fact, since you use Device Tree standard property, I > > would expect you only need to pass the maximum delay value and some > > storage for your array of delays. > > Actually the PHY library will return either the 0th index if the value is to > small or the max index if the value is to large > > based on the array passed in so maybe this check is unnecessary. Hi Dan I'm not sure the helper is implementing the best behaviour. Rounded to the nearest when within the supported range is O.K. But if the request is outside the range, i would report an error. Any why is your PHY special, in that is does care about out of range delays, when others using new the new core helper don't? Andrew ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 4/4] net: dp83869: Add RGMII internal delay configuration 2020-05-23 15:09 ` Andrew Lunn @ 2020-05-23 21:40 ` Dan Murphy 2020-05-23 22:07 ` Andrew Lunn 0 siblings, 1 reply; 27+ messages in thread From: Dan Murphy @ 2020-05-23 21:40 UTC (permalink / raw) To: Andrew Lunn Cc: Florian Fainelli, hkallweit1, davem, robh, netdev, linux-kernel, devicetree Andrew On 5/23/20 10:09 AM, Andrew Lunn wrote: >>>> + dp83869->tx_id_delay = DP83869_RGMII_CLK_DELAY_INV; >>>> + ret = of_property_read_u32(of_node, "tx-internal-delay-ps", >>>> + &dp83869->tx_id_delay); >>>> + if (!ret && dp83869->tx_id_delay > dp83869_internal_delay[delay_size]) { >>>> + phydev_err(phydev, >>>> + "tx-internal-delay value of %u out of range\n", >>>> + dp83869->tx_id_delay); >>>> + return -EINVAL; >>>> + } >>> This is the kind of validation that I would be expecting from the PHY >>> library to do, in fact, since you use Device Tree standard property, I >>> would expect you only need to pass the maximum delay value and some >>> storage for your array of delays. >> Actually the PHY library will return either the 0th index if the value is to >> small or the max index if the value is to large >> >> based on the array passed in so maybe this check is unnecessary. > Hi Dan > > I'm not sure the helper is implementing the best behaviour. Rounded to > the nearest when within the supported range is O.K. But if the request > is outside the range, i would report an error. Hope this email does not bounce. > Any why is your PHY special, in that is does care about out of range > delays, when others using new the new core helper don't? We are not rounding to nearest here. Basically the helper works to find the best match If the delay passed in is less than or equal to the smallest delay then return the smallest delay index If the delay passed in is greater then the largest delay then return the max delay index Not sure what you mean about this PHY being special. This helper is not PHY specific. After I think about this more I am thinking a helper may be over kill here and the delay to setting should be done within the PHY driver itself Dan > Andrew ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 4/4] net: dp83869: Add RGMII internal delay configuration 2020-05-23 21:40 ` Dan Murphy @ 2020-05-23 22:07 ` Andrew Lunn 2020-05-26 17:48 ` Dan Murphy 0 siblings, 1 reply; 27+ messages in thread From: Andrew Lunn @ 2020-05-23 22:07 UTC (permalink / raw) To: Dan Murphy Cc: Florian Fainelli, hkallweit1, davem, robh, netdev, linux-kernel, devicetree > > Any why is your PHY special, in that is does care about out of range > > delays, when others using new the new core helper don't? > > We are not rounding to nearest here. Basically the helper works to find the > best match > > If the delay passed in is less than or equal to the smallest delay then > return the smallest delay index > > If the delay passed in is greater then the largest delay then return the max > delay index + /* Find an approximate index by looking up the table */ + if (delay > delay_values[i - 1] && + delay < delay_values[i]) { + if (delay - delay_values[i - 1] < delay_values[i] - delay) + return i - 1; + else + return i; This appears to round to the nearest value when it is not an exact match. The documentation is a hint to the DT developer what value to put in DT. By saying it rounders, the developer does not need to go digging through the source code to find an exact value, otherwise -EINVAL will be returned. They can just use the value the HW engineer suggested, and the PHY will pick whatever is nearest. > Not sure what you mean about this PHY being special. This helper is > not PHY specific. As you said, if out of range, the helper returns the top/bottom value. Your PHY is special, the top/bottom value is not good enough, you throw an error. The point of helpers is to give uniform behaviour. We have one line helpers, simply because they give uniform behaviour, rather than have each driver do it subtlety different. But it also means drivers should try to not add additional constraints over what the helper already has, unless it is actually required by the hardware. > After I think about this more I am thinking a helper may be over kill here > and the delay to setting should be done within the PHY driver itself The helper is useful, it will result in uniform handling of rounding between DT values and what the PHY can actually do. But please also move your range check and error message inside the helper. Andrew ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH net-next v2 4/4] net: dp83869: Add RGMII internal delay configuration 2020-05-23 22:07 ` Andrew Lunn @ 2020-05-26 17:48 ` Dan Murphy 0 siblings, 0 replies; 27+ messages in thread From: Dan Murphy @ 2020-05-26 17:48 UTC (permalink / raw) To: Andrew Lunn Cc: Florian Fainelli, hkallweit1, davem, robh, netdev, linux-kernel, devicetree Andrew On 5/23/20 5:07 PM, Andrew Lunn wrote: >>> Any why is your PHY special, in that is does care about out of range >>> delays, when others using new the new core helper don't? >> We are not rounding to nearest here. Basically the helper works to find the >> best match >> >> If the delay passed in is less than or equal to the smallest delay then >> return the smallest delay index >> >> If the delay passed in is greater then the largest delay then return the max >> delay index > + /* Find an approximate index by looking up the table */ > + if (delay > delay_values[i - 1] && > + delay < delay_values[i]) { > + if (delay - delay_values[i - 1] < delay_values[i] - delay) > + return i - 1; > + else > + return i; > > This appears to round to the nearest value when it is not an exact > match. > > The documentation is a hint to the DT developer what value to put in > DT. By saying it rounders, the developer does not need to go digging > through the source code to find an exact value, otherwise -EINVAL will > be returned. They can just use the value the HW engineer suggested, > and the PHY will pick whatever is nearest. > >> Not sure what you mean about this PHY being special. This helper is >> not PHY specific. > As you said, if out of range, the helper returns the top/bottom > value. Your PHY is special, the top/bottom value is not good enough, > you throw an error. > > The point of helpers is to give uniform behaviour. We have one line > helpers, simply because they give uniform behaviour, rather than have > each driver do it subtlety different. But it also means drivers should > try to not add additional constraints over what the helper already > has, unless it is actually required by the hardware. > >> After I think about this more I am thinking a helper may be over kill here >> and the delay to setting should be done within the PHY driver itself > The helper is useful, it will result in uniform handling of rounding > between DT values and what the PHY can actually do. But please also > move your range check and error message inside the helper. I re-worked v3 to be a bit more of a helper and incorporated Florian's and you comments Dan > Andrew ^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2020-05-26 17:48 UTC | newest] Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-05-20 12:18 [PATCH net-next v2 0/4] DP83869 Enhancements Dan Murphy 2020-05-20 12:18 ` [PATCH net-next v2 1/4] net: phy: dp83869: Update port-mirroring to read straps Dan Murphy 2020-05-20 12:18 ` [PATCH net-next v2 2/4] net: phy: dp83869: Set opmode from straps Dan Murphy 2020-05-20 15:49 ` Florian Fainelli 2020-05-20 12:18 ` [PATCH net-next v2 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 Dan Murphy 2020-05-20 13:56 ` Andrew Lunn 2020-05-20 15:28 ` Dan Murphy 2020-05-20 15:30 ` Dan Murphy 2020-05-20 15:36 ` Andrew Lunn 2020-05-20 15:56 ` Dan Murphy 2020-05-20 16:03 ` Florian Fainelli 2020-05-20 16:43 ` Andrew Lunn 2020-05-20 17:20 ` Dan Murphy 2020-05-20 17:45 ` Florian Fainelli 2020-05-20 17:52 ` Dan Murphy 2020-05-20 19:27 ` Andrew Lunn 2020-05-20 20:02 ` Dan Murphy 2020-05-20 20:44 ` Andrew Lunn 2020-05-20 20:55 ` Dan Murphy 2020-05-20 12:18 ` [PATCH net-next v2 4/4] net: dp83869: Add RGMII internal delay configuration Dan Murphy 2020-05-22 12:25 [PATCH net-next v2 0/4] RGMII Internal delay common property Dan Murphy 2020-05-22 12:25 ` [PATCH net-next v2 4/4] net: dp83869: Add RGMII internal delay configuration Dan Murphy 2020-05-22 16:13 ` Florian Fainelli 2020-05-22 18:50 ` Dan Murphy 2020-05-23 15:09 ` Andrew Lunn 2020-05-23 21:40 ` Dan Murphy 2020-05-23 22:07 ` Andrew Lunn 2020-05-26 17:48 ` Dan Murphy
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