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From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Ulf Hansson <ulf.hansson@linaro.org>,
	Viresh Kumar <vireshk@kernel.org>,
	Stephen Boyd <sboyd@kernel.org>,
	Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-pm@vger.kernel.org
Subject: [PATCH v7 19/37] pwm: tegra: Add runtime PM and OPP support
Date: Fri,  2 Jul 2021 02:27:10 +0300	[thread overview]
Message-ID: <20210701232728.23591-20-digetx@gmail.com> (raw)
In-Reply-To: <20210701232728.23591-1-digetx@gmail.com>

The PWM on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now PWM must be resumed using
runtime PM API in order to initialize the PWM power state. The PWM clock
rate must be changed using OPP API that will reconfigure the power domain
performance state in accordance to the rate. Add runtime PM and OPP
support to the PWM driver.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/pwm/pwm-tegra.c | 104 ++++++++++++++++++++++++++++++++--------
 1 file changed, 85 insertions(+), 19 deletions(-)

diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 11a10b575ace..ea124d40f272 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -42,12 +42,16 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/pm_opp.h>
 #include <linux/pwm.h>
 #include <linux/platform_device.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/pm_runtime.h>
 #include <linux/slab.h>
 #include <linux/reset.h>
 
+#include <soc/tegra/common.h>
+
 #define PWM_ENABLE	(1 << 31)
 #define PWM_DUTY_WIDTH	8
 #define PWM_DUTY_SHIFT	16
@@ -145,12 +149,25 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 		required_clk_rate =
 			(NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;
 
-		err = clk_set_rate(pc->clk, required_clk_rate);
-		if (err < 0)
+		/*
+		 * GENPD performance state should be changed only for
+		 * the resumed device because GENPD core tracks performance
+		 * state and drops/restores the state on RPM suspend/resume.
+		 */
+		err = pm_runtime_resume_and_get(pc->dev);
+		if (err)
+			return err;
+
+		err = dev_pm_opp_set_rate(pc->dev, required_clk_rate);
+		if (err < 0) {
+			pm_runtime_put(pc->dev);
 			return -EINVAL;
+		}
 
 		/* Store the new rate for further references */
 		pc->clk_rate = clk_get_rate(pc->clk);
+
+		pm_runtime_put(pc->dev);
 	}
 
 	rate = pc->clk_rate >> PWM_DUTY_WIDTH;
@@ -181,8 +198,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	 * before writing the register. Otherwise, keep it enabled.
 	 */
 	if (!pwm_is_enabled(pwm)) {
-		err = clk_prepare_enable(pc->clk);
-		if (err < 0)
+		err = pm_runtime_resume_and_get(pc->dev);
+		if (err)
 			return err;
 	} else
 		val |= PWM_ENABLE;
@@ -193,7 +210,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	 * If the PWM is not enabled, turn the clock off again to save power.
 	 */
 	if (!pwm_is_enabled(pwm))
-		clk_disable_unprepare(pc->clk);
+		pm_runtime_put(pc->dev);
 
 	return 0;
 }
@@ -204,8 +221,8 @@ static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 	int rc = 0;
 	u32 val;
 
-	rc = clk_prepare_enable(pc->clk);
-	if (rc < 0)
+	rc = pm_runtime_resume_and_get(pc->dev);
+	if (rc)
 		return rc;
 
 	val = pwm_readl(pc, pwm->hwpwm);
@@ -224,7 +241,7 @@ static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 	val &= ~PWM_ENABLE;
 	pwm_writel(pc, pwm->hwpwm, val);
 
-	clk_disable_unprepare(pc->clk);
+	pm_runtime_put(pc->dev);
 }
 
 static const struct pwm_ops tegra_pwm_ops = {
@@ -256,11 +273,21 @@ static int tegra_pwm_probe(struct platform_device *pdev)
 	if (IS_ERR(pwm->clk))
 		return PTR_ERR(pwm->clk);
 
+	ret = devm_tegra_core_dev_init_opp_table_simple(&pdev->dev);
+	if (ret)
+		return ret;
+
+	pm_runtime_enable(&pdev->dev);
+
+	ret = pm_runtime_resume_and_get(&pdev->dev);
+	if (ret)
+		goto disable_pm;
+
 	/* Set maximum frequency of the IP */
-	ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency);
+	ret = dev_pm_opp_set_rate(pwm->dev, pwm->soc->max_frequency);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
-		return ret;
+		goto put_pm;
 	}
 
 	/*
@@ -278,7 +305,7 @@ static int tegra_pwm_probe(struct platform_device *pdev)
 	if (IS_ERR(pwm->rst)) {
 		ret = PTR_ERR(pwm->rst);
 		dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
-		return ret;
+		goto put_pm;
 	}
 
 	reset_control_deassert(pwm->rst);
@@ -291,34 +318,70 @@ static int tegra_pwm_probe(struct platform_device *pdev)
 	if (ret < 0) {
 		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 		reset_control_assert(pwm->rst);
-		return ret;
+		goto put_pm;
 	}
 
+	pm_runtime_put(&pdev->dev);
+
 	return 0;
+put_pm:
+	pm_runtime_put(&pdev->dev);
+disable_pm:
+	pm_runtime_disable(&pdev->dev);
+	return ret;
 }
 
 static int tegra_pwm_remove(struct platform_device *pdev)
 {
 	struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
+	int err;
 
 	pwmchip_remove(&pc->chip);
 
+	err = pm_runtime_resume_and_get(pc->dev);
+	if (err)
+		return err;
+
 	reset_control_assert(pc->rst);
+	pm_runtime_put(pc->dev);
+	pm_runtime_disable(pc->dev);
 
 	return 0;
 }
 
-#ifdef CONFIG_PM_SLEEP
-static int tegra_pwm_suspend(struct device *dev)
+static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev)
 {
-	return pinctrl_pm_select_sleep_state(dev);
+	struct tegra_pwm_chip *pc = dev_get_drvdata(dev);
+	int err;
+
+	clk_disable_unprepare(pc->clk);
+
+	err = pinctrl_pm_select_sleep_state(dev);
+	if (err) {
+		clk_prepare_enable(pc->clk);
+		return err;
+	}
+
+	return 0;
 }
 
-static int tegra_pwm_resume(struct device *dev)
+static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)
 {
-	return pinctrl_pm_select_default_state(dev);
+	struct tegra_pwm_chip *pc = dev_get_drvdata(dev);
+	int err;
+
+	err = pinctrl_pm_select_default_state(dev);
+	if (err)
+		return err;
+
+	err = clk_prepare_enable(pc->clk);
+	if (err) {
+		pinctrl_pm_select_sleep_state(dev);
+		return err;
+	}
+
+	return 0;
 }
-#endif
 
 static const struct tegra_pwm_soc tegra20_pwm_soc = {
 	.num_channels = 4,
@@ -344,7 +407,10 @@ static const struct of_device_id tegra_pwm_of_match[] = {
 MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
 
 static const struct dev_pm_ops tegra_pwm_pm_ops = {
-	SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume)
+	SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume,
+			   NULL)
+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+				pm_runtime_force_resume)
 };
 
 static struct platform_driver tegra_pwm_driver = {
-- 
2.30.2


  parent reply	other threads:[~2021-07-01 23:29 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-01 23:26 [PATCH v7 00/37] NVIDIA Tegra power management patches for 5.15 Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 01/37] soc/tegra: pmc: Temporarily disable PMC state syncing Dmitry Osipenko
2021-08-12 16:02   ` Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 02/37] soc/tegra: pmc: Implement attach_dev() of power domain drivers Dmitry Osipenko
2021-08-02 14:48   ` Ulf Hansson
2021-08-02 18:23     ` Dmitry Osipenko
2021-08-04  9:59       ` Ulf Hansson
2021-08-04 21:16         ` Dmitry Osipenko
2021-08-09 14:15           ` Ulf Hansson
2021-08-09 23:56             ` Dmitry Osipenko
2021-08-10 10:51               ` Ulf Hansson
2021-08-11 19:30                 ` Dmitry Osipenko
2021-08-11 22:41                   ` Dmitry Osipenko
2021-08-12  1:40                     ` Dmitry Osipenko
2021-08-12 11:17                       ` Ulf Hansson
2021-08-12 16:24                         ` Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 03/37] soc/tegra: Don't print error message when OPPs not available Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 04/37] soc/tegra: Add devm_tegra_core_dev_init_opp_table_simple() Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 05/37] dt-bindings: clock: tegra-car: Document new tegra-clocks node Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 06/37] clk: tegra: Support runtime PM and power domain Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 07/37] dt-bindings: host1x: Document OPP and power domain properties Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 08/37] dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 09/37] gpu: host1x: Add host1x_channel_stop() Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 10/37] gpu: host1x: Add runtime PM support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 11/37] gpu: host1x: Add stub driver for MPE, VI, EPP and ISP Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 12/37] drm/tegra: dc: Support OPP and SoC core voltage scaling Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 13/37] drm/tegra: hdmi: Add OPP support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 14/37] drm/tegra: gr2d: Support OPP and power management Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 15/37] drm/tegra: gr3d: " Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 16/37] drm/tegra: vic: Stop channel before suspending Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 17/37] usb: chipidea: tegra: Add runtime PM support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 18/37] bus: tegra-gmi: " Dmitry Osipenko
2021-07-01 23:27 ` Dmitry Osipenko [this message]
2021-07-01 23:27 ` [PATCH v7 20/37] mmc: sdhci-tegra: Add runtime PM and OPP support Dmitry Osipenko
2021-07-02  3:39   ` kernel test robot
2021-07-01 23:27 ` [PATCH v7 21/37] mtd: rawnand: tegra: Add runtime PM support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 22/37] soc/tegra: fuse: Clear fuse->clk on driver probe failure Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 23/37] soc/tegra: fuse: Add runtime PM support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 24/37] soc/tegra: fuse: Enable fuse clock on suspend Dmitry Osipenko
2021-07-21 16:00   ` Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 25/37] clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 26/37] spi: tegra20-slink: Improve runtime PM usage Dmitry Osipenko
2021-07-02  8:29   ` kernel test robot
2021-07-01 23:27 ` [PATCH v7 27/37] spi: tegra20-slink: Add OPP support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 28/37] memory: tegra20-emc: Add minimal runtime PM support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 29/37] memory: tegra30-emc: " Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 30/37] media: dt: bindings: tegra-vde: Convert to schema Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 31/37] media: dt: bindings: tegra-vde: Document OPP and power domain Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 32/37] media: staging: tegra-vde: Support generic " Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 33/37] ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 34/37] ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 35/37] ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 36/37] ARM: tegra: Add Memory Client resets to Tegra30 " Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 37/37] soc/tegra: pmc: Enable core domain support on Tegra20 and Tegra30 Dmitry Osipenko
2021-07-09 13:01 ` [PATCH v7 00/37] NVIDIA Tegra power management patches for 5.15 Ulf Hansson
2021-07-09 21:23   ` Dmitry Osipenko

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