From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Viresh Kumar <vireshk@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-pm@vger.kernel.org
Subject: [PATCH v7 34/37] ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees
Date: Fri, 2 Jul 2021 02:27:25 +0300 [thread overview]
Message-ID: <20210701232728.23591-35-digetx@gmail.com> (raw)
In-Reply-To: <20210701232728.23591-1-digetx@gmail.com>
Add OPP tables and power domains to all peripheral devices which
support power management on Tegra30 SoC.
Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
.../tegra30-asus-nexus7-grouper-common.dtsi | 1 +
arch/arm/boot/dts/tegra30-beaver.dts | 1 +
arch/arm/boot/dts/tegra30-cardhu.dtsi | 1 +
arch/arm/boot/dts/tegra30-colibri.dtsi | 17 +-
arch/arm/boot/dts/tegra30-ouya.dts | 1 +
.../arm/boot/dts/tegra30-peripherals-opp.dtsi | 1412 +++++++++++++++++
arch/arm/boot/dts/tegra30.dtsi | 156 ++
7 files changed, 1586 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
index ae8300baa2d4..cd62e44fd571 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
@@ -953,6 +953,7 @@ pmc@7000e400 {
nvidia,core-pwr-off-time = <0>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
+ core-supply = <&vdd_core>;
};
ahub@70080000 {
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index e159feeedef7..b54cbb24c4d3 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1915,6 +1915,7 @@ pmc@7000e400 {
nvidia,core-pwr-off-time = <0>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
+ core-supply = <&core_vdd_reg>;
};
ahub@70080000 {
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index d9dd11569d4b..ff49bf17b119 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -391,6 +391,7 @@ pmc@7000e400 {
nvidia,core-pwr-off-time = <0>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
+ core-supply = <&vdd_core>;
};
ahub@70080000 {
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index 413e35215804..0627b64f044d 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -765,9 +765,14 @@ vdd1_reg: vdd1 {
vddctrl_reg: vddctrl {
regulator-name = "+V1.0_VDD_CPU";
- regulator-min-microvolt = <1150000>;
- regulator-max-microvolt = <1150000>;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-coupled-with = <&vdd_core>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
regulator-always-on;
+
+ nvidia,tegra-cpu-regulator;
};
reg_1v8_vio: vio {
@@ -890,18 +895,23 @@ temp-sensor@4c {
};
/* SW: +V1.2_VDD_CORE */
- regulator@60 {
+ vdd_core: regulator@60 {
compatible = "ti,tps62362";
reg = <0x60>;
regulator-name = "tps62362-vout";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1400000>;
+ regulator-coupled-with = <&vddctrl_reg>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
regulator-boot-on;
regulator-always-on;
ti,vsel0-state-low;
/* VSEL1: EN_CORE_DVFS_N low for DVFS */
ti,vsel1-state-low;
+
+ nvidia,tegra-core-regulator;
};
};
@@ -914,6 +924,7 @@ pmc@7000e400 {
nvidia,core-pwr-off-time = <0>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
+ core-supply = <&vdd_core>;
/* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
i2c-thermtrip {
diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts
index ab8744f3d72d..2494a933f2b4 100644
--- a/arch/arm/boot/dts/tegra30-ouya.dts
+++ b/arch/arm/boot/dts/tegra30-ouya.dts
@@ -275,6 +275,7 @@ pmc@7000e400 {
nvidia,core-pwr-off-time = <458>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
+ core-supply = <&vdd_core>;
};
mc_timings: memory-controller@7000f000 {
diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
index 2c9780319725..788dcac2079e 100644
--- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
+++ b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
@@ -1,6 +1,56 @@
// SPDX-License-Identifier: GPL-2.0
/ {
+ core_opp_table: core-power-domain-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ core_opp_950: opp@950000 {
+ opp-microvolt = <950000 950000 1350000>;
+ opp-level = <950000>;
+ };
+
+ core_opp_1000: opp@1000000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-level = <1000000>;
+ };
+
+ core_opp_1050: opp@1050000 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-level = <1050000>;
+ };
+
+ core_opp_1100: opp@1100000 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-level = <1100000>;
+ };
+
+ core_opp_1150: opp@1150000 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-level = <1150000>;
+ };
+
+ core_opp_1200: opp@1200000 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-level = <1200000>;
+ };
+
+ core_opp_1250: opp@1250000 {
+ opp-microvolt = <1250000 1250000 1350000>;
+ opp-level = <1250000>;
+ };
+
+ core_opp_1300: opp@1300000 {
+ opp-microvolt = <1300000 1300000 1350000>;
+ opp-level = <1300000>;
+ };
+
+ core_opp_1350: opp@1350000 {
+ opp-microvolt = <1350000 1350000 1350000>;
+ opp-level = <1350000>;
+ };
+ };
+
emc_icc_dvfs_opp_table: emc-dvfs-opp-table {
compatible = "operating-points-v2";
@@ -8,126 +58,147 @@ opp@12750000,950 {
opp-microvolt = <950000 950000 1350000>;
opp-hz = /bits/ 64 <12750000>;
opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_950>;
};
opp@12750000,1000 {
opp-microvolt = <1000000 1000000 1350000>;
opp-hz = /bits/ 64 <12750000>;
opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1000>;
};
opp@12750000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <12750000>;
opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
};
opp@25500000,950 {
opp-microvolt = <950000 950000 1350000>;
opp-hz = /bits/ 64 <25500000>;
opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_950>;
};
opp@25500000,1000 {
opp-microvolt = <1000000 1000000 1350000>;
opp-hz = /bits/ 64 <25500000>;
opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1000>;
};
opp@25500000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <25500000>;
opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
};
opp@27000000,950 {
opp-microvolt = <950000 950000 1350000>;
opp-hz = /bits/ 64 <27000000>;
opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_950>;
};
opp@27000000,1000 {
opp-microvolt = <1000000 1000000 1350000>;
opp-hz = /bits/ 64 <27000000>;
opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1000>;
};
opp@27000000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <27000000>;
opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
};
opp@51000000,950 {
opp-microvolt = <950000 950000 1350000>;
opp-hz = /bits/ 64 <51000000>;
opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_950>;
};
opp@51000000,1000 {
opp-microvolt = <1000000 1000000 1350000>;
opp-hz = /bits/ 64 <51000000>;
opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1000>;
};
opp@51000000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <51000000>;
opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
};
opp@54000000,950 {
opp-microvolt = <950000 950000 1350000>;
opp-hz = /bits/ 64 <54000000>;
opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_950>;
};
opp@54000000,1000 {
opp-microvolt = <1000000 1000000 1350000>;
opp-hz = /bits/ 64 <54000000>;
opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1000>;
};
opp@54000000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <54000000>;
opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
};
opp@102000000,950 {
opp-microvolt = <950000 950000 1350000>;
opp-hz = /bits/ 64 <102000000>;
opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_950>;
};
opp@102000000,1000 {
opp-microvolt = <1000000 1000000 1350000>;
opp-hz = /bits/ 64 <102000000>;
opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1000>;
};
opp@102000000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <102000000>;
opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
};
opp@108000000,1000 {
opp-microvolt = <1000000 1000000 1350000>;
opp-hz = /bits/ 64 <108000000>;
opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1000>;
};
opp@108000000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <108000000>;
opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
};
opp@204000000,1000 {
opp-microvolt = <1000000 1000000 1350000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1000>;
opp-suspend;
};
@@ -135,6 +206,7 @@ opp@204000000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
opp-suspend;
};
@@ -142,126 +214,147 @@ opp@333500000,1000 {
opp-microvolt = <1000000 1000000 1350000>;
opp-hz = /bits/ 64 <333500000>;
opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1000>;
};
opp@333500000,1200 {
opp-microvolt = <1200000 1200000 1350000>;
opp-hz = /bits/ 64 <333500000>;
opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1200>;
};
opp@333500000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <333500000>;
opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
};
opp@375000000,1000 {
opp-microvolt = <1000000 1000000 1350000>;
opp-hz = /bits/ 64 <375000000>;
opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1000>;
};
opp@375000000,1200 {
opp-microvolt = <1200000 1200000 1350000>;
opp-hz = /bits/ 64 <375000000>;
opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1200>;
};
opp@375000000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <375000000>;
opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
};
opp@400000000,1000 {
opp-microvolt = <1000000 1000000 1350000>;
opp-hz = /bits/ 64 <400000000>;
opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1000>;
};
opp@400000000,1200 {
opp-microvolt = <1200000 1200000 1350000>;
opp-hz = /bits/ 64 <400000000>;
opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1200>;
};
opp@400000000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <400000000>;
opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
};
opp@416000000,1200 {
opp-microvolt = <1200000 1200000 1350000>;
opp-hz = /bits/ 64 <416000000>;
opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1200>;
};
opp@416000000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <416000000>;
opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
};
opp@450000000,1200 {
opp-microvolt = <1200000 1200000 1350000>;
opp-hz = /bits/ 64 <450000000>;
opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1200>;
};
opp@450000000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <450000000>;
opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
};
opp@533000000,1200 {
opp-microvolt = <1200000 1200000 1350000>;
opp-hz = /bits/ 64 <533000000>;
opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1200>;
};
opp@533000000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <533000000>;
opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
};
opp@625000000,1200 {
opp-microvolt = <1200000 1200000 1350000>;
opp-hz = /bits/ 64 <625000000>;
opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1200>;
};
opp@625000000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <625000000>;
opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
};
opp@667000000,1200 {
opp-microvolt = <1200000 1200000 1350000>;
opp-hz = /bits/ 64 <667000000>;
opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1200>;
};
opp@750000000,1300 {
opp-microvolt = <1300000 1300000 1350000>;
opp-hz = /bits/ 64 <750000000>;
opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1300>;
};
opp@800000000,1300 {
opp-microvolt = <1300000 1300000 1350000>;
opp-hz = /bits/ 64 <800000000>;
opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1300>;
};
opp@900000000,1350 {
opp-microvolt = <1350000 1350000 1350000>;
opp-hz = /bits/ 64 <900000000>;
opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1350>;
};
};
@@ -383,4 +476,1323 @@ opp@900000000 {
opp-peak-kBps = <7200000>;
};
};
+
+ gr2d_dvfs_opp_table: gr2d-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@267000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <267000000>;
+ opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@285000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <285000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@304000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <304000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@332000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <332000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@361000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <361000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@380000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <380000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1150>;
+ };
+
+ opp@408000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <408000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1150>;
+ };
+
+ opp@416000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <416000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@446000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <446000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@484000000,1250 {
+ opp-microvolt = <1250000 1250000 1350000>;
+ opp-hz = /bits/ 64 <484000000>;
+ opp-supported-hw = <0x000C>;
+ required-opps = <&core_opp_1250>;
+ };
+
+ opp@520000000,1300 {
+ opp-microvolt = <1300000 1300000 1350000>;
+ opp-hz = /bits/ 64 <520000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1300>;
+ };
+
+ opp@600000000,1350 {
+ opp-microvolt = <1350000 1350000 1350000>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1350>;
+ };
+ };
+
+ gr3d_dvfs_opp_table: gr3d-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@234000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <234000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1000>, <&core_opp_1000>;
+ };
+
+ opp@247000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <247000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1000>, <&core_opp_1000>;
+ };
+
+ opp@285000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <285000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1050>, <&core_opp_1050>;
+ };
+
+ opp@304000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <304000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1050>, <&core_opp_1050>;
+ };
+
+ opp@332000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <332000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1100>, <&core_opp_1100>;
+ };
+
+ opp@361000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <361000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1100>, <&core_opp_1100>;
+ };
+
+ opp@380000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <380000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1150>, <&core_opp_1150>;
+ };
+
+ opp@408000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <408000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1150>, <&core_opp_1150>;
+ };
+
+ opp@416000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <416000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1200>, <&core_opp_1200>;
+ };
+
+ opp@446000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <446000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1200>, <&core_opp_1200>;
+ };
+
+ opp@484000000,1250 {
+ opp-microvolt = <1250000 1250000 1350000>;
+ opp-hz = /bits/ 64 <484000000>;
+ opp-supported-hw = <0x000C>;
+ required-opps = <&core_opp_1250>, <&core_opp_1250>;
+ };
+
+ opp@520000000,1300 {
+ opp-microvolt = <1300000 1300000 1350000>;
+ opp-hz = /bits/ 64 <520000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1300>, <&core_opp_1300>;
+ };
+
+ opp@600000000,1350 {
+ opp-microvolt = <1350000 1350000 1350000>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1350>, <&core_opp_1350>;
+ };
+ };
+
+ afi_dvfs_opp_table: afi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@250000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <250000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ cve_dvfs_opp_table: cve-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@297000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <297000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1050>;
+ };
+ };
+
+ disp1_dvfs_opp_table: disp1-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@120000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <120000000>;
+ opp-supported-hw = <0x0009>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@155000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <155000000>;
+ opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@190000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <190000000>;
+ opp-supported-hw = <0x0009>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@268000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <268000000>;
+ opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1050>;
+ };
+ };
+
+ disp2_dvfs_opp_table: disp2-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@120000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <120000000>;
+ opp-supported-hw = <0x0009>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@155000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <155000000>;
+ opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@190000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <190000000>;
+ opp-supported-hw = <0x0009>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@268000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <268000000>;
+ opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1050>;
+ };
+ };
+
+ dsia_dvfs_opp_table: dsia-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@275000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <275000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ dsib_dvfs_opp_table: dsib-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@275000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <275000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ epp_dvfs_opp_table: epp-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@267000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <267000000>;
+ opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@285000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <285000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@304000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <304000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@332000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <332000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@361000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <361000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@380000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <380000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1150>;
+ };
+
+ opp@408000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <408000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1150>;
+ };
+
+ opp@416000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <416000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@446000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <446000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@484000000,1250 {
+ opp-microvolt = <1250000 1250000 1350000>;
+ opp-hz = /bits/ 64 <484000000>;
+ opp-supported-hw = <0x000C>;
+ required-opps = <&core_opp_1250>;
+ };
+
+ opp@520000000,1300 {
+ opp-microvolt = <1300000 1300000 1350000>;
+ opp-hz = /bits/ 64 <520000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1300>;
+ };
+
+ opp@600000000,1350 {
+ opp-microvolt = <1350000 1350000 1350000>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1350>;
+ };
+ };
+
+ fuse_burn_dvfs_opp_table: fuse_burn-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@26000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <26000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1150>;
+ };
+ };
+
+ hdmi_dvfs_opp_table: hdmi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@148500000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <148500000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ host1x_dvfs_opp_table: host1x-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@152000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <152000000>;
+ opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@188000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <188000000>;
+ opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@222000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <222000000>;
+ opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@242000000,1250 {
+ opp-microvolt = <1250000 1250000 1350000>;
+ opp-hz = /bits/ 64 <242000000>;
+ opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
+ };
+
+ opp@254000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <254000000>;
+ opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1150>;
+ };
+
+ opp@267000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <267000000>;
+ opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@300000000,1350 {
+ opp-microvolt = <1350000 1350000 1350000>;
+ opp-hz = /bits/ 64 <300000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1350>;
+ };
+ };
+
+ mipi_dvfs_opp_table: mipi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@60000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <60000000>;
+ opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1200>;
+ };
+ };
+
+ mpe_dvfs_opp_table: mpe-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@234000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <234000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@247000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <247000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@285000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <285000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@304000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <304000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@332000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <332000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@361000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <361000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@380000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <380000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1150>;
+ };
+
+ opp@408000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <408000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1150>;
+ };
+
+ opp@416000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <416000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@446000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <446000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@484000000,1250 {
+ opp-microvolt = <1250000 1250000 1350000>;
+ opp-hz = /bits/ 64 <484000000>;
+ opp-supported-hw = <0x000C>;
+ required-opps = <&core_opp_1250>;
+ };
+
+ opp@520000000,1300 {
+ opp-microvolt = <1300000 1300000 1350000>;
+ opp-hz = /bits/ 64 <520000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1300>;
+ };
+
+ opp@600000000,1350 {
+ opp-microvolt = <1350000 1350000 1350000>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1350>;
+ };
+ };
+
+ sclk_dvfs_opp_table: sclk-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@51000000,950 {
+ opp-microvolt = <950000 950000 1350000>;
+ opp-hz = /bits/ 64 <51000000>;
+ opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp@136000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <136000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@164000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <164000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@191000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <191000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@205000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <205000000>;
+ opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@216000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <216000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1150>;
+ };
+
+ opp@227000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <227000000>;
+ opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@267000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <267000000>;
+ opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@334000000,1250 {
+ opp-microvolt = <1250000 1250000 1350000>;
+ opp-hz = /bits/ 64 <334000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1250>;
+ };
+
+ opp@378000000,1250 {
+ opp-microvolt = <1250000 1250000 1350000>;
+ opp-hz = /bits/ 64 <378000000>;
+ opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
+ };
+ };
+
+ se_dvfs_opp_table: se-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@267000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <267000000>;
+ opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@285000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <285000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@304000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <304000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@332000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <332000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@361000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <361000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@380000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <380000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1150>;
+ };
+
+ opp@408000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <408000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1150>;
+ };
+
+ opp@416000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <416000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@446000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <446000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@484000000,1250 {
+ opp-microvolt = <1250000 1250000 1350000>;
+ opp-hz = /bits/ 64 <484000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1250>;
+ };
+
+ opp@520000000,1300 {
+ opp-microvolt = <1300000 1300000 1350000>;
+ opp-hz = /bits/ 64 <520000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1300>;
+ };
+
+ opp@600000000,1350 {
+ opp-microvolt = <1350000 1350000 1350000>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1350>;
+ };
+
+ opp@625000000,1250 {
+ opp-microvolt = <1250000 1250000 1350000>;
+ opp-hz = /bits/ 64 <625000000>;
+ opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
+ };
+ };
+
+ ndflash_dvfs_opp_table: ndflash-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@120000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <120000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@200000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <200000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1150>;
+ };
+ };
+
+ nor_dvfs_opp_table: nor-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@108000000,1250 {
+ opp-microvolt = <1250000 1250000 1350000>;
+ opp-hz = /bits/ 64 <108000000>;
+ opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
+ };
+
+ opp@115000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <115000000>;
+ opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@130000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <130000000>;
+ opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@133000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <133000000>;
+ opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1150>;
+ };
+ };
+
+ pcie_dvfs_opp_table: pcie-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@250000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <250000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ pll_c_dvfs_opp_table: pll_c-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@533000000,950 {
+ opp-microvolt = <950000 950000 1350000>;
+ opp-hz = /bits/ 64 <533000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp@667000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <667000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@800000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <800000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@1066000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <1066000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@1200000000,1350 {
+ opp-microvolt = <1350000 1350000 1350000>;
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1350>;
+ };
+ };
+
+ pll_e_dvfs_opp_table: pll_e-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@100000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <100000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ pll_m_dvfs_opp_table: pll_m-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@533000000,950 {
+ opp-microvolt = <950000 950000 1350000>;
+ opp-hz = /bits/ 64 <533000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp@667000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <667000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@800000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <800000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@1066000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <1066000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1200>;
+ };
+ };
+
+ pwm_dvfs_opp_table: pwm-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@408000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <408000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ sata_dvfs_opp_table: sata-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@216000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <216000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ sata_oob_dvfs_opp_table: sata_oob-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@216000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <216000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ sbc1_dvfs_opp_table: sbc1-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@52000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <52000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@60000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <60000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@100000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <100000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1200>;
+ };
+ };
+
+ sbc2_dvfs_opp_table: sbc2-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@52000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <52000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@60000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <60000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@100000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <100000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1200>;
+ };
+ };
+
+ sbc3_dvfs_opp_table: sbc3-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@52000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <52000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@60000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <60000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@100000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <100000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1200>;
+ };
+ };
+
+ sbc4_dvfs_opp_table: sbc4-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@52000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <52000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@60000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <60000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@100000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <100000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1200>;
+ };
+ };
+
+ sbc5_dvfs_opp_table: sbc5-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@52000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <52000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@60000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <60000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@100000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <100000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1200>;
+ };
+ };
+
+ sbc6_dvfs_opp_table: sbc6-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@52000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <52000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@60000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <60000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@100000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <100000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1200>;
+ };
+ };
+
+ sdmmc1_dvfs_opp_table: sdmmc1-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@104000000,950 {
+ opp-microvolt = <950000 950000 1350000>;
+ opp-hz = /bits/ 64 <104000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp@208000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <208000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1200>;
+ };
+ };
+
+ sdmmc3_dvfs_opp_table: sdmmc3-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@104000000,950 {
+ opp-microvolt = <950000 950000 1350000>;
+ opp-hz = /bits/ 64 <104000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_950>;
+ };
+
+ opp@208000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <208000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1200>;
+ };
+ };
+
+ spdif_out_dvfs_opp_table: spdif-out-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@26000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <26000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ tvdac_dvfs_opp_table: tvdac-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@220000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <220000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ tvo_dvfs_opp_table: tvo-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@297000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <297000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1050>;
+ };
+ };
+
+ usbd_dvfs_opp_table: usbd-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@480000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ usb2_dvfs_opp_table: usb2-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@480000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ usb3_dvfs_opp_table: usb3-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@480000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x000F>;
+ required-opps = <&core_opp_1000>;
+ };
+ };
+
+ vde_dvfs_opp_table: vde-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@228000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <228000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@247000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <247000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@275000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <275000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@304000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <304000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@332000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <332000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@352000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <352000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@380000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <380000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1150>;
+ };
+
+ opp@400000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <400000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1150>;
+ };
+
+ opp@416000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <416000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@437000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <437000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@484000000,1250 {
+ opp-microvolt = <1250000 1250000 1350000>;
+ opp-hz = /bits/ 64 <484000000>;
+ opp-supported-hw = <0x000C>;
+ required-opps = <&core_opp_1250>;
+ };
+
+ opp@520000000,1300 {
+ opp-microvolt = <1300000 1300000 1350000>;
+ opp-hz = /bits/ 64 <520000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1300>;
+ };
+
+ opp@600000000,1350 {
+ opp-microvolt = <1350000 1350000 1350000>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1350>;
+ };
+ };
+
+ vi_dvfs_opp_table: vi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@216000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <216000000>;
+ opp-supported-hw = <0x0003>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@219000000,1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <219000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp@267000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <267000000>;
+ opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@285000000,1050 {
+ opp-microvolt = <1050000 1050000 1350000>;
+ opp-hz = /bits/ 64 <285000000>;
+ opp-supported-hw = <0x0001>;
+ required-opps = <&core_opp_1050>;
+ };
+
+ opp@300000000,1100 {
+ opp-microvolt = <1100000 1100000 1350000>;
+ opp-hz = /bits/ 64 <300000000>;
+ opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1100>;
+ };
+
+ opp@371000000,1150 {
+ opp-microvolt = <1150000 1150000 1350000>;
+ opp-hz = /bits/ 64 <371000000>;
+ opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1150>;
+ };
+
+ opp@409000000,1200 {
+ opp-microvolt = <1200000 1200000 1350000>;
+ opp-hz = /bits/ 64 <409000000>;
+ opp-supported-hw = <0x0006>;
+ required-opps = <&core_opp_1200>;
+ };
+
+ opp@425000000,1250 {
+ opp-microvolt = <1250000 1250000 1350000>;
+ opp-hz = /bits/ 64 <425000000>;
+ opp-supported-hw = <0x0004>;
+ required-opps = <&core_opp_1250>;
+ };
+
+ opp@470000000,1250 {
+ opp-microvolt = <1250000 1250000 1350000>;
+ opp-hz = /bits/ 64 <470000000>;
+ opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index c577c191be4b..6e760faaff29 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -54,6 +54,8 @@ pcie@3000 {
<&tegra_car 72>,
<&tegra_car 74>;
reset-names = "pex", "afi", "pcie_x";
+ operating-points-v2 = <&pcie_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
pci@1,0 {
@@ -123,6 +125,8 @@ host1x@50000000 {
resets = <&tegra_car 28>;
reset-names = "host1x";
iommus = <&mc TEGRA_SWGROUP_HC>;
+ operating-points-v2 = <&host1x_dvfs_opp_table>;
+ power-domains = <&pd_heg>;
#address-cells = <1>;
#size-cells = <1>;
@@ -136,6 +140,7 @@ mpe@54040000 {
clocks = <&tegra_car TEGRA30_CLK_MPE>;
resets = <&tegra_car 60>;
reset-names = "mpe";
+ power-domains = <&pd_mpe>;
iommus = <&mc TEGRA_SWGROUP_MPE>;
};
@@ -147,6 +152,7 @@ vi@54080000 {
clocks = <&tegra_car TEGRA30_CLK_VI>;
resets = <&tegra_car 20>;
reset-names = "vi";
+ power-domains = <&pd_venc>;
iommus = <&mc TEGRA_SWGROUP_VI>;
};
@@ -158,6 +164,7 @@ epp@540c0000 {
clocks = <&tegra_car TEGRA30_CLK_EPP>;
resets = <&tegra_car 19>;
reset-names = "epp";
+ power-domains = <&pd_heg>;
iommus = <&mc TEGRA_SWGROUP_EPP>;
};
@@ -169,6 +176,7 @@ isp@54100000 {
clocks = <&tegra_car TEGRA30_CLK_ISP>;
resets = <&tegra_car 23>;
reset-names = "isp";
+ power-domains = <&pd_venc>;
iommus = <&mc TEGRA_SWGROUP_ISP>;
};
@@ -180,6 +188,8 @@ gr2d@54140000 {
clocks = <&tegra_car TEGRA30_CLK_GR2D>;
resets = <&tegra_car 21>;
reset-names = "2d";
+ operating-points-v2 = <&gr2d_dvfs_opp_table>;
+ power-domains = <&pd_heg>;
iommus = <&mc TEGRA_SWGROUP_G2>;
};
@@ -193,6 +203,9 @@ gr3d@54180000 {
resets = <&tegra_car 24>,
<&tegra_car 98>;
reset-names = "3d", "3d2";
+ operating-points-v2 = <&gr3d_dvfs_opp_table>;
+ power-domains = <&pd_3d0>, <&pd_3d1>;
+ power-domain-names = "3d0", "3d1";
iommus = <&mc TEGRA_SWGROUP_NV>,
<&mc TEGRA_SWGROUP_NV2>;
@@ -207,6 +220,8 @@ dc@54200000 {
clock-names = "dc", "parent";
resets = <&tegra_car 27>;
reset-names = "dc";
+ operating-points-v2 = <&disp1_dvfs_opp_table>;
+ power-domains = <&pd_core>;
iommus = <&mc TEGRA_SWGROUP_DC>;
@@ -237,6 +252,8 @@ dc@54240000 {
clock-names = "dc", "parent";
resets = <&tegra_car 26>;
reset-names = "dc";
+ operating-points-v2 = <&disp2_dvfs_opp_table>;
+ power-domains = <&pd_core>;
iommus = <&mc TEGRA_SWGROUP_DCB>;
@@ -267,6 +284,8 @@ hdmi@54280000 {
clock-names = "hdmi", "parent";
resets = <&tegra_car 51>;
reset-names = "hdmi";
+ operating-points-v2 = <&hdmi_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -275,6 +294,8 @@ tvo@542c0000 {
reg = <0x542c0000 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_TVO>;
+ operating-points-v2 = <&tvo_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -286,6 +307,8 @@ dsi@54300000 {
clock-names = "dsi", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
+ operating-points-v2 = <&dsia_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -297,6 +320,8 @@ dsi@54400000 {
clock-names = "dsi", "parent";
resets = <&tegra_car 84>;
reset-names = "dsi";
+ operating-points-v2 = <&dsib_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
};
@@ -357,6 +382,40 @@ tegra_car: clock@60006000 {
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+
+ tegra-clocks {
+ sclk {
+ compatible = "nvidia,tegra30-sclk",
+ "nvidia,tegra-clock";
+ operating-points-v2 = <&sclk_dvfs_opp_table>;
+ clocks = <&tegra_car TEGRA30_CLK_SCLK>;
+ power-domains = <&pd_core>;
+ };
+
+ pll_c {
+ compatible = "nvidia,tegra30-pllc",
+ "nvidia,tegra-clock";
+ operating-points-v2 = <&pll_c_dvfs_opp_table>;
+ clocks = <&tegra_car TEGRA30_CLK_PLL_C>;
+ power-domains = <&pd_core>;
+ };
+
+ pll_e {
+ compatible = "nvidia,tegra30-plle",
+ "nvidia,tegra-clock";
+ operating-points-v2 = <&pll_e_dvfs_opp_table>;
+ clocks = <&tegra_car TEGRA30_CLK_PLL_E>;
+ power-domains = <&pd_core>;
+ };
+
+ pll_m {
+ compatible = "nvidia,tegra30-pllm",
+ "nvidia,tegra-clock";
+ operating-points-v2 = <&pll_m_dvfs_opp_table>;
+ clocks = <&tegra_car TEGRA30_CLK_PLL_M>;
+ power-domains = <&pd_core>;
+ };
+ };
};
flow-controller@60007000 {
@@ -467,6 +526,8 @@ vde@6001a000 {
reset-names = "vde", "mc";
resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
iommus = <&mc TEGRA_SWGROUP_VDE>;
+ operating-points-v2 = <&vde_dvfs_opp_table>;
+ power-domains = <&pd_vde>;
};
apbmisc@70000800 {
@@ -564,6 +625,8 @@ gmi@70009000 {
clock-names = "gmi";
resets = <&tegra_car 42>;
reset-names = "gmi";
+ operating-points-v2 = <&nor_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -574,6 +637,8 @@ pwm: pwm@7000a000 {
clocks = <&tegra_car TEGRA30_CLK_PWM>;
resets = <&tegra_car 17>;
reset-names = "pwm";
+ operating-points-v2 = <&pwm_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -675,6 +740,8 @@ spi@7000d400 {
reset-names = "spi";
dmas = <&apbdma 15>, <&apbdma 15>;
dma-names = "rx", "tx";
+ operating-points-v2 = <&sbc1_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -689,6 +756,8 @@ spi@7000d600 {
reset-names = "spi";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
+ operating-points-v2 = <&sbc2_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -703,6 +772,8 @@ spi@7000d800 {
reset-names = "spi";
dmas = <&apbdma 17>, <&apbdma 17>;
dma-names = "rx", "tx";
+ operating-points-v2 = <&sbc3_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -717,6 +788,8 @@ spi@7000da00 {
reset-names = "spi";
dmas = <&apbdma 18>, <&apbdma 18>;
dma-names = "rx", "tx";
+ operating-points-v2 = <&sbc4_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -731,6 +804,8 @@ spi@7000dc00 {
reset-names = "spi";
dmas = <&apbdma 27>, <&apbdma 27>;
dma-names = "rx", "tx";
+ operating-points-v2 = <&sbc5_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -745,6 +820,8 @@ spi@7000de00 {
reset-names = "spi";
dmas = <&apbdma 28>, <&apbdma 28>;
dma-names = "rx", "tx";
+ operating-points-v2 = <&sbc6_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -764,6 +841,72 @@ tegra_pmc: pmc@7000e400 {
clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
#clock-cells = <1>;
+
+ pd_core: core-domain {
+ operating-points-v2 = <&core_opp_table>;
+ #power-domain-cells = <0>;
+ };
+
+ powergates {
+ pd_3d0: 3d0 {
+ clocks = <&tegra_car TEGRA30_CLK_GR3D>;
+ resets = <&mc TEGRA30_MC_RESET_3D>,
+ <&tegra_car TEGRA30_CLK_GR3D>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_3d1: 3d1 {
+ clocks = <&tegra_car TEGRA30_CLK_GR3D2>;
+ resets = <&mc TEGRA30_MC_RESET_3D2>,
+ <&tegra_car TEGRA30_CLK_GR3D2>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_venc: venc {
+ clocks = <&tegra_car TEGRA30_CLK_ISP>,
+ <&tegra_car TEGRA30_CLK_VI>,
+ <&tegra_car TEGRA30_CLK_CSI>;
+ resets = <&mc TEGRA30_MC_RESET_ISP>,
+ <&mc TEGRA30_MC_RESET_VI>,
+ <&tegra_car TEGRA30_CLK_ISP>,
+ <&tegra_car 20 /* VI */>,
+ <&tegra_car TEGRA30_CLK_CSI>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_vde: vdec {
+ clocks = <&tegra_car TEGRA30_CLK_VDE>;
+ resets = <&mc TEGRA30_MC_RESET_VDE>,
+ <&tegra_car TEGRA30_CLK_VDE>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_mpe: mpe {
+ clocks = <&tegra_car TEGRA30_CLK_MPE>;
+ resets = <&mc TEGRA30_MC_RESET_MPE>,
+ <&tegra_car TEGRA30_CLK_MPE>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_heg: heg {
+ clocks = <&tegra_car TEGRA30_CLK_GR2D>,
+ <&tegra_car TEGRA30_CLK_EPP>,
+ <&tegra_car TEGRA30_CLK_HOST1X>;
+ resets = <&mc TEGRA30_MC_RESET_2D>,
+ <&mc TEGRA30_MC_RESET_EPP>,
+ <&mc TEGRA30_MC_RESET_HC>,
+ <&tegra_car TEGRA30_CLK_GR2D>,
+ <&tegra_car TEGRA30_CLK_EPP>,
+ <&tegra_car TEGRA30_CLK_HOST1X>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+ };
};
mc: memory-controller@7000f000 {
@@ -784,6 +927,7 @@ emc: memory-controller@7000f400 {
reg = <0x7000f400 0x400>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_EMC>;
+ power-domains = <&pd_core>;
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&emc_icc_dvfs_opp_table>;
@@ -798,6 +942,8 @@ fuse@7000f800 {
clock-names = "fuse";
resets = <&tegra_car 39>;
reset-names = "fuse";
+ operating-points-v2 = <&fuse_burn_dvfs_opp_table>;
+ power-domains = <&pd_core>;
};
hda@70030000 {
@@ -906,6 +1052,8 @@ mmc@78000000 {
clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
+ operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -928,6 +1076,8 @@ mmc@78000400 {
clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
+ operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -952,6 +1102,8 @@ usb@7d000000 {
reset-names = "usb";
nvidia,needs-double-reset;
nvidia,phy = <&phy1>;
+ operating-points-v2 = <&usbd_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -991,6 +1143,8 @@ usb@7d004000 {
resets = <&tegra_car 58>;
reset-names = "usb";
nvidia,phy = <&phy2>;
+ operating-points-v2 = <&usb2_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -1029,6 +1183,8 @@ usb@7d008000 {
resets = <&tegra_car 59>;
reset-names = "usb";
nvidia,phy = <&phy3>;
+ operating-points-v2 = <&usb3_dvfs_opp_table>;
+ power-domains = <&pd_core>;
status = "disabled";
};
--
2.30.2
next prev parent reply other threads:[~2021-07-01 23:30 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-01 23:26 [PATCH v7 00/37] NVIDIA Tegra power management patches for 5.15 Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 01/37] soc/tegra: pmc: Temporarily disable PMC state syncing Dmitry Osipenko
2021-08-12 16:02 ` Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 02/37] soc/tegra: pmc: Implement attach_dev() of power domain drivers Dmitry Osipenko
2021-08-02 14:48 ` Ulf Hansson
2021-08-02 18:23 ` Dmitry Osipenko
2021-08-04 9:59 ` Ulf Hansson
2021-08-04 21:16 ` Dmitry Osipenko
2021-08-09 14:15 ` Ulf Hansson
2021-08-09 23:56 ` Dmitry Osipenko
2021-08-10 10:51 ` Ulf Hansson
2021-08-11 19:30 ` Dmitry Osipenko
2021-08-11 22:41 ` Dmitry Osipenko
2021-08-12 1:40 ` Dmitry Osipenko
2021-08-12 11:17 ` Ulf Hansson
2021-08-12 16:24 ` Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 03/37] soc/tegra: Don't print error message when OPPs not available Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 04/37] soc/tegra: Add devm_tegra_core_dev_init_opp_table_simple() Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 05/37] dt-bindings: clock: tegra-car: Document new tegra-clocks node Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 06/37] clk: tegra: Support runtime PM and power domain Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 07/37] dt-bindings: host1x: Document OPP and power domain properties Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 08/37] dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 09/37] gpu: host1x: Add host1x_channel_stop() Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 10/37] gpu: host1x: Add runtime PM support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 11/37] gpu: host1x: Add stub driver for MPE, VI, EPP and ISP Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 12/37] drm/tegra: dc: Support OPP and SoC core voltage scaling Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 13/37] drm/tegra: hdmi: Add OPP support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 14/37] drm/tegra: gr2d: Support OPP and power management Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 15/37] drm/tegra: gr3d: " Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 16/37] drm/tegra: vic: Stop channel before suspending Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 17/37] usb: chipidea: tegra: Add runtime PM support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 18/37] bus: tegra-gmi: " Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 19/37] pwm: tegra: Add runtime PM and OPP support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 20/37] mmc: sdhci-tegra: " Dmitry Osipenko
2021-07-02 3:39 ` kernel test robot
2021-07-01 23:27 ` [PATCH v7 21/37] mtd: rawnand: tegra: Add runtime PM support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 22/37] soc/tegra: fuse: Clear fuse->clk on driver probe failure Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 23/37] soc/tegra: fuse: Add runtime PM support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 24/37] soc/tegra: fuse: Enable fuse clock on suspend Dmitry Osipenko
2021-07-21 16:00 ` Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 25/37] clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 26/37] spi: tegra20-slink: Improve runtime PM usage Dmitry Osipenko
2021-07-02 8:29 ` kernel test robot
2021-07-01 23:27 ` [PATCH v7 27/37] spi: tegra20-slink: Add OPP support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 28/37] memory: tegra20-emc: Add minimal runtime PM support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 29/37] memory: tegra30-emc: " Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 30/37] media: dt: bindings: tegra-vde: Convert to schema Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 31/37] media: dt: bindings: tegra-vde: Document OPP and power domain Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 32/37] media: staging: tegra-vde: Support generic " Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 33/37] ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees Dmitry Osipenko
2021-07-01 23:27 ` Dmitry Osipenko [this message]
2021-07-01 23:27 ` [PATCH v7 35/37] ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 36/37] ARM: tegra: Add Memory Client resets to Tegra30 " Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 37/37] soc/tegra: pmc: Enable core domain support on Tegra20 and Tegra30 Dmitry Osipenko
2021-07-09 13:01 ` [PATCH v7 00/37] NVIDIA Tegra power management patches for 5.15 Ulf Hansson
2021-07-09 21:23 ` Dmitry Osipenko
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